NEC V850E/Dx3 Preliminary User's Manual page 171

Clock Generator
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(3) WATCH mode
In WATCH mode, the clock supply for the CPU system and the majority of
peripherals is stopped.
The main oscillator continues operation. PLL and SSCG are stopped. By
default, ring oscillator and sub oscillator operation is not affected. For
exceptions see "Ring and sub oscillator operation" on page 184.
Table 4-26 Clock Generator status in WATCH mode
Item
Main oscillator
Sub oscillator
Ring oscillator
SSCG
PLL
VBCLK (CPU system)
IICLK
PCLK0, PCLK1
PCLK2...PCLK15
SPCLK0, SPCLK1
SPCLK2...SPCLK15
FOUTCLK
WTCLK / LCDCLK
WDTCLK
WCTCLK
The WATCH mode can be released by
• the unmasked maskable interrupts INTPn, INTCnWUP, INTWTnUV,
INTTM01, INTVCn, INTCBnR
• NMI0, NMIWDT
• RESET, RESPOC, RESWDT, RESCMM, RESCMS
On WATCH mode release, the CPU starts operation using the following
clocks:
• if PSM.OSCDIS = 1: sub clock source selected before WATCH mode was
entered, that means, either ring oscillator or sub oscillator (defined by
PCC.SOSCP)
• if PSM.OSCDIS = 0: main oscillator
If the ring oscillator was stopped before entering the WATCH mode, the
oscillation stabilization time for the ring oscillator is ensured by hardware after
WATCH mode release.
PLL and SSCG remain stopped after WATCH release.
Peripheral clock supply is switched to main oscillator supply, if
PSM.OSCDIS = 0, otherwise the ring oscillator is used for peripheral clocks.
Preliminary User's Manual U17566EE1V2UM00
Status Remarks
unchanged/stopped Stopped if PSM.OSCDIS = 1
operates
operates/stopped Stopped if WCC.ROSTP = 1
stopped
stopped
stopped
stopped
stopped
stopped
stopped
stopped
unchanged/stopped Stopped, if the selected clock
source stops
unchanged/stopped Stopped, if the selected clock
source stops
unchanged/stopped Stopped, if the selected clock
source stops
unchanged/stopped Depends on clock selector
PSM.CMODE
Chapter 4
171