NEC V850E/Dx3 Preliminary User's Manual page 364

Chapter 11
364
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(d) Operation of TPnCCR1 register
Count clock
selection
TPnCE bit
Figure 11-5 Configuration of TPnCCR1 register
If the set value of the TPnCCR1 register is less than the set value of the
TPnCCR0 register, the INTTPnCC1 signal is generated once per cycle. At
the same time, the output of the TOPn1 pin is inverted.
The TOPn1 pin outputs a square wave with the same cycle as that output
by the TOPn0 pin.
Preliminary User's Manual U17566EE1V2UM00
16-bit Timer/Event Counter P (TMP)
TPnCCR1 register
CCR1 buffer register
controller
Match signal
Clear
16-bit counter
controller
Match signal
CCR0 buffer register
TPnCCR0 register
Output
TOPn1 pin
INTTPnCC1 signal
Output
TOPn0 pin
INTTPnCC0 signal