In-Service Priority Register (Ispr); Id Flag - NEC Renesas V850/SC1 User Manual

32-bit single-chip microcontrollers
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7.3.5 In-service priority register (ISPR)

This register holds the priority level of the maskable interrupt currently requesting acknowledgement. When the
interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set (1)
and remains set while the interrupt is being serviced.
When the RETI instruction is executed, the bit corresponding to the interrupt request having the highest priority is
automatically reset (0) by hardware. However, it is not reset (0) when execution is returned from non-maskable
interrupt servicing or exception processing.
This register is read-only, in 8- or 1-bit units.
After reset: 00H
R
Symbol
<7>
<6>
ISPR
ISPR7
ISPR6
ISPRn
0
Interrupt request with priority n not acknowledged
1
Interrupt request with priority n acknowledged
Remark
n: 0 to 7 (priority level)

7.3.6 ID flag

The interrupt disable flag (ID) controls the enabling and disabling of maskable interrupt requests, and is assigned
to the PSW.
After reset: 00000020H
Symbol
31
PSW
ID
0
Maskable interrupt acknowledgement enabled
1
Maskable interrupt acknowledgement disabled (pending)
Note Interrupt disable flag (ID) function
ID is set (1) by the DI instruction and reset (0) by the EI instruction. Its value is also modified by the RETI
instruction or LDSR instruction when referencing the PSW.
Non-maskable interrupts and exceptions are acknowledged regardless of this flag. When a maskable
interrupt is acknowledged, the ID flag is automatically set (1) by hardware.
An interrupt request generated during the acknowledgement disabled period (ID = 1) can be acknowledged
when the xxIFn bit of xxICn is set (1), and the ID flag is reset (0).
Remark
xx: Identifying name of each peripheral unit (see Table 7-2)
n:
Peripheral unit number (see Table 7-2)
CHAPTER 7
INTERRUPT/EXCEPTION PROCESSING FUNCTION
Address: FFFFF166H
<5>
<4>
ISPR5
ISPR4
Indicates priority of interrupt currently requesting acknowledgement
Figure 7-9. ID Flag
0
Specifies maskable interrupt servicing
User's Manual U15109EJ3V0UD
<3>
<2>
<1>
ISPR3
ISPR2
ISPR1
8
7
6
5
4
3
NP EP ID SAT CY OV
Note
<0>
ISPR0
2
1
0
S
Z
237

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