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B.10 CAN Controller
Register
CnMDATA[7:0]m
Access
R
⎧
T
=
SUWL
+
VSWL
Formular
⎨
a
⎩
Access
8-bit Write
⎧
T
=
SUWL
+
VSWL
Formular
⎨
a
⎩
Access
16-bit Write
⎧
T
=
SUWL
+
VSWL
Formular
⎨
a
⎩
Register
CnRGPT, CnTGPT, CnLIPT, CnLOPT
Access
R
⎧
T
=
SUWL
+
VSWL
⎨
Formular
a
⎩
Register
all other
Access
R/W
⎧
T
=
SUWL
+
VSWL
Formular
⎨
a
⎩
B.11 A/D Converter
Register
ADAM0[2:0], ADACR0n
Access
R
⎧
T
=
SUWL
+
VSWL
⎨
Formular
a
⎩
Access
W
(
T
=
SUWL
+
VSWL
Formular
a
Register
all other
Access
R/W
(
T
=
SUWL
+
VSWL
Formular
a
Preliminary User's Manual U17566EE1V2UM00
⋅
4 f
VBCLK
------------------------------------------------------ -
+ +
3
ru
(
) f
⋅
2
+
VSWL
PCLK0
⋅
5 f
VBCLK
------------------------------------------------------ -
+ +
3
ru
(
) f
⋅
2
+
VSWL
PCLK0
⋅
3 f
VBCLK
------------------------------------------------------ -
+ +
3
ru
(
) f
⋅
2
+
VSWL
PCLK0
⋅
4 f
VBCLK
+ +
3
ru
------------------------------------------------------ -
(
) f
⋅
2
+
VSWL
PCLK0
⋅
2 f
VBCLK
------------------------------------------------------ -
+ +
3
ru
(
) f
⋅
2
VSWL
+
PCLK0
⋅
2 f
VBCLK
+ +
3
ru
--------------------------------------------------------- -
(
) f
⋅
2
+
VSWL
SPCLK0
1
)
⋅
+
3
----------------- -
f
VBCLK
1
)
⋅
----------------- -
+
3
f
VBCLK
Appendix B
⎫
1
⋅
(
)
⋅
----------------- -
2
+
VSWL
⎬
f
⎭
VBCLK
⎫
1
⋅
(
)
⋅
----------------- -
2
+
VSWL
⎬
f
⎭
VBCLK
⎫
1
⋅
(
)
⋅
----------------- -
2
+
VSWL
⎬
f
⎭
VBCLK
⎫
1
⋅
(
)
⋅
2
+
VSWL
----------------- -
⎬
f
⎭
VBCLK
⎫
1
⋅
(
)
⋅
----------------- -
2
+
VSWL
⎬
f
⎭
VBCLK
⎫
1
⋅
(
)
⋅
+
1
2
+
VSWL
----------------- -
⎬
f
⎭
VBCLK
917
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