NEC V850E/Dx3 Preliminary User's Manual page 173

Clock Generator
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(5) STOP mode
In STOP mode, all clock sources are stopped, except sub and ring oscillator.
These can be configured in register WCC to stop as well. No clock is available,
and no internal self-timed processes operates.
Table 4-28 Clock Generator status in STOP mode
Item
Main oscillator
Sub oscillator
Ring oscillator
SSCG
PLL
VBCLK (CPU system)
IICLK
PCLK0, PCLK1
PCLK2...PCLK15
SPCLK0, SPCLK1
SPCLK2...SPCLK15
FOUTCLK
WTCLK / LCDCLK
WDTCLK
WCTCLK
The STOP mode can be released by
• the unmasked maskable interrupts INTPn, INTCnWUP, INTVCn, INTCBnR
• NMI0, NMIWDT
• RESET, RESPOC, RESWDT, RESCMM, RESCMS
On STOP mode release, the CPU clock and peripheral clocks are supplied by
the main oscillator.
(6) Clock status summary
Table 4-29 on page 174 summarizes the status of all clocks delivered by the
Clock Generator in the different states.
"Normal" describes all status except reset and power save modes.
The HALT mode is not listed in the table. It does not change any of the table
items, but stoppes only the CPU core operation.
Below the table you find the explanation of the terms used in the table.
Preliminary User's Manual U17566EE1V2UM00
Status Remark
stopped
operates/stopped Stopped if WCC.SOSTP = 1
operates/stopped Stopped if WCC.ROSTP = 1
stopped
stopped
stopped
stopped
stopped
stopped
stopped
stopped
stopped
stopped
unchanged/stopped Stopped, if the selected clock
source stops
stopped
Chapter 4
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