NEC V850E/Dx3 Preliminary User's Manual page 817

LCD Controller/Driver (LCD-C/D)
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(2) Segment Signals
Segment signals correspond to the contents of the 40 LCD display control
registers SEGREG0k. Bits 0 to 3 of these registers are read in synchronization
with the common signals COM0 to COM3, this means bit 0 is read in
synchronization with common signal COM0 and so on.
• If the value of the bit is 1 while the common signal is at selection level, the
corresponding segment signal is set to selection level.
• If the value of the bit is 0 while the common signal is at selection level, the
corresponding segment signal is set to non-selection level.
Figure 22-5 shows the selection and non-selection level of segment signals.
Figure 22-5 Selection level and non-selection level of segment signals
T = duty cycle time.
The table below shows the relation of the bits in registers SEGREG0k (k = 0 to
39) with common signals COM0 to COM3 and segment output signals SEG00
to SEG39.
SEGREG00
0
SEGREG00
1
SEGREG00
2
•
•
•
SEGREG03
8
SEGREG03
9
Each of the bits 0 to 4 represents the status of one LCD segment. Setting the
bit to 1 will make the LCD segment visible.
For example, setting bit SEGREG02[3] to 1 will make the LCD segment visible,
that is controlled by the signal pair SEG2 and COM3.
Preliminary User's Manual U17566EE1V2UM00
Segment signal
T
7 6 5 4 3
•
•
•
↑
COM3 COM2 COM1 COM0
Chapter 22
V
LC0
V
LC1
V
LCD
V
LC2
V
SS1
T
2 1 0
→
SEG0
→
SEG1
→
SEG2
→
SEG38
→
SEG39
↑ ↑ ↑
•
•
•
817