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Clock Generator
Bit position
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1
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CGSTAT - Clock Generator status register
The 8-bit CGSTAT register is read-only. It indicates the status of the main
oscillator and the status of the clock generator after wake-up from power save
mode.
Access
This register can be read in 8-bit units.
Address
FFFF F824
.
H
Initial Value
0000 1101
. The register is initialized by any reset.
B
7
CMPLPSM
R
Table 4-5
CGSTAT register contents
Bit name
Function
CMPLPSM
Completed power save mode entry:
0: Power save mode configuration not completed.
1: Power save mode configuration completed.
This bit is cleared when the clock generator has accepted a power save mode
request. However if CGSTAT.CMLPSM was already 0 before a power save mode
request it can not be used as an indicator that the clock generator has accepted
this power save mode request.
This bit is set when the clock generator has completely set up it's power save
mode configuration, i.e. all registers are set up, PLL and SSCG are switched off.
However if CGSTAT.CMLPSM was already 1 before a power save mode request it
can not be used as the only indicator that the clock generator has completed
power save mode configuration.
If the clock generator has not accepted a power save mode request this bit
remains unchanged.
Refer also to ""CPU operation after power save mode release" on page 181".
OSCSTAT
Main oscillator status indicator (determined by counter):
0: Main oscillator has not settled.
1: Main oscillator has stabilized.
The OSCSTAT flag is cleared whenever the main oscillator is switched to stand-by
mode due to entering the Sub-WATCH or STOP mode.
After the main oscillator is restarted, the oscillation stabilization counter will count
up from 0 to 40.960 (approx. 10ms @ 4 MHz) to assure stable oscillator
operation. When the oscillation stabilization counter reaches 40.960, the counter
is stopped, and the OSCSTAT flag is set.
Preliminary User's Manual U17566EE1V2UM00
6
5
4
3
0
0
0
1
R
R
R
R
Chapter 4
2
1
0
1
OSCSTAT
1
R
R
R
139
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