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Chapter 8
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2. Set the DMA request bit DTFRn.DRQn = 0 in parallel to changing
DTFRn.IFCn[2:0], i.e. within the same write operation. Thus DTFRn must
be written in 8-bit access mode. Do not change DTFRn.IFCn[2:0] with
single-bit instructions.
The following list details the functions of the individual DMA trigger sources
referenced in the above table.
• INTCB2R...INTCB0R
The receive interrupts of the Clocked Serial Interfaces CSIB2...CSIB0 are
used as DMA trigger sources. In case of a receive overflow condition no
DMA trigger will be issued. The receive error interrupt of the respective
CSIB INTCBnRE should be enabled to inform the application software about
the overflow condition.
• INTCB2T...INTCB0T
The transmit interrupts of the Clocked Serial Interfaces CSIB2...CSIB0 are
used as DMA trigger sources.
• INTUA1R, INTUA0R
The receive interrupts of the Asynchronous Serial Interfaces UARTA1 or
UARTA0 are used as DMA trigger sources.
In case of a receive overflow, or a framing or parity error condition, no DMA
trigger will be issued. The receive error interrupt INTUAnRE of the
respective UARTn should be enabled to inform the application software
about the error condition. These interrupts are also generated upon
reception of an SBF in LIN mode.
• INTUA1T, INTUA0T
The transmit interrupts of the Asynchronous Serial Interfaces UARTA1 or
UARTA0 are used as DMA trigger sources.
• INTLCD
The interrupt signal of the LCD Bus Interface macro is used to trigger the
DMA transfer.
• INTIIC0, INTIIC1
2
The interrupts of the I
C Interfaces IIC0, IIC1 are used to trigger the
respective DMA channel.
DRQn
DMA request
0
No DMA transfer request is pending for channel n
1
DMA transfer request is pending for channel n
DOFLn
DMA request overflow
0
DMA transfer request overflow did not occur for channel n
1
DMA transfer request overflow occurred for channel n
DMACTn
DMA active count
DMACTn=0 must be set if internal RAM is not specified as source or
0
destination
DMACTn=1 must be set if internal RAM is specified as source or
1
destination
Preliminary User's Manual U17566EE1V2UM00
DMA Controller (DMAC)
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