NEC V850E/Dx3 Preliminary User's Manual page 295

Bus and Memory Control (BCU, MEMC)
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(2) Read operation with address setup wait states and idle state insertion
TASW
BCLK
A[23:0] (output) Off-page address
CSk (output)
RD (output)
WR (output)
D[7:0] (I/O)
D[15:0] (I/O)
WAIT (input)
00B
BCC.BCk[1:0]
Figure 7-20 Reading page ROM with address setup wait states and idle state
insertion
Register settings:
• BCTm.BTk0 = 1 (connected external device is page ROM)
• ASC.ACk[1:0] = 01
• DWCm.DWk[2:0] = 000
access inserted)
• PRC.PRW[2:0] = 000
access inserted)
• BCC.BCk[1:0] : see Figure 7-20
Note 1. The circles indicate the sampling timing.
2. The broken line indicates the high-impedance state (bus is not driven).
Preliminary User's Manual U17566EE1V2UM00
T1 T2 TASW TO1
On-page address
Data
01B
(one address setup wait state inserted)
B
(no programmable data wait states for off-page
B
(no programmable data wait states for on-page
B
Chapter 7
TO2 TI
Data
295