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Asynchronous Serial Interface (UARTA)
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16.6 Baud Rate Generator
The dedicated baud rate generator consists of a source clock selector block
and an 8-bit programmable counter, and generates a serial clock during
transmission and reception with UARTAn. Regarding the serial clock, a
dedicated baud rate generator output can be selected for each channel.
There is an 8-bit counter for transmission and another one for reception.
16.6.1 Baud Rate Generator configuration
UAnPWR
PCLK1
PCLK2
PCLK3
PCLK4
Selector
PCLK5
PCLK6
PCLK7
PCLK8
UAnCTL1:
UAnCKS2 to UAnCKS0
Figure 16-11
Configuration of baud rate generator
(a) Base clock
When the UAnCTL0.UAnPWR bit is 1, the clock selected by the
UAnCTL1.UAnCKS[2:0] bits is supplied to the 8-bit counter. This clock is
called the base clock. When the UAnPWR bit = 0, f
level.
(b) Serial clock generation
A serial clock can be generated by setting the UAnCTL1 register and the
UAnCTL2 register.
The base clock is selected by UAnCTL1.UAnCKS2 to UAnCTL1.UAnCKS0
bits.
The frequency division value for the 8-bit counter can be set using the
UAnCTL2.UAnBRS[7:0] bits.
Preliminary User's Manual U17566EE1V2UM00
UAnPWR, UAnTXEn bus
(or UAnRXE bit)
8-bit counter
f
UCLK
Match detector
UAnCTL2:
UAnBRS7 to UAnBRS0
Chapter 16
1/2
Baud rate
is fixed to the low
UCLK
533
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