NEC V850E/Dx3 Preliminary User's Manual page 461

16-bit Multi-Purpose Timer G (TMG)
GCCn1 Master register
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(c) When GCCnm is rewritten during operation (m = 1 to 4)
When GCCn1 is rewritten from 5555H to AAAAH, the operation shown below
is performed.
The figure below shows a case where TMGn0 is selected for GCCn1.
ENFG0
Ma tch
TM G n0
GCCn1 Slave register
INTTGnCC1
INTTGnOV0
TOGn1(AL VG 1=1)
TOGn1(AL VG 1=0)
Figure 13-11 Timing when GCCnm is rewritten during operation (free run)
GCCn1 and TMGn0 are selected.
If GCCn1 is rewritten to AAAAH after the second INTCCGn1 is generated as
shown in the figure above, AAAAH is reloaded to the GCCn1 register when the
next overflow occurs.
The next match interrupt (INTCCGn1) is generated when the value of the
counter is AAAAH. The pulse width also matches accordingly.
Preliminary User's Manual U17566EE1V2UM00
FFFFH FFFFH
Ma tch
5555H
5555H
5555H
Chapter 13
FFFFH
Ma tch
AAAAH
AAAAH
AAAAH
461