NEC V850E/Dx3 Preliminary User's Manual page 408

Chapter 11
408
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(2) Operation flow in free-running timer mode
(a) When using capture/compare register as compare register
FFFFH
16-bit counter
D
10
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TOPn0 pin output
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
INTTPnOV signal
TPnOVF bit
<1>
Figure 11-28 Software processing flow in free-running timer mode (compare function)
(1/2)
Preliminary User's Manual U17566EE1V2UM00
D D
00 00
D
D
10
D
11
D
00
D
10
Cleared to 0 by Cleared to 0 by
CLR instruction CLR instruction
<2> <2>
16-bit Timer/Event Counter P (TMP)
D
01 01
D D
11 11
D
01
D
11
Cleared to 0 by
CLR instruction
<2>
<3>