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Chapter 13
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13.10 Precautions Timer Gn
(1)
When POWERn bit of TMGMHn register is set
The rewriting of the CSEn2 to CSEn0 bits of TMGMHn register is prohibited.
These bits set the prescaler for the Timer Gn counter.
The rewriting of the CCSGny bits (y = 0 to 5) is prohibited.
This bits (OCTLGnL and OCTLGnH registers) set the capture mode or the
compare mode to the GCCy register. For the GCCn0 register and the GCCn5
register these bits (TMGMLn register) set the "free run" or "match and clear"
mode of the TMGn0 and TMGn1 counter.
The rewriting of the TMGCMnL and the TMGCMHn register is prohibited.
These registers configure the counter (TMGn0 or TMGn1) for the GCCnm
register (m = 1 to 4) and define the edge detection for the TIGnm input pins
(falling, rising, both).
Even when POWERn bit is set, TOGnm output is switched by switching the
ALVGnm bit of OCTLGnL and OCTLGnH registers.
These bits configure the active level of the TOGnm-pins (m = 1 to 4).
(2)
When POWERn bit and TMGxE bit are set (x = 0, 1)
The rewriting of ALVGnm is prohibited (m = 1 to 4).
These bits configure the active level of the TOGnm-pins (m = 1 to 4).
When in compare-mode the rewriting of the GCCn0 or GCCn5 register is
prohibited.
In compare mode these registers set the value for the "match and clear" mode
of the TMGn0 and TMGn1 counter.
(3)
Functionality
When the POWERn bit is set to "0", regardless of the SWFGnm bit (OCTLGnL
and OCTLGnH registers), the TOGnm pins are tied to the inactive level.
The SWFGnm bit enables or disables the output of the TOGnm pins. This bit
can be rewritten during timer operation.
The CLRGx bit (x = 0, 1) is a flag. If this bit is read, a "0" is read at all times.
This bit clears the corresponding counter (TMGn0 or TMGn1)
When GCCnm register (m = 1 to 4) are used in capture operation:
If two or more overflows of TMGn0 or TMGn1 occur between captures, a
software-based measure needs to be taken to count overflow interrupts
(INTTMGn0 or INTTMGn1).
Preliminary User's Manual U17566EE1V2UM00
16-bit Multi-Purpose Timer G (TMG)
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