NEC V850E/Dx3 Preliminary User's Manual page 443

16-bit Multi-Purpose Timer G (TMG)
Bit
position
7, 6
3, 1
2, 0
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Table 13-4 TMGMn register contents (2/2)
Bit name Function
CCSGn5 Specifies the mode of the TMGn0 (TMGn1)(CCSGn5 for TMGn1, CCSGn0 for
CCSGn0 TMGn0):
0: Free-run mode for TMGn1 (TMGn0), GCCn5 (GCCn0) in capture mode (an
detected edge at Pin TIGn5 (TIGn0) stores the value of TMGn1 (TMGn0) in
GCCn5 (GCCn0) and an interrupt INTCCGn5 (INTCCGn0) is output)
1: Match and Clear mode of the TMGn1 (TMGn0), GCCn5 (GCCn0) in compare
mode (when the data of GCCn5 (GCCn0) match the count value of the TMGn1
(TMGn0), the counter is cleared and the interrupt INTCCGn5 (INTCCGn0)
occurs)
Caution: When the POWERn bit is set, the rewriting of this bits are prohibited!
Simultaneously writing with the POWERn bit is allowed.
CLRGnx Specifies software clear for TMGnx
0: Continue TMGnx operation
1: Clears (0) the count value of TMGnx, the corresponding TOGnx is deactivated.
Note: TMGnx starts 1 peripheral-clock after this bit is set this bit is not readable
(always read 0)
TMGnxE Specifies TMGnx count operation enable/disable
0: Stop count operation the counter holds the immediate preceding value the
corresponding TOGnx is deactivated
1: Enable count operation
Note: 1. the counter needs at least 1 peripheral-clock (
2. the counter needs at least 4 peripheral-clocks (
Preliminary User's Manual U17566EE1V2UM00
Chapter 13
f
) to stop
SPCLK0
f
) to start
SPCLK0
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