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16-bit Timer/Event Counter P (TMP)
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<1> Count operation start flow
(TPnCKS0 to TPnCKS2 bits)
<2> Overflow flag clear flow
Execute instruction to clear
TPnOVF bit (CLR TPnOVF).
<3> Count operation stop flow
Figure 11-31
Software processing flow in free-running timer mode (capture function)
(2/2)
Preliminary User's Manual U17566EE1V2UM00
START
Register initial setting
Initial setting of these registers
TPnCTL0
is performed before setting the
TPnCE bit to 1.
TPnCTL1,
TPnIOC1,
TPnOPT0
The TPnCKS0 to TPnCKS2 bits can
be set at the same time when counting
TPnCE bit = 1
has been started (TPnCE bit = 1).
Read TPnOPT0 register
(check overflow flag).
NO
TPnOVF bit = 1
YES
Counter is initialized and
counting is stopped by
TPnCE bit = 0
clearing TPnCE bit to 0.
STOP
Chapter 11
411
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