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Chapter 11
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If an overflow occurs twice or more when the capture trigger interval is
long, the correct pulse width may not be obtained.
If the capture trigger interval is long, slow the count clock to lengthen one
cycle of the 16-bit counter, or use software. An example of how to use
software is shown next.
FFFFH
16-bit counter
0000H
TPnCE bit
TIPnm pin input
TPnCCRm register
INTTPnOV signal
TPnOVF bit
Overflow
Note
counter
Figure 11-36
Example when capture trigger interval is long
Note
The overflow counter is set arbitrarily by software on the internal RAM.
<1> Read the TPnCCRm register (setting of the default value of the
TIPnm pin input).
<2> An overflow occurs. Increment the overflow counter and clear the
overflow flag to 0 in the overflow interrupt servicing.
<3> An overflow occurs a second time. Increment (+1) the overflow
counter and clear the overflow flag to 0 in the overflow interrupt
servicing.
<4> Read the TPnCCRm register.
Read the overflow counter.
When the overflow counter is "N", the pulse width can be calculated
by (N × 10000H + D
In this example, the pulse width is (20000H + D
overflow occurs twice.
Clear the overflow counter (0H).
Preliminary User's Manual U17566EE1V2UM00
16-bit Timer/Event Counter P (TMP)
D
m0
D
m0
0H
1H
1 cycle of 16-bit counter
Pulse width
<1> <2>
– D
).
m1
m0
D
m1
D
m1
2H 0H
<3> <4>
– D
) because an
m1
m0
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