Clock Generator Operation; Ring And Sub Oscillator Operation; Watch Timer And Watch Calibration Timer Clocks; Clock Output Foutclk - NEC V850E/Dx3 Preliminary User's Manual

Chapter 4
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4.4 Clock Generator Operation

4.4.1 Ring and sub oscillator operation

By default, sub and ring oscillator operate during all power save modes.
However, it can be specified in the WCC register that the sub oscillator stops in
STOP mode (WCC.SOSTP).
It can also be specified that the ring oscillator stops in WATCH, Sub-WATCH,
and STOP mode (WCC.ROSTP).
These bits can be written once after system reset, independent of the reset
source.

4.4.2 Watch Timer and Watch Calibration Timer clocks

The Watch Timer input clock WTCLK can be derived directly from the main,
sub, or ring oscillator. Therefore, the WT can be operating in all power save
modes.
Because PCLK1 is stopped during power save modes, the Watch Calibration
Timer input clock WCTCLK can be directly connected to the main oscillator
output.
Note WCTCLK is not available in Sub-WATCH and STOP mode where the main
oscillator is stopped. These modes must be released before the WCT can
operate.

4.4.3 Clock output FOUTCLK

The Clock Generator output signal FOUTCLK supplies a clock for external
components. It can be derived from any internal clock source, that means ring
oscillator, sub oscillator, main oscillator, PLL, or SSCG.
FOUTCLK must be enabled by register setting (FCC.FOEN = 1). It is not
influenced by the power save modes. But FOUTCLK stops, if the selected
clock source stops.
After reset release, FOUTCLK is disabled (register FCC is cleared), and the
pin FOUT put in input mode.
Note 1. If you change the configuration of FOUTCLK or enable/disable the
selected clock source while FOUTCLK is active, glitches or irregular clock
periods may appear at the output pin.
2. The clock signal FOUTCLK cannot be used to synchronize external
circuitry to other output signals of the microcontroller—it has no specified
phase relation to other output signals.
3. There is an upper frequency limit for the output buffer of the FOUTCLK
function. Do not select a frequency higher than the maximum output buffer
frequency. Please refer to the Electrical Target Specification for the
frequency limit.
Preliminary User's Manual U17566EE1V2UM00
Clock Generator