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NEC V850ES/SG2 mPD703260 Preliminary User's Manual

32-bit single-chip microcontroller

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Preliminary User's Manual

V850ES/SG2

32-Bit Single-Chip Microcontroller

Hardware

µ µ µ µ PD703260

µ µ µ µ PD703260Y

µ µ µ µ PD703261

µ µ µ µ PD703261Y

µ µ µ µ PD703262

µ µ µ µ PD703262Y

µ µ µ µ PD703263

µ µ µ µ PD703263Y

µ µ µ µ PD70F3261

µ µ µ µ PD70F3261Y

µ µ µ µ PD70F3263

µ µ µ µ PD70F3263Y

Document No. U16541EJ1V0UM00 (1st edition)

Date Published February 2003 N CP(K)

©

Printed in Japan

TM

µ µ µ µ PD703270

µ µ µ µ PD703270Y

µ µ µ µ PD703271

µ µ µ µ PD703271Y

µ µ µ µ PD703272

µ µ µ µ PD703272Y

µ µ µ µ PD703273

µ µ µ µ PD703273

µ µ µ µ PD70F3271

µ µ µ µ PD70F3271Y

µ µ µ µ PD70F3273

µ µ µ µ PD70F3273Y

2003

µ µ µ µ PD703280

µ µ µ µ PD703280Y

µ µ µ µ PD703281

µ µ µ µ PD703281Y

µ µ µ µ PD703282

µ µ µ µ PD703282Y

µ µ µ µ PD703283

µ µ µ µ PD703283Y

µ µ µ µ PD70F3281

µ µ µ µ PD70F3281Y

µ µ µ µ PD70F3283

µ µ µ µ PD70F3283Y

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Page 1 Preliminary User’s Manual V850ES/SG2 32-Bit Single-Chip Microcontroller Hardware µ µ µ µ PD703260 µ µ µ µ PD703270 µ µ µ µ PD703280 µ µ µ µ PD703260Y µ µ µ µ PD703270Y µ µ µ µ PD703280Y µ µ µ µ PD703261 µ...
Page 2 [MEMO] Preliminary User’s Manual U16541EJ1V0UM...
Page 3 C system, provided that the system conforms to the I C Standard Specification as defined by Philips. IEBus and Inter Equipment Bus are registered trademarks of NEC Electronics Corporation. V850 Series and V850/SG2 are trademarks of NEC Electronics Corporation. Preliminary User’s Manual U16541EJ1V0UM...
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 PREFACE Readers This manual is intended for users who wish to understand the functions of the V850ES/SG2 and design application systems using these products. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/SG2 shown in the Organization below. Organization This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES Architecture User’s Manual).
Page 7 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/SG2 Document Name Document No. V850ES Architecture User’s Manual U15943E V850ES/SG2 Hardware User’s Manual This manual Documents related to development tools Document Name Document No.
Page 8: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION........................32 General............................32 Features ............................35 Application Fields........................36 Ordering Information.......................37 Pin Configuration (Top View) ....................39 Function Block Configuration ....................44 1.6.1 Internal block diagram .......................44 1.6.2 Internal units ..........................45 CHAPTER 2 PIN FUNCTIONS ........................48 List of Pin Functions .......................48 Pin States..........................55 Description of Pin Functions....................56 Pin I/O Circuit Types, I/O Buffer Power Supplies and Handling of Unused Pins ....65 CHAPTER 3 CPU FUNCTION .........................70...
Page 9 4.3.4 Port 3............................123 4.3.5 Port 4............................131 4.3.6 Port 5............................135 4.3.7 Port 7............................140 4.3.8 Port 9............................143 4.3.9 Port CM ........................... 153 4.3.10 Port CT ............................ 156 4.3.11 Port DH............................ 159 4.3.12 Port DL ............................ 162 Port Function Operation .......................176 4.4.1 Write to I/O ports ........................
Page 10 Control Registers........................217 Operation..........................222 6.4.1 Operation of each clock......................222 6.4.2 Clock output function .......................222 PLL Function..........................223 6.5.1 Overview..........................223 6.5.2 Control registers ........................223 6.5.3 Usage ............................227 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P ................228 Features ..........................228 Function Outline ........................228 Configuration .........................229 Control Registers........................233 Operation..........................239 7.5.1 Anytime write and reload ......................239...
Page 11 9.4.2 Clock generator and clock enable timing ................317 CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) ..............318 10.1 Function ..........................318 10.2 Configuration .........................319 10.3 Control Registers ........................320 10.4 Operation..........................322 10.5 Usage............................323 10.6 Cautions ..........................323 CHAPTER 11 WATCH TIMER FUNCTIONS..................324 11.1 Functions ..........................324 11.2 Configuration .........................326 11.3...
Page 12 14.4 Operation..........................378 14.4.1 Operation in normal mode .......................378 14.4.2 Operation in real-time output mode ..................378 14.4.3 Cautions ..........................379 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ..........380 15.1 Mode Switching of UARTA and Other Serial Interfaces ............380 15.1.1 CSIB4 and UARTA0 mode switching ..................380 15.1.2 UARTA2 and I C00 mode switching ..................381...
Page 13 16.8.1 Baud rate generation....................... 444 CHAPTER 17 I C BUS ...........................445 17.1 Mode Switching of I C Bus and Other Serial Interfaces ............445 17.1.1 UARTA2 and I C00 mode switching ..................445 17.1.2 CSIB0 and I C01 mode switching.................... 446 17.1.3 UARTA1 and I C02 mode switching ..................
Page 14 18.1.3 Communication mode......................516 18.1.4 Communication address ......................516 18.1.5 Broadcast communication .......................517 18.1.6 Transfer format of IEBus ......................517 18.1.7 Transfer data ...........................527 18.1.8 Bit format ..........................529 18.2 Configuration .........................530 18.3 Control Registers........................532 18.4 Interrupt Operations of IEBus Controller ................562 18.4.1 Interrupt control block ......................562 18.4.2 Example of identifying interrupt ....................564 18.4.3...
Page 15 19.8 CAN Controller Initialization....................665 19.8.1 Initialization of CAN module ....................665 19.8.2 Initialization of message buffer....................665 19.8.3 Transition from INIT mode in operational mode ..............666 19.8.4 Resetting of CAN module error counter C0ERC in INIT mode..........667 19.9 Message Reception .......................668 19.9.1 Message reception ........................
Page 16 20.7 Transfer Object ........................728 20.7.1 Transfer object.........................728 20.7.2 External bus cycles during DMA transfer (two-cycle transfer)..........728 20.8 DMA Channel Priorities......................729 20.9 DMA Transfer Start Factors ....................729 20.10 DMA Transfer End .........................729 20.10.1 DMA transfer end interrupt ......................729 20.10.2 Terminal count output upon DMA transfer end................729 20.11 Precautions ..........................730 20.11.1 Interrupt factors ........................731 CHAPTER 21 CRC FUNCTION ......................732...
Page 17 22.6 Interrupt Acknowledge Time of CPU ...................773 22.7 Periods in Which Interrupts Are Not Acknowledged by CPU ...........774 CHAPTER 23 KEY INTERRUPT FUNCTION..................775 23.1 Function ..........................775 23.2 Control Register ........................776 CHAPTER 24 STANDBY FUNCTION ....................777 24.1 Overview..........................777 24.2 HALT Mode..........................780 24.2.1 Setting and operation status....................
Page 18 CHAPTER 27 ROM CORRECTION FUNCTION ..................809 27.1 Overview ..........................809 27.2 Control Registers........................810 27.3 ROM Correction Operation and Program Flow..............812 CHAPTER 28 FLASH MEMORY ......................814 28.1 Features ..........................815 28.1.1 Erasure unit ..........................815 28.2 Writing with Flash Programmer ...................816 28.3 Programming Environment ....................816 28.4 Communication Mode ......................817 28.5...
Page 19 LIST OF FIGURES (1/9) Figure No. Title Page Pin I/O Circuits ..............................68 CPU Address Space ............................80 Image on Address Space ..........................81 Data Memory Map (Physical Addresses) ......................83 Program Memory Map............................. 84 Internal ROM Area (256 KB) ........................... 85 Internal ROM/Internal Flash Memory Area (384 KB)..................
Page 20 LIST OF FIGURES (2/9) Figure No. Title Page 5-21 Bus Hold Cycle ..............................213 Clock Generator ............................215 Block Diagram of Timer P..........................229 Flowchart of Basic Operation for Anytime Write....................240 Timing Diagram for Anytime Write.........................241 Flowchart of Basic Operation for Reload.......................242 Timing Chart for Reload ..........................243 Flowchart of Basic Operation in Interval Timer Mode..................244 Basic Operation Timing in Interval Timer Mode ....................245 Flowchart of Basic Operation in External Event Count Mode................248...
Page 21 LIST OF FIGURES (3/9) Figure No. Title Page 8-14 Flowchart of Basic Operation in PWM Mode....................301 8-15 Basic Operation Timing in PWM Mode ......................303 8-16 Flowchart of Basic Operation in Free-Running Mode ................... 306 8-17 Basic Operation Timing in Free-Running Mode (TQ0CCS3 = 0, TQ0CCS2 = 0, TQ0CCS1 = 0, TQ0CCS0 = 0)..............
Page 22 LIST OF FIGURES (4/9) Figure No. Title Page 13-11 Timing Example of One-Shot Scan Mode Operation (When Power-Fail Compare Is Made: ADA0S Register = 03H) ..............367 13-12 Processing of Analog Input Pin ........................368 13-13 Generation Timing of A/D Conversion End Interrupt Request...............369 13-14 Pin Processing Example........................370 REF0...
Page 23 LIST OF FIGURES (5/9) Figure No. Title Page 17-3 UARTA1 and I C02 Mode Switch Settings ....................447 17-4 Block Diagram of I C0n ..........................449 17-5 Serial Bus Configuration Example Using I C Bus..................450 17-6 Pin Configuration Diagram ..........................468 17-7 C Bus Serial Data Transfer Timing......................
Page 24 LIST OF FIGURES (6/9) Figure No. Title Page 18-18 Timing of INTIE2 and INTSTA Interrupt Request Signal Generation in Locked State (for (4) and (5)) ..554 18-19 Timing of INTIE2 and INTSTA Interrupt Request Signal Generation in Locked State (for (3))......555 18-20 Configuration of Interrupt Control Block ......................563 18-21...
Page 25 LIST OF FIGURES (7/9) Figure No. Title Page 19-21 Reception State Transition Chart ........................605 19-22 Error State Transition Chart .......................... 606 19-23 Connection to CAN Bus ..........................607 19-24 CAN0 Module Mask 1 Registers (C0MASK1L, C0MASK1H) ................ 635 19-25 CAN0 Module Mask 2 Registers (C0MASK2L, C0MASK2H) ................
Page 26 LIST OF FIGURES (8/9) Figure No. Title Page 19-61 Shutdown Process (Normal Shutdown)......................710 19-62 Shutdown Process (Forcible Shutdown) .......................711 19-63 Error Handling ...............................712 19-64 Setting CPU Standby (from CAN Sleep Mode) .....................713 19-65 Setting CPU Standby (from CAN Stop Mode) ....................714 20-1 DMAC Bus Cycle State Transition.........................726 21-1...
Page 27 LIST OF FIGURES (9/9) Figure No. Title Page 25-6 Operation in Software STOP Mode and After Software STOP Mode Is Released........806 25-7 Operation When Main Clock Is Stopped ....................... 806 26-1 Regulator............................... 807 26-2 REGC Pin Connection (REGC = Capacity)....................808 27-1 Block Diagram of ROM Correction ........................
Page 28 LIST OF TABLES (1/4) Table No. Title Page V850ES/SG2 Product List ..........................33 Pin I/O Buffer Power Supplies .........................48 Pin Operation States in Various Modes......................55 Program Registers............................72 System Register Numbers..........................73 Interrupt/Exception Table ..........................88 I/O Buffer Power Supplies for Pins ........................114 Port Configuration............................115 Port 0 Alternate-Function Pins........................116 Valid Edge Specification..........................120 Port 1 Alternate-Function Pins........................121...
Page 29 LIST OF TABLES (2/4) Table No. Title Page 10-1 Configuration of RTO ............................ 319 10-2 Operation During Manipulation of Real-Time Output Buffer Register 0 ............319 10-3 Operation Modes and Output Triggers of Real-Time Output Port ..............321 11-1 Interval Time of Interval Timer........................325 11-2 Configuration of Watch Timer........................
Page 30 LIST OF TABLES (3/4) Table No. Title Page 18-10 Timing of Setting ENIEBUS Bit and Participation in Communication ............534 18-11 Registers That Are Not Reset by ENIEBUS Bit .....................534 18-12 Registers That Must Be Set Before Each Communication ................534 18-13 Slave Request Condition (SLVRQ Bit Setting Condition) ................540 18-14 Operation if Parity Does Not Match .......................546...
Page 31 LIST OF TABLES (4/4) Table No. Title Page 22-1 Interrupt Source List ............................739 22-2 NMI Valid Edge Specification ........................747 22-3 Interrupt Control Register (xxICn) ......................... 756 22-4 Valid Edge Specification ..........................762 22-5 Valid Edge Specification ..........................763 22-6 Valid Edge Specification ..........................
Page 32: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The V850ES/SG2 is one of the products in the NEC Electronics V850 Series of single-chip microcontrollers designed for low-power operation for real-time control applications. General The V850ES/SG2 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, and a D/A converter.
Page 33 CHAPTER 1 INTRODUCTION Table 1-1. V850ES/SG2 Product List Function RAM Size IEBus Maskable Interrupts Non-maskable Interrupts Part Number Type Size External Internal µ PD703260 Mask ROM 256 KB 24 KB None None None µ PD703260Y On-chip µ PD703261 384 KB 32 KB None µ...
Page 34 CHAPTER 1 INTRODUCTION • Mask ROM version µ PD703260, 703260Y, 703261, 703261Y, 703262, 703262Y, 703263, 703263Y, 703270, 703270Y, 703271, 703271Y, 703272, 703272Y, 703273, 703273Y, 703280, 703280Y, 703281, 703281Y, 703282, 703282Y, 703283, 703283Y • Flash memory version µ PD70F3261, 70F3261Y, 70F3263, 70F3263Y, 70F3271, 70F3271Y, 70F3273, 70F3273Y, 70F3281, 70F3281Y, 70F3283, 70F3283Y •...
Page 35: Features
CHAPTER 1 INTRODUCTION Features Number of instructions: 83 Minimum instruction execution time: 50 ns (operating with main clock (f ) of 20 MHz) 32 bits × 32 registers General-purpose registers: Signed multiplication (16 × 16 → 32): 1 to 2 clocks Instruction set: Signed multiplication (32 ×...
Page 36: Application Fields
CHAPTER 1 INTRODUCTION ROM correction: 4 correction addresses specifiable Clock generator: During main clock or subclock operation 7-level CPU clock (f /2, f /4, f /8, f /16, f /32, f Clock-through mode/PLL mode selectable Ring-OSC: 200 kHz (TYP.) Power-save functions: HALT/IDLE1/IDLE2/software STOP/subclock/sub-IDLE mode 100-pin plastic QFP (14 ×...
Page 37: Ordering Information
CHAPTER 1 INTRODUCTION Ordering Information Part Number Package Internal ROM µ PD703260GF-xxx-3BA 100-pin plastic QFP (14 × 20) 256 KB (mask ROM) µ PD703260GC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) 256 KB (mask ROM) µ PD703260YGF-xxx-3BA 100-pin plastic QFP (14 × 20) 256 KB (mask ROM) µ...
Page 38 CHAPTER 1 INTRODUCTION Part Number Package Internal ROM µ PD703281YGF-xxx-3BA 100-pin plastic QFP (14 × 20) 384 KB (mask ROM) µ PD703281YGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) 384 KB (mask ROM) µ PD703282GF-xxx-3BA 100-pin plastic QFP (14 × 20) 512 KB (mask ROM) µ...
Page 39: Pin Configuration (Top View)
CHAPTER 1 INTRODUCTION Pin Configuration (Top View) 100-pin plastic QFP (14 × 20) µ PD703260GF-xxx-3BA µ PD703270GF-xxx-3BA µ PD703280GF-xxx-3BA µ PD703260YGF-xxx-3BA µ PD703270YGF-xxx-3BA µ PD703280YGF-xxx-3BA µ PD703261GF-xxx-3BA µ PD703271GF-xxx-3BA µ PD703281GF-xxx-3BA µ PD703261YGF-xxx-3BA µ PD703271YGF-xxx-3BA µ PD703281YGF-xxx-3BA µ PD703262GF-xxx-3BA µ PD703272GF-xxx-3BA µ...
Page 40 CHAPTER 1 INTRODUCTION P71/ANI1 PDL7/AD7 P70/ANI0 PDL6/AD6 Note 1 PDL5/AD5/FLMD1 REF0 PDL4/AD4 P10/ANO0 PDL3/AD3 P11/ANO1 PDL2/AD2 PDL1/AD1 REF1 PDH4/A20 PDL0/AD0 PDH5/A21 Note 1 Note 1 /FLMD0 PCT6/ASTB REGC PCT4/RD PCT1/WR1 PCT0/WR0 PCM3/HLDRQ RESET PCM2/HLDAK PCM1/CLKOUT PCM0/WAIT P02/NMI PDH3/A19 P03/INTP0/ADTRG PDH2/A18 P04/INTP1 P915/A15/INTP6/TIP50/TOP50 Note 5...
Page 41 CHAPTER 1 INTRODUCTION 100-pin plastic LQFP (fine pitch) (14 × 14) µ PD703260GC-xxx-8EU µ PD703270GC-xxx-8EU µ PD703280GC-xxx-8EU µ PD703260YGC-xxx-8EU µ PD703270YGC-xxx-8EU µ PD703280YGC-xxx-8EU µ PD703261GC-xxx-8EU µ PD703271GC-xxx-8EU µ PD703281GC-xxx-8EU µ PD703261YGC-xxx-8EU µ PD703271YGC-xxx-8EU µ PD703281YGC-xxx-8EU µ PD703262GC-xxx-8EU µ PD703272GC-xxx-8EU µ PD703282GC-xxx-8EU µ...
Page 42 CHAPTER 1 INTRODUCTION PDL4/AD4 REF0 PDL3/AD3 P10/ANO0 PDL2/AD2 P11/ANO1 PDL1/AD1 PDL0/AD0 REF1 PDH4/A20 PDH5/A21 Note 1 Note 1 /FLMD0 PCT6/ASTB PCT4/RD REGC PCT1/WR1 PCT0/WR0 PCM3/HLDRQ PCM2/HLDAK RESET PCM1/CLKOUT PCM0/WAIT PDH3/A19 P02/NMI PDH2/A18 P03/INTP0/ADTRG P915/A15/INTP6/TIP50/TOP50 P04/INTP1 P914/A14/INTP5/TIP51/TOP51 Note 5 P05/INTP2/DRST P913/A13/INTP4 P912/A12/SCKB3 P06/INTP3 Note 2...
Page 43 CHAPTER 1 INTRODUCTION Pin names A0 to A21: Address bus PCM0 to PCM3: Port CM AD0 to AD15: Address/data bus PCT0, PCT1, ADTRG: A/D trigger input PCT4, PCT6: Port CT ANI0 to ANI11: Analog input PDH0 to PDH5: Port DH ANO0, ANO1: Analog output PDL0 to PDL15:...
Page 44: Function Block Configuration
CHAPTER 1 INTRODUCTION Function Block Configuration 1.6.1 Internal block diagram INTC Instruction INTP0 to INTP7 Note 1 queue HLDRQ 16-bit timer/ TIQ00 to TIQ03 32-bit barrel Multiplier HLDAK counter Q: 16 × 16 → 32 shifter ASTB TOQ00 to TOQ03 1 ch WAIT System...
Page 45: Internal Units
CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) contribute to faster processing of complex instructions.
Page 46 CHAPTER 1 INTRODUCTION (10) Watchdog timer 2 A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. Either the Ring-OSC, the main clock, or the subclock can be selected as the source clock. Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal (WDT2RES) after an overflow occurs.
Page 47 CHAPTER 1 INTRODUCTION (19) Real-time output function The real-time output function transfers preset 6-bit data to output latches upon the occurrence of an external trigger signal or a timer compare register match signal. (20) CRC function A CRC operation circuit that generates 16-bit CRC (Cyclic Redundancy Check) code upon setting of 8-bit data is provided on chip.
Page 48: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS List of Pin Functions The names and functions of the pins of the V850ES/SG2 pin are described below. There are three types of pin I/O buffer power supplies: AV , AV , BV , and EV .
Page 49 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name Function Alternate Function Note 1 Port 4 SIB0/SDA01 3-bit I/O port Note 1 SOB0/SCL01 Input/output can be specified in 1-bit units. SCKB0 Port 5 TIQ01/KR0/TOQ01/RTP00 6-bit I/O port TIQ02/KR1/TOQ02/RTP01 Input/output can be specified in 1-bit units. TIQ03/KR2/TOQ03/RTP02/ Note 2 SIB2/KR3/TIQ00/TOQ00/RTP03/...
Page 50 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Function Alternate Function PCM0 Port CM WAIT 4-bit I/O port PCM1 CLKOUT Input/output can be specified in 1-bit units. PCM2 HLDAK PCM3 HLDRQ PCT0 Port CT 4-bit I/O port PCT1 Input/output can be specified in 1-bit units. PCT4 PCT6 ASTB...
Page 51 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/4) Pin Name Function Alternate Function Note 1 Output Address bus for external memory P90/KR6/TDXA1/SDA02 (when using separate bus) Note 1 P91/KR7/RXDA1/SCL02 P92/TIP41/TOP41 P93/TIP40/TOP40 P94/TIP31/TOP31 P95/TIP30/TOP30 P96/TIP21/TOP21 P97/SIB1/TIP20/TOP20 P98/SOB1 P99/SCKB1 P910/SIB3 P911/SOB3 P912/SCKB3 P913/INTP4 P914/INTP5/TIP51/TOP51 P915/INTP6/TIP50/TOP50...
Page 52 CHAPTER 2 PIN FUNCTIONS (2/4) Pin Name Function Alternate Function − − Positive power supply for bus interface and alternate-function ports − − Ground potential for bus interface and alternate-function ports CLKOUT Output Internal system clock output PCM1 Note 1 Note 2 CRXD0 Input...
Page 53 CHAPTER 2 PIN FUNCTIONS (3/4) Pin Name Function Alternate Function Input External interrupt input (non-maskable, analog noise elimination) Output Read strobe signal output for external memory PCT4 − − REGC Connection of regulator output stabilization capacitance − RESET Input System reset input RTP00 Output Real-time output port...
Page 54 CHAPTER 2 PIN FUNCTIONS (4/4) Pin Name Function Alternate Function TIP30 Input External event/clock input (TMP3) P95/A5/TOP30 TIP31 External event/clock input (TMP3) P94/A4/TOP31 TIP40 External event/clock input (TMP4) P93/A3/TOP40 TIP41 External event/clock input (TMP4) P92/A2/TOP41 TIP50 External event/clock input (TMP5) P915/A15/INTP6/TOP50 TIP51 External event/clock input (TMP5)
Page 55: Pin States
CHAPTER 2 PIN FUNCTIONS Pin States The operation states of pins in the various modes are described below. Table 2-2. Pin Operation States in Various Modes Note 2 Bus Control Pin Reset HALT Mode During IDLE1, IDLE2 Idle State Bus Hold DMA Transfer Mode, Software STOP...
Page 56: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS Description of Pin Functions (1) P02 to P05 (Port 0) … 3-state I/O P02 to P05 function as a 5-bit I/O port for which input and output can be specified in 1-bit units. In addition to I/O port pins, these pins can also be used as an NMI input, external interrupt request signal inputs, the external trigger for the A/D converter, and debug reset input.
Page 57 CHAPTER 2 PIN FUNCTIONS (3) P30 to P39 (port 3) … 3-state I/O P30 to P39 function as a 10-bit I/O port for which input and output can be set in 1-bit units. In addition to I/O port pins, these pins can also be used as external interrupt request signal inputs, serial interface I/O, timer/counter I/O, CAN data I/O, and IEBus data I/O.
Page 58 CHAPTER 2 PIN FUNCTIONS (xii) CRXD0 (CAN receive data) … Input This is the receive data input pin for CAN0 (CRXD0 is valid only in the CAN controller version). (xiii) CTXD0 (CAN transmit data) … Output This is the transmit data output pin for CAN0 (CTXD0 is valid only in the CAN controller version). (xiv) IERX0 (IEBus receive data) …...
Page 59 CHAPTER 2 PIN FUNCTIONS (5) P50 to P55 (port 5) … 3-state I/O P50 to P55 function as a 6-bit I/O port for which input and output can be set in 1-bit units. In addition to I/O port pins, these pins can also be used as serial interface I/O, timer/counter I/O, real-time output, debug function I/O, and key interrupt input function.
Page 60 CHAPTER 2 PIN FUNCTIONS (6) P70 to P711 (port 7) … 3-state I/O P70 to P711 function as a 12-bit I/O port for which input and output can be set in 1-bit units. In addition to I/O port pins, these pins can also be used as analog input pins for the A/D converter in the control mode.
Page 61 CHAPTER 2 PIN FUNCTIONS (viii) A0 to A15 (address bus) … Output These are 16-bit address output pins used during external access. The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the bus cycle becomes inactive, these pins hold the address of the immediately preceding bus cycle.
Page 62 CHAPTER 2 PIN FUNCTIONS (iv) WAIT (wait) … Input This is a control signal input pin that inserts data wait states in the bus cycle. Data can be input to this pin asynchronous to the CLKOUT signal. In the multiplexed mode, this pin is sampled at the falling edge of the CLKOUT signal in the T2 and TW states of the bus cycle.
Page 63 CHAPTER 2 PIN FUNCTIONS (b) Control mode (i) A16 to A21 (address bus) … Output These are 6-bit address output pins used by the address bus during external access. The output changes in synchronization with the rising edge of the clock during the T1 state of the bus cycle. When the bus cycle becomes inactive, these pins hold the address of the immediately preceding bus cycle.
Page 64 CHAPTER 2 PIN FUNCTIONS (18) EV (power supply for port) This is the positive power supply pin for I/O ports and alternate-function pins. (19) EV (ground for port) This is the ground pin for I/O ports and alternate-function pins. (20) V (power supply) This is the positive power supply pin.
Page 65: Pin I/O Circuit Types, I/O Buffer Power Supplies And Handling Of Unused Pins
CHAPTER 2 PIN FUNCTIONS Pin I/O Circuit Types, I/O Buffer Power Supplies and Handling of Unused Pins (1/3) Alternate Function I/O Circuit Type Recommended Connection 10-D Input: Independently connect to EV or EV via a resistor. INTP0/ADTRG Output: Leave open. INTP1 Note 1 INTP2/DRST...
Page 66 CHAPTER 2 PIN FUNCTIONS (2/3) Alternate Function I/O Circuit Type Recommended Connection P70 to P711 ANI0 to ANI11 11-F Input: Independently connect to AV or AV via a REF0 resistor. Output: Leave open. Note 1 A0/KR6/TDXA1/SDA02 10-D Input: Independently connect to EV or EV via a resistor.
Page 67 CHAPTER 2 PIN FUNCTIONS (3/3) Alternate Function I/O Circuit Type Recommended Connection − − Directly connect to V REF0 − − Directly connect to V REF1 − − Directly connect to V − − − − − − − − −...
Page 68 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits (1/2) Type 2 Type 10-G Data P-ch IN/OUT Open drain N-ch Output disable Schmitt-triggered input with hysteresis characteristics Input enable Type 5 Type 11-F Data P-ch IN/OUT Open drain Data N-ch P-ch Output disable...
Page 69 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits (2/2) Type 16 Feedback cut-off P-ch Preliminary User’s Manual U16541EJ1V0UM...
Page 70: Chapter 3 Cpu Function
CHAPTER 3 CPU FUNCTION The CPU of the V850ES/SG2 is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. Features Minimum instruction execution time: 50 ns (at 20 MHz operation: 3.0 to 3.6 V) 30.5 ns (with subclock (f = 32.768 kHz operation)) Memory space...
Page 71: Cpu Register Set
CHAPTER 3 CPU FUNCTION CPU Register Set The registers of the V850ES/SG2 can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual. (1) Program register set (2) System register set (Zero register)
Page 72: Program Register Set
CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data variable or an address variable.
Page 73: System Register Set
CHAPTER 3 CPU FUNCTION 3.2.2 System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. Table 3-2.
Page 74 CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs. If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).
Page 75 CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs. If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status word (PSW) are saved to FEPSW.
Page 76 CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are validated immediately after completion of LDSR instruction execution.
Page 77 CHAPTER 3 CPU FUNCTION (2/2) Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is performed.
Page 78 CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the program status word (PSW) are saved to DBPSW.
Page 79: Operation Modes
CHAPTER 3 CPU FUNCTION Operation Modes 3.3.1 Operation modes The V850ES/SG2 has the following operation modes. (1) Normal operation mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released.
Page 80: Address Space
CHAPTER 3 CPU FUNCTION Address Space 3.4.1 CPU address space The CPU of the V850ES/SG2 has 32-bit architecture and supports up to 4 GB of linear address space (data space) for operand addressing (data access). It also supports up to 64 MB of linear address space (program space) for instruction addressing.
Page 81: Image
CHAPTER 3 CPU FUNCTION 3.4.2 Image For addressing instruction addresses, up to 16 MB of external memory area, internal ROM area, and internal RAM area in an area of up to 16 MB of linear address space (program space) is supported. Up to 4 GB of linear address space (data space) is supported for operand addressing (data access).
Page 82: Wraparound Of Cpu Address Space
CHAPTER 3 CPU FUNCTION 3.4.3 Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. Therefore, the lowest address of the program space, 00000000H, and the highest address, 03FFFFFFH, are contiguous addresses.
Page 83: Memory Map
CHAPTER 3 CPU FUNCTION 3.4.4 Memory map The areas shown in Figure 3-3 are reserved in the V850ES/SG2. Figure 3-3. Data Memory Map (Physical Addresses) 3 F F F F F F H 3 F F F F F F H On-chip peripheral I/O area (4 KB) 3 F F F 0 0 0 H...
Page 84 CHAPTER 3 CPU FUNCTION Figure 3-4. Program Memory Map 0 3 F F F F F F H Use prohibited (program fetch prohibited area) 0 3 F F F 0 0 0 H 0 3 F F E F F F H Internal RAM area (60 KB) 0 3 F F 0 0 0 0 H 0 3 F E F F F F H...
Page 85: Areas
CHAPTER 3 CPU FUNCTION 3.4.5 Areas (1) Internal ROM/internal flash memory area Up to 1 MB is reserved as an internal ROM/internal flash memory area. (a) Internal ROM (256 KB) 256 KB are allocated to addresses 0000000H to 003FFFFH of the following versions. Accessing addresses 0040000H to 00FFFFFH is prohibited.
Page 86 CHAPTER 3 CPU FUNCTION (b) Internal ROM/internal flash memory area (384 KB) 384 KB are allocated to addresses 0000000H to 005FFFFH of the following versions. Accessing addresses 0060000H to 00FFFFFH is prohibited. • µ PD703261, 703261Y, 703271, 703271Y, 703281, 703281Y, 70F3261, 70F3261Y, 70F3271, 70F3271Y, 70F3281, 70F3281Y Figure 3-6.
Page 87 CHAPTER 3 CPU FUNCTION (d) Internal ROM/internal flash memory area (640 KB) 640 KB are allocated to addresses 0000000H to 009FFFFH of the following versions. Accessing addresses 00A0000H to 00FFFFFH is prohibited. • µ PD703263, 703263Y, 703273, 703273Y, 703283, 703283Y, 70F3263, 70F3263Y, 70F3273, 70F3273Y, 70F3283, 70F3283Y Figure 3-8.
Page 88 CHAPTER 3 CPU FUNCTION Table 3-3. Interrupt/Exception Table First Address of Interrupt/ Interrupt/ First Address of Interrupt/ Interrupt/ Exception Table Exception Source Exception Table Exception Source 00000000H RESET 00000230H INTTP4CC0 00000010H 00000240H INTTP4CC1 00000020H INTWDT2 00000250H INTTP5OV 0000004nH TRAP0n (n = 0 to F) 00000260H INTTP5CC0 0000005nH...
Page 89 CHAPTER 3 CPU FUNCTION (2) Internal RAM area Up to 60 KB are reserved as the internal RAM area. (a) Internal RAM (24 KB) 24 KB are allocated to addresses 3FF9000H to 3FFEFFFH of the following versions. Accessing addresses 3FF0000H to 3FF8FFFH is prohibited. •...
Page 90 CHAPTER 3 CPU FUNCTION (b) Internal RAM (32 KB) 32 KB are allocated to addresses 3FF7000H to 3FFEFFFH of the following versions. Accessing addresses 3FF0000H to 3FF6FFFH is prohibited. • µ PD703261, 703261Y, 703271, 703271Y, 703281, 703281Y, 70F3261, 70F3261Y, 70F3271, 70F3271Y, 70F3281, 70F3281Y Figure 3-10.
Page 91 CHAPTER 3 CPU FUNCTION (d) Internal RAM area (48 KB) 48 KB are allocated to addresses 3FF3000H to 3FFEFFFH of the following versions. Accessing addresses 3FF0000H to 3FF2FFFH is prohibited. • µ PD703263, 703263Y, 703273, 703273Y, 703283, 703283Y, 70F3263, 70F3263Y, 70F3273, 70F3273Y, 70F3283, 70F3283Y Figure 3-12.
Page 92 CHAPTER 3 CPU FUNCTION (3) On-chip peripheral I/O area 4 KB of addresses 3FFF000H to 3FFFFFFH are reserved as the on-chip peripheral I/O area. Figure 3-13. On-Chip Peripheral I/O Area 3 F F F F F F H On-chip peripheral I/O area (4 KB) 3 F F F 0 0 0 H Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the on-...
Page 93: Recommended Use Of Address Space
CHAPTER 3 CPU FUNCTION 3.4.6 Recommended use of address space The architecture of the V850ES/SG2 requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be directly accessed by an instruction for operand data.
Page 94 CHAPTER 3 CPU FUNCTION (2) Data space With the V850ES/SG2, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address.
Page 95 CHAPTER 3 CPU FUNCTION Figure 3-14. Recommended Memory Map Program space Data space F F F F F F F F H On-chip peripheral I/O F F F F F 0 0 0 H F F F F E F F F H Internal RAM x F F F F F F F H F F F E C 0 0 0 H...
Page 96: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.7 Peripheral I/O registers (1/11) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF004H Port DL Undefined √ √ FFFFF004H Port DLL PDLL Undefined √ √ FFFFF005H Port DLH PDLH Undefined √ √ FFFFF006H Port DH Undefined √...
Page 97 CHAPTER 3 CPU FUNCTION (2/11) Address Function Register Name Symbol Manipulatable Bits Default Value FFFFF0D0H DMA addressing control register 0 DADC0 0000H √ FFFFF0D2H DMA addressing control register 1 DADC1 0000H √ FFFFF0D4H DMA addressing control register 2 DADC2 0000H √...
Page 98 CHAPTER 3 CPU FUNCTION (3/11) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF13EH Interrupt control register TP3OVIC √ √ FFFFF140H Interrupt control register TP3CCIC0 √ √ FFFFF142H Interrupt control register TP3CCIC1 √ √ FFFFF144H Interrupt control register TP4OVIC √...
Page 99 CHAPTER 3 CPU FUNCTION (4/11) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF1FAH In-service priority register ISPR √ FFFFF1FCH Command register PRCMD Undefined √ √ FFFFF1FEH Power save control register √ √ FFFFF200H A/D converter mode register 0 ADA0M0 √...
Page 100 CHAPTER 3 CPU FUNCTION (5/11) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF321H BRG1 prescaler compare register PRSCM1 √ FFFFF324H BRG2 prescaler mode register PRSM2 √ FFFFF325H BRG2 prescaler compare register PRSCM2 √ FFFFF328H BRG3 prescaler mode register PRSM3 √...
Page 101 CHAPTER 3 CPU FUNCTION (6/11) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF428H Port mode register 4 √ √ FFFFF42AH Port mode register 5 √ √ FFFFF42EH Port mode register 7L PM7L √ √ FFFFF42FH Port mode register 7H PM7H √...
Page 102 CHAPTER 3 CPU FUNCTION (7/11) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF590H TMP0 control register 0 TP0CTL0 √ √ FFFFF591H TMP0 control register 1 TP0CTL1 √ √ FFFFF592H TMP0 I/O control register 0 TP0IOC0 √ √...
Page 103 CHAPTER 3 CPU FUNCTION (8/11) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF5DAH TMP4 counter register TP4CNT 0000H √ √ FFFFF5E0H TMP5 control register 0 TP5CTL0 √ √ FFFFF5E1H TMP5 control register 1 TP5CTL1 √ √ FFFFF5E2H TMP5 I/O control register 0 TP5IOC0 √...
Page 104 CHAPTER 3 CPU FUNCTION (9/11) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF844H Correction address register 1 CORAD1 00000000H √ FFFFF844H Correction address register 1L CORAD1L 0000H √ FFFFF846H Correction address register 1H CORAD1H 0000H √ FFFFF848H Correction address register 2 CORAD2 00000000H...
Page 105 CHAPTER 3 CPU FUNCTION (10/11) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFFC20H External interrupt rising edge specification register 0 INTR0 √ √ FFFFFC26H External interrupt rising edge specification register 3L INTR3L √ √ FFFFFC33H External interrupt rising edge specification register 9H INTR9H √...
Page 106 CHAPTER 3 CPU FUNCTION (11/11) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFFD36H CSIB3 transmit data register CB3TX 0000H √ FFFFFD36H CSIB3 transmit data register L CB3TXL √ √ FFFFFD40H CSIB4 control register 0 CB4CTL0 √ √ FFFFFD41H CSIB4 control register 1 CB4CTL1...
Page 107: Programmable Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.8 Programmable peripheral I/O registers The peripheral I/O area select control register (BPC) is used for programmable peripheral I/O register area selection. (1) Peripheral I/O area select control register (BPC) The BPC register can be read or written in 16-bit units. Address Default value FFFFF064H...
Page 108: Special Registers
CHAPTER 3 CPU FUNCTION 3.4.9 Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. V850ES/SG2 has the following eight (seven in mask ROM version) special registers. • Power save control register (PSC) •...
Page 109 CHAPTER 3 CPU FUNCTION (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared in <2> to the command register (PRCMD). <3>...
Page 110 CHAPTER 3 CPU FUNCTION (2) Command register (PRCMD) The command register (PRCMD) is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang- up.
Page 111 CHAPTER 3 CPU FUNCTION (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFF802H <...
Page 112: Notes
CHAPTER 3 CPU FUNCTION 3.4.10 Notes Be sure to set the following register first when using the V850ES/SG2. • System wait control register (VSWC) • On-chip debug mode register (OCDM) (flash memory version only) After setting the OCDM register, set the VSWC register, and then set the other registers as necessary. When using the external bus, set each pin to the control mode by using the port-related registers after setting the above register.
Page 113 CHAPTER 3 CPU FUNCTION (2) On-chip debug mode register (OCDM) (flash memory version only) The OCDM register is used to switch between the normal operation mode and the on-chip debug mode. This register is a special register (see 3.4.9 Special registers). Writing is possible only using a specific sequence so as to not overwrite setting contents by mistake due to inadvertent program loops, etc.
Page 114: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS Features I/O ports: 84 Other peripheral function I/O pins can be alternatively used Input/output specifiable in 1-bit units Basic Port Configuration The V850ES/SG2 features a total of 84 I/O ports consisting of ports 0, 1, 3, 4, 5, 7, 9, CM, CT, DH, and DL. The port configuration is shown below.
Page 115: Port Configuration
CHAPTER 4 PORT FUNCTIONS Port Configuration Table 4-2. Port Configuration Item Configuration Control register Port mode register n (PMn: n = 0, 1, 3, 4, 5, 7, 9, CM, CT, DH, DL) Port mode control register n (PMCn: n = 0, 3, 4, 5, 9, CM, CT, DH, DL) Port function control register n (PFCn: n = 0, 3, 4, 5, 9) Port function control expansion register n (PFCEn: n = 3, 5, 9) Port function register n (PFn: n = 0, 3, 4, 5, 9)
Page 116: Port 0
CHAPTER 4 PORT FUNCTIONS 4.3.2 Port 0 Port 0 is a 5-bit port for which I/O settings can be controlled in 1-bit units. (1) Port 0 functions Port input/output data specifiable in 1-bit units Specification made by port register 0 (P0) Port input/output specifiable in 1-bit units Specification made by port mode register 0 (PM0) Port mode/control mode (alternate functions) specifiable in 1-bit units...
Page 117 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register 0 (P0) The P0 register is an 8-bit register that controls pin level read and output level write. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF400H Output data control (in output mode) (n = 2 to 6) Outputs 0...
Page 118 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register 0 (PMC0) The PMC0 register is an 8-bit register that specifies port or control mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF440H PMC0...
Page 119 CHAPTER 4 PORT FUNCTIONS (e) Port function register 0 (PF0) The PF0 register is an 8-bit register that specifies normal output or N-ch open-drain output. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFFC60H PF06...
Page 120 CHAPTER 4 PORT FUNCTIONS (g) External interrupt rising edge specification register 0 (INTR0) The INTR0 register is an 8-bit register that specifies detection of the rising edge for the external interrupt pin. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 121: Port 1
CHAPTER 4 PORT FUNCTIONS 4.3.3 Port 1 Port 1 is a 2-bit port for which I/O settings can be controlled in 1-bit units. (1) Port 1 functions Port input/output data specifiable in 1-bit units Specification made by port register 1 (P1) Port input/output specification in 1-bit units Specification made by port mode register 1 (PM1) Port 1 includes the following alternate-function pins.
Page 122 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register 1 (P1) The P1 register is an 8-bit register that controls pin level read and output level write. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF402H Output data control (in output mode) (n = 0, 1) Outputs 0...
Page 123: Port 3
CHAPTER 4 PORT FUNCTIONS 4.3.4 Port 3 Port 3 is a 10-bit port for which I/O settings can be controlled in 1-bit units. (1) Port 3 functions Port input/output data specifiable in 1-bit units Specification made by port register 3 (P3) Port input/output specifiable in 1-bit units Specification made by port mode register 3 (PM3) Port mode/control mode (alternate functions) specifiable in 1-bit units...
Page 124 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register 3 (P3) The P3 register is a 16-bit register that controls pin level read and output level write. This register can be read or written in 16-bit units. However, when using the higher 8 bits of the P3 register as the P3H register and the lower 8 bits as the P3L register, P3 can be read or written in 8-bit or 1-bit units.
Page 125 CHAPTER 4 PORT FUNCTIONS (b) Port mode register 3 (PM3) The PM3 register is a 16-bit register that specifies input or output mode. This register can be read or written in 16-bit units. However, when using the higher 8 bits of the PM3 register as the PM3H register and the lower 8 bits as the PM3L register, PM3 can be read or written in 8-bit or 1-bit units.
Page 126 CHAPTER 4 PORT FUNCTIONS After reset: 0000H Address: PMC3 FFFFF446H, PMC3L FFFFF446H, PMC3H FFFFF447H Note PMC3 (PMC3H PMC39 PMC38 (PMC3L) PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PMC39 Specification of P39 pin operation mode in control mode I/O port RXDA2/SCL00 I/O PMC38 Specification of P38 pin operation mode in control mode...
Page 127 CHAPTER 4 PORT FUNCTIONS (d) Port function control register 3 (PFC3) The PFC3 register is a 16-bit register that specifies control mode 1, control mode 2, control mode 3, or control mode 4. This register can be read or written in 16-bit units. However, when using the higher 8 bits of the PFC3 register as the PFC3H register and the lower 8 bits as the PFC3L register, PFC3 can be read or written in 8-bit and 1-bit units.
Page 128 CHAPTER 4 PORT FUNCTIONS (f) P3 pin control mode settings PFC39 Specification of P39 Pin Control Mode RXDA2 input SCL00 input PFC38 Specification of P38 Pin Control Mode TXDA2 output SDA00 I/O PFC37 Specification of P37 Pin Control Mode CRXD0 input IERX0 input PFC36 Specification of P36 Pin Control Mode...
Page 129 CHAPTER 4 PORT FUNCTIONS PFC31 Specification of P31 Pin Control Mode Note RXDA0/INTP7 input SIB4 input PFC30 Specification of P30 Pin Control Mode TXDA0 output SOB4 output Note The INTP7 pin and RXDA0 pin are alternate-function pins. When using the pin as the RXDA0 pin, disable edge detection for the INTP7 alternate-function pin.
Page 130 CHAPTER 4 PORT FUNCTIONS (h) External interrupt falling edge specification register 3L (INTF3L) The INTF3L register is an 8-bit register that specifies detection of the falling edge for the external interrupt pin. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 131: Port 4
CHAPTER 4 PORT FUNCTIONS 4.3.5 Port 4 Port 4 is a 3-bit port that controls I/O in 1-bit units. (1) Port 4 functions Port input/output specifiable in 1-bit units Specification made by port register 4 (P4) Port input/output specifiable in 1-bit units Specification made by port mode register 4 (PM4) Port mode/control mode (alternate functions) specifiable in 1-bit units Specification made by port mode control register 4 (PMC4)
Page 132 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register (P4) The P4 register is an 8-bit register that controls pin level read and output level write. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF408H Output data control (in output mode) (n = 0 to 2) Outputs 0...
Page 133 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register 4 (PMC4) The PMC4 register is an 8-bit register that specifies port or control mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF448H PMC4...
Page 134 CHAPTER 4 PORT FUNCTIONS (e) Port function register 4 (PF4) The PF4 register is an 8-bit register that specifies normal output or N-ch open-drain output. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFFC68H PF42...
Page 135: Port 5
CHAPTER 4 PORT FUNCTIONS 4.3.6 Port 5 Port 5 is a 6-bit port that controls I/O in 1-bit units. (1) Port 5 functions Port input/output data specifiable in 1-bit units Specification made by port register 5 (P5) Port input/output specifiable in 1-bit units Specification made by port mode register 5 (PM5) Port mode/control mode (alternate functions) specifiable in 1-bit units Specification made by port mode control register 5 (PMC5)
Page 136 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register 5 (P5) The P5 register is an 8-bit register that controls pin level read and output level write. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF40AH Output data control (in output mode) (n = 0 to 5) Outputs 0...
Page 137 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register 5 (PMC5) The PMC5 register is an 8-bit register that specifies port or control mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF44AH PMC5...
Page 138 CHAPTER 4 PORT FUNCTIONS (e) Port function control expansion register 5 (PFCE5) The PFCE5 register is an 8-bit register that specifies control mode 1, control mode 2, control mode 3, or control mode 4. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 139 CHAPTER 4 PORT FUNCTIONS PFCE51 PFC51 Specification of P51 Pin Control Mode Setting prohibited Note TIQ02/KR1 input TOQ02 output RTP01 output PFCE50 PFC50 Specification of P50 Pin Control Mode Setting prohibited Note TIQ01/KR0 input TOQ01 output RTP00 output Note The KRn pin and TIQ0m pin are alternate-function pins. When using the pin as the TIQ0m pin, disable KRn pin key return detection, which is the alternate function.
Page 140: Port 7
CHAPTER 4 PORT FUNCTIONS 4.3.7 Port 7 Port 7 is a 12-bit port for which I/O settings can be controlled in 1-bit units. (1) Port 7 functions Port input/output data specifiable in 1-bit units Specification made by port 7 register (P7) Port input/output specifiable in 1-bit units Specification made by port mode register 7 (PM7) Port 7 includes the following alternate-function pins.
Page 141 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register 7H, port register 7L (P7H, P7L) The P7H and P7L registers are 8-bit registers that control pin level read and output level write. These registers can be read or written in 8-bit or 1-bit units. 16-bit access is not possible.
Page 142 CHAPTER 4 PORT FUNCTIONS (b) Port mode register 7H, port mode register 7L (PM7H, PM7L) The PM7H and PM7L registers are 8-bit registers that specify input or output mode. These registers can be read or written in 8-bit or 1-bit units. 16-bit access is not possible.
Page 143: Port 9
CHAPTER 4 PORT FUNCTIONS 4.3.8 Port 9 Port 9 is a 16-bit port for which I/O settings can be controlled in 1-bit units. (1) Port 9 functions Port input/output data specifiable in 1-bit units Specification made by port register 9 (P9) Port input/output specifiable in 1-bit units Specification made by port mode register 9 (PM9) Port mode/control mode (alternate functions) specifiable in 1-bit units...
Page 144 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register 9 (P9) The P9 register is a 16-bit register that controls pin level read and output level write. This register can be read or written in 8-bit or 1-bit units. However, when using the higher 8 bits of the P9 register as the P9H register and the lower 8 bits as the P9L register, P9 can be read or written in 8-bit or 1-bit units.
Page 145 CHAPTER 4 PORT FUNCTIONS (b) Port mode register 9 (PM9) The PM9 register is a 16-bit register that specifies input or output mode. This register can be read or written in 16-bit units. However, when using the higher 8 bits of the PM9 register as the PM9H register and the lower 8 bits as the PM9L register, PM9 can be read or written in 8-bit and 1-bit units.
Page 146 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register 9 (PMC9) The PMC9 register is a 16-bit register that specifies port or control mode. This register can be read or written in 16-bit units. However, when using the higher 8 bits of the PMC9 register as the PMC9H register and the lower 8 bits as the PMC9L register, PMC9 can be read or written in 8-bit or 1-bit units.
Page 147 CHAPTER 4 PORT FUNCTIONS (2/2) PMC98 Specification of P98 pin operation mode I/O port A8/SOB1 output PMC97 Specification of P97 pin operation mode I/O port A7/SIB1/TIP20/TOP20 I/O PMC96 Specification of P96 pin operation mode I/O port A6/TIP21/TOP21 output PMC95 Specification of P95 pin operation mode I/O port A5/TIP30/TOP30 I/O PMC94...
Page 148 CHAPTER 4 PORT FUNCTIONS (d) Port function control register 9 (PFC9) The PFC9 register is a 16-bit register that specifies control mode 1, control mode 2, control mode 3, or control mode 4. This register can be read or written in 16-bit units. However, when using the higher 8 bits of the PFC9 register as the PFC9H register and the lower 8 bits as the PFC9L register, PFC9 can be read or written in 8-bit or 1-bit units.
Page 149 CHAPTER 4 PORT FUNCTIONS (f) P9 pin control mode settings PFCE915 PFC915 Specification of P915 Pin Control Mode A15 output INTP6 input TIP50 input Setting prohibited PFCE914 PFC914 Specification of P914 Pin Control Mode A14 output INTP5 input TIP51 input TOP51 output PFC913 Specification of P913 Pin Control Mode...
Page 150 CHAPTER 4 PORT FUNCTIONS PFCE96 PFC96 Specification of P96 Pin Control Mode A6 output Setting prohibited TIP21 input TOP21 output PFCE95 PFC95 Specification of P95 Pin Control Mode A5 output TIP30 input TOP30 output Setting prohibited PFCE94 PFC94 Specification of P94 Pin Control Mode A4 output TIP31 input TOP31 output...
Page 151 CHAPTER 4 PORT FUNCTIONS (g) Port function register 9 (PF9) The PF9 register is a 16-bit register that specifies normal output or N-ch open-drain output. This register can be read or written in 16-bit units. However, when using the higher 8 bits of the PF9 register as the PF9H register and the lower 8 bits as the PF9L register, PF9 can be read or written in 8-bit or 1-bit units.
Page 152 CHAPTER 4 PORT FUNCTIONS (i) External interrupt rising edge specification register 9H (INTR9H) The INTR9H register is an 8-bit register that specifies external interrupt pin rising edge detection. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 153: Port Cm
CHAPTER 4 PORT FUNCTIONS 4.3.9 Port CM Port CM is a 4-bit port for which I/O settings can be controlled in 1-bit units. (1) Port CM functions Port input/output data specifiable in 1-bit units Specification made by port register CM (PCM) Port input/output specifiable in 1-bit units Specification made by port mode register CM (PMCM) Port mode/control mode (alternate functions) specifiable in 1-bit units...
Page 154 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register CM (PCM) The PCM register is an 8-bit register that controls pin level read and output level write. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF00CH PCM3 PCM2...
Page 155 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register CM (PMCCM) The PMCCM register is an 8-bit register that specifies port or control mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF04CH PMCCM...
Page 156: Port Ct
CHAPTER 4 PORT FUNCTIONS 4.3.10 Port CT Port CT is a 4-bit port for which I/O settings can be controlled in 1-bit units. (1) Port CT functions Port input/output data specifiable in 1-bit units Specification made by port register CT (PCT) Port input/output specifiable in 1-bit units Specification made by port mode register CT (PMCT) Port mode/control mode (alternate functions) specifiable in 1-bit units...
Page 157 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register CT (PCT) The PCT register is an 8-bit register that controls pin level read and output level write. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF00AH PCT6 PCT4...
Page 158 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register CT (PMCCT) The PMCCT register is an 8-bit register that specifies port or control mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF04AH PMCCT...
Page 159: Port Dh
CHAPTER 4 PORT FUNCTIONS 4.3.11 Port DH Port DH is a 6-bit port for which I/O settings can be controlled in 1-bit units. (1) Port DH functions Port input/output data specifiable in 1-bit units Specification made by port register DH (PDH) Port input/output specifiable in 1-bit units Specification made by port mode register DH (PMDH) Port mode/control mode (alternate functions) specifiable in 1-bit units...
Page 160 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register DH (PDH) The PDH register is an 8-bit register that controls pin level read and output level write. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF006H PDH5 PDH4...
Page 161 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register DH (PMCDH) The PMCDH register is an 8-bit register that specifies port or control mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF046H PMCDH...
Page 162: Port Dl
CHAPTER 4 PORT FUNCTIONS 4.3.12 Port DL Port DL is a 16-bit port for which I/O settings can be controlled in 1-bit units. (1) Port DL functions Port input/output data specifiable in 1-bit units Specification made by port register DL (PDL) Port input/output specifiable in 1-bit units Specification made by port mode register DL (PMDL) Port mode/control mode (alternate functions) specifiable...
Page 163 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register DL (PDL) The PDL register is a 16-bit register that controls pin level read and output level write. This register can be read or written in 16-bit units. However, when using the higher 8 bits of the PDL register as the PDLH register and the lower 8 bits as the PDLL register, PDL can be read or written in 8-bit or 1-bit units.
Page 164 CHAPTER 4 PORT FUNCTIONS (b) Port mode register DL (PMDL) The PMDL register is a 16-bit register that specifies input or output mode. This register can be read or written in 16-bit units. However, when using the higher 8 bits of the PMDL register as the PMDLH register and the lower 8 bits as the PMDLL register, PMDL can be read or written in 8-bit or 1-bit units.
Page 165 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register DL (PMCDL) The PMCDL register is a 16-bit register that specifies port or control mode. This register can be read or written in 16-bit units. However, when using the higher 8 bits of the PMCDL register as the PMCDLH register and the lower 8 bits as the PMCDLL register, PMCDL can be read or written in 8-bit or 1-bit units.
Page 166 Table 4-17. Using Port Pin as Alternate-Function Pin (1/10) Pin Name Alternate Function PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pnx Bit of (Registers) PMn Register PMCn Register PFCEn Register PFCn Register Pn Register Name −...
Page 167 Table 4-17. Using Port Pin as Alternate-Function Pin (2/10) Pin Name Alternate Function PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pnx Bit of (Registers) PMn Register PMCn Register PFCEn Register PFCn Register Pn Register Name −...
Page 168 Table 4-17. Using Port Pin as Alternate-Function Pin (3/10) Pin Name Alternate Function Other Bits PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Pnx Bit of (Registers) PMn Register PMCn Register PFCEn Register PFCn Register Pn Register Name −...
Page 169 Table 4-17. Using Port Pin as Alternate-Function Pin (4/10) Pin Name Alternate Function PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pnx Bit of (Registers) PMn Register PMCn Register PFCEn Register PFCn Register Pn Register Name Input TIQ03...
Page 170 Table 4-17. Using Port Pin as Alternate Function-Pin (5/10) Pin Name Alternate Function Other Bits Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Pn Register Name SOB2 Output...
Page 171 Table 4-17. Using Port Pin as Alternate-Function Pin (6/10) Pin Name Alternate Function Other Bits Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Pn Register Name −...
Page 172 Table 4-17. Using Port Pin as Alternate-Function Pin (7/10) Pin Name Alternate Function PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pnx Bit of (Registers) PMn Register PMCn Register PFCEn Register PFCn Register Pn Register Name Output PMC93 = 1...
Page 173 Table 4-17. Using Port Pin as Alternate-Function Pin (8/10) Pin Name Alternate Function Other Bits PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Pnx Bit of (Registers) Pn Register PMn Register PMCn Register PFCEn Register PFCn Register Name P912 PMC912 = 1...
Page 174 Table 4-17. Using Port Pin as Alternate-Function Pin (9/10) Pin Name Alternate Function PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pnx Bit of PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Pn Register Name −...
Page 175 Table 4-17. Using Port Pin as Alternate-Function Pin (10/10) Pin Name Alternate Function PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pnx Bit of (Registers) PMn Register PMCn Register PFCEn Register PFCn Register Pn Register Name −...
Page 176: Port Function Operation
CHAPTER 4 PORT FUNCTIONS Port Function Operation The port operation differs according to the I/O mode settings, as follows. 4.4.1 Write to I/O ports (1) Output mode Values are written to output latches using transfer instructions. Moreover, the output latch contents are output from the pin.
Page 177: Chapter 5 Bus Control Function
CHAPTER 5 BUS CONTROL FUNCTION The V850ES/SG2 is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. Features Output is selectable from a multiplexed bus with a minimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles.
Page 178: Bus Control Pins
CHAPTER 5 BUS CONTROL FUNCTION Bus Control Pins The pins used to connect an external device are listed in the table below. Table 5-1. Bus Control Pins (Multiplexed Bus) Bus Control Pin Alternate-Function Pin Function AD0 to AD15 PDL0 to PDL15 Address/data bus A16 to A21 PDH0 to PDH5...
Page 179: Memory Block Function
CHAPTER 5 BUS CONTROL FUNCTION Memory Block Function The 64 MB memory space is divided into memory blocks of (lower) 2 MB, 2 MB, 4 MB, and 8 MB. The programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units.
Page 180: External Bus Interface Mode Control Function
CHAPTER 5 BUS CONTROL FUNCTION External Bus Interface Mode Control Function The V850ES/SG2 includes the following two external bus interface modes. • Multiplexed bus mode • Separate bus mode These two modes can be selected by using the external bus interface mode control register (EXIMC). (1) External bus interface mode control register (EXIMC) The EXIMC register can be read or written in 8-bit or 1-bit units.
Page 181: Bus Access
CHAPTER 5 BUS CONTROL FUNCTION Bus Access 5.5.1 Number of clocks for access The following table shows the number of basic clocks required for accessing each resource. Area (Bus Width) Internal ROM (32 Bits) Internal RAM (32 Bits) External Memory (16 Bits) Bus Cycle Type Note 1 Note 2...
Page 182: Access By Bus Size
CHAPTER 5 BUS CONTROL FUNCTION 5.5.3 Access by bus size The V850ES/SG2 accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to 16 bits. •...
Page 183 CHAPTER 5 BUS CONTROL FUNCTION (2) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) First access Second access Address Address Address 2n + 1 2n + 1 2n + 2 Halfword data...
Page 184 CHAPTER 5 BUS CONTROL FUNCTION (3) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Second access Address Address 4n + 1 4n + 3 4n + 2 Word data External data Word data External data <2>...
Page 185 CHAPTER 5 BUS CONTROL FUNCTION (a) 16-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External data Word data External data <4>...
Page 186 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Second access Third access Fourth access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External data Word data External data Word data...
Page 187 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Third access Fourth access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External data Word data...
Page 188: Wait Function
CHAPTER 5 BUS CONTROL FUNCTION Wait Function 5.6.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle that is executed for each memory block space. The number of wait states can be programmed by using data wait control register 0 (DWC0).
Page 189: External Wait Function
CHAPTER 5 BUS CONTROL FUNCTION 5.6.2 External wait function To synchronize an extremely slow external device, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). Access to each area of the internal ROM, internal RAM, and on-chip peripheral I/O is not subject to control by the external wait function, in the same manner as the programmable wait function.
Page 190: Relationship Between Programmable Wait And External Wait
CHAPTER 5 BUS CONTROL FUNCTION 5.6.3 Relationship between programmable wait and external wait Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WAIT pin. In other words, the number of wait cycles is determined by the side with the greatest number of cycles.
Page 191: Programmable Address Wait Function
CHAPTER 5 BUS CONTROL FUNCTION 5.6.4 Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the address wait control register (AWC). Address wait insertion is set for each memory block area (memory blocks 0 to 3). If an address setup wait is inserted, it seems that the high-clock period of the T1 state is extended by 1 clock.
Page 192: Idle State Insertion Function
CHAPTER 5 BUS CONTROL FUNCTION Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by the chip select function in the multiplexed address/data bus mode. In the separate bus mode, one idle state (TI) can be inserted after the T2 state.
Page 193: Bus Hold Function
CHAPTER 5 BUS CONTROL FUNCTION Bus Hold Function 5.8.1 Functional outline The HLDAK and HLDRQ functions are valid if the PCM2 and PCM3 pins are set in the control mode. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status).
Page 194: Bus Hold Procedure
CHAPTER 5 BUS CONTROL FUNCTION 5.8.2 Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited Normal status <3> End of current bus cycle <4> Shift to bus idle status <5>...
Page 195: Bus Priority
CHAPTER 5 BUS CONTROL FUNCTION Bus Priority Bus hold, instruction fetch (branch), instruction fetch (successive), and operand data accesses are executed in the external bus cycle. Bus hold has the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (successive).
Page 196: Bus Timing
CHAPTER 5 BUS CONTROL FUNCTION 5.11 Bus Timing 5.11.1 Multiplexed bus (1) Read cycle Figure 5-4. Basic Bus Cycle CLKOUT Address A16 to A21 Note AD0 to AD15 Address Data ASTB WR0, WR1 WAIT Note AD0 to AD7 hold the address output when odd address byte data is accessed. AD8 to AD15 hold the address output when even address byte data is accessed.
Page 197 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-5. When Wait State (1 Wait) Is Inserted CLKOUT A16 to A21 Address Note Address AD0 to AD15 Data ASTB WR0, WR1 WAIT Note AD0 to AD7 hold the address output when odd address byte data is accessed. AD8 to AD15 hold the address output when even address byte data is accessed.
Page 198 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-6. When Idle State Is Inserted CLKOUT A16 to A21 Address Note AD0 to AD15 Address Data ASTB WR0, WR1 WAIT Note AD0 to AD7 hold the address output when odd address byte data is accessed. AD8 to AD15 hold the address output when even address byte data is accessed.
Page 199 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-7. When Wait State (1 Wait) and Idle State Are Inserted CLKOUT A16 to A21 Address Note Address Data AD0 to AD15 ASTB WR0, WR1 WAIT Note AD0 to AD7 hold the address output when odd address byte data is accessed. AD8 to AD15 hold the address output when even address byte data is accessed.
Page 200 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-8. When Address Wait State Is Inserted TASW TAHW CLKOUT Address A16 to A21 Note Address AD0 to AD15 Data ASTB WR0, WR1 WAIT Note AD0 to AD7 hold the address output when odd address byte data is accessed. AD8 to AD15 hold the address output when even address byte data is accessed.
Page 201 CHAPTER 5 BUS CONTROL FUNCTION (2) Write cycle Figure 5-9. Basic Bus Cycle CLKOUT Address A16 to A21 Note 1 AD0 to AD15 Data Address ASTB Note 2 WR0, WR1 WAIT Notes 1. AD0 to AD7 hold the address output when odd address byte data is accessed. AD8 to AD15 hold the address output when even address byte data is accessed.
Page 202 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-10. When Wait State (1 Wait) Is Inserted CLKOUT Address A16 to A21 Note 1 AD0 to AD15 Data Address ASTB Note 2 WR0, WR1 WAIT Notes 1. AD0 to AD7 hold the address output when odd address byte data is accessed. AD8 to AD15 hold the address output when even address byte data is accessed.
Page 203 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-11. When Address Wait State Is Inserted TASW TAHW CLKOUT Address A16 to A21 Note 1 AD0 to AD15 Data Address ASTB Note 2 WR0, WR1 WAIT Notes 1. AD0 to AD7 hold the address output when odd address byte data is accessed. AD8 to AD15 hold the address output when even address byte data is accessed.
Page 204 CHAPTER 5 BUS CONTROL FUNCTION (3) Bus hold cycle Figure 5-12. Bus Hold Cycle CLKOUT HLDRQ HLDAK A16 to A21 Address Undefined Address Note 1 AD0 to AD15 Data Undefined Address ASTB Note 2 WR0, WR1 WAIT Bus hold cycle Notes 1.
Page 205: Separate Bus
CHAPTER 5 BUS CONTROL FUNCTION 5.11.2 Separate bus (1) Read cycle Figure 5-13. Basic Bus Cycle CLKOUT Address A0 to A21 Note AD0 to AD15 Data ASTB WR0, WR1 WAIT Note AD0 to AD7 go into a high-impedance state when odd address byte data is accessed. AD8 to AD15 go into a high-impedance state when even address byte data is accessed.
Page 206 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-14. When Wait State (1 Wait) Is Inserted CLKOUT Address A0 to A21 Note AD0 to AD15 Data ASTB WR0, WR1 WAIT Note AD0 to AD7 go into a high-impedance state when odd address byte data is accessed. AD8 to AD15 go into a high-impedance state when even address byte data is accessed.
Page 207 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-15. When Idle State Is Inserted CLKOUT Address A0 to A21 Note AD0 to AD15 Data ASTB WR0, WR1 WAIT Note AD0 to AD7 go into a high-impedance state when odd address byte data is accessed. AD8 to AD15 go into a high-impedance state when even address byte data is accessed.
Page 208 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-16. When Wait State (1 Wait) and Idle State Are Inserted CLKOUT Address A0 to A21 Note Data AD0 to AD15 ASTB WR0, WR1 WAIT Note AD0 to AD7 go into a high-impedance state when odd address byte data is accessed. AD8 to AD15 go into a high-impedance state when even address byte data is accessed.
Page 209 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-17. When Address Wait State Is Inserted TASW TAHW CLKOUT Address A0 to A21 Note Data AD0 to AD15 ASTB WR0, WR1 WAIT Note AD0 to AD7 go into a high-impedance state when odd address byte data is accessed. AD8 to AD15 go into a high-impedance state when even address byte data is accessed.
Page 210 CHAPTER 5 BUS CONTROL FUNCTION (2) Write cycle Figure 5-18. Basic Bus Cycle CLKOUT Address A0 to A21 Note 1 AD0 to AD15 Data ASTB Note 2 WR0, WR1 WAIT Notes 1. AD0 to AD7 become undefined when odd address byte data is accessed. AD8 to AD15 become undefined when even address byte data is accessed.
Page 211 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-19. When Wait State (1 Wait) Is Inserted CLKOUT Address A0 to A21 Note 1 AD0 to AD15 Data ASTB Note 2 WR0, WR1 WAIT Notes 1. AD0 to AD7 become undefined when odd address byte data is accessed. AD8 to AD15 become undefined when even address byte data is accessed.
Page 212 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-20. When Address Wait State Is Inserted TASW TAHW CLKOUT Address A0 to A21 Note 1 Data AD0 to AD15 ASTB Note 2 WR0, WR1 WAIT Notes 1. AD0 to AD7 become undefined when odd address byte data is accessed. AD8 to AD15 become undefined when even address byte data is accessed.
Page 213 CHAPTER 5 BUS CONTROL FUNCTION (3) Bus hold cycle Figure 5-21. Bus Hold Cycle CLKOUT HLDRQ HLDAK A0 to A21 Address Undefined Address Note 1 AD0 to AD15 Data ASTB Note 2 WR0, WR1 WAIT Bus hold cycle Notes 1. AD0 to AD7 become undefined when odd address byte data is accessed. AD8 to AD15 become undefined when even address byte data is accessed.
Page 214: Chapter 6 Clock Generation Function
CHAPTER 6 CLOCK GENERATION FUNCTION Overview The following clock generation functions are available. Main clock oscillator • In clock-through mode = 2.5 to 10 MHz (f = 2.5 to 10 MHz) • In PLL mode = 2.5 to 5 MHz (f = 10 to 20 MHz) Subclock oscillator (sub-resonator) •...
Page 215: Configuration
CHAPTER 6 CLOCK GENERATION FUNCTION Configuration Figure 6-1. Clock Generator FRC bit Timer M clock Subclock Watch timer clock, oscillator watchdog timer 2 clock to f Watch timer clock Prescaler 3 IDLE mode IDLE control IDLE mode CCLSF bit, PLLON bit MFRC bit CLS bit, CK2 to CK0 bits...
Page 216 CHAPTER 6 CLOCK GENERATION FUNCTION (4) Ring-OSC Outputs a frequency (f ) of 200 kHz (TYP.). (5) Prescaler 1 This prescaler generates the clock (f to f /1,024) to be supplied to the following on-chip peripheral functions: TMP0 to TMP5, TMQ, TMM, CSIB0 to CSIB4, UARTA0 to UARTA2, I C00 to I C02, ADC, DAC, and WDT2 (6) Prescaler 2...
Page 217: Control Registers
CHAPTER 6 CLOCK GENERATION FUNCTION Control Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (see 3.4.9 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 03H.
Page 218 CHAPTER 6 CLOCK GENERATION FUNCTION (2/2) Clock selection (f × Setting prohibited × × × Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being output. 2. Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit manipulation instruction, do not change the set values of the CK2 to CK0 bits.
Page 219 CHAPTER 6 CLOCK GENERATION FUNCTION (2) Power save control register (PSC) The PSC register is a special register. Data can be written to this register only in a combination of specific sequences (see 3.4.9 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 220 CHAPTER 6 CLOCK GENERATION FUNCTION (3) Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation status in the power save mode and the clock operation. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 221 CHAPTER 6 CLOCK GENERATION FUNCTION (4) Ring OSC mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of Ring OSC. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 01H After reset: FFFFF806H <...
Page 222: Operation
CHAPTER 6 CLOCK GENERATION FUNCTION Operation 6.4.1 Operation of each clock The following table shows the operation status of each clock. Table 6-1. Operation Status of Each Clock PLL Register CLK Bit = 0, MCK Bit = 0 CLS Bit = 1, CLS Bit = 1, MCK Bit = 0 MCK Bit = 1...
Page 223: Pll Function
CHAPTER 6 CLOCK GENERATION FUNCTION PLL Function 6.5.1 Overview The PLL function is used to output the operating clock of the CPU and peripheral macro at a frequency 4 or 8 times higher than the oscillation frequency, and select the clock-through mode. When PLL function is used: Input clock = 2.5 to 5 MHz (output: 10 to 20 MHz) Clock-through mode: Input clock = 2.5 to 10 MHz (output: 2.5 to 10 MHz)
Page 224 CHAPTER 6 CLOCK GENERATION FUNCTION (2) Clock control register (CKC) The CKC register controls the internal system clock in the PLL mode. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 0AH. After reset: Address: FFFFF822H...
Page 225 CHAPTER 6 CLOCK GENERATION FUNCTION (3) Lock register (LOCKR) Phase lock occurs at a given frequency following power application or immediately after the software STOP mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). This time until stabilization is called the lockup status, and the stabilized state is called the locked status.
Page 226 CHAPTER 6 CLOCK GENERATION FUNCTION (4) PLL lockup time specification register (PLLS) The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLON bit of the PLLCTL register is changed from 0 to 1. This register can be read or written in 8-bit or 1-bit units.
Page 227: Usage
CHAPTER 6 CLOCK GENERATION FUNCTION 6.5.3 Usage (1) To use PLL • After the RESET signal has been released, the PLL operates (PLLON bit = 1), but because the default mode is the clock-through mode (SELPLL bit = 0), select the PLL mode (SELPLL bit = 1). •...
Page 228: Chapter 7 16-Bit Timer/Event Counter P
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Features Timer P (TMP) is a 16-bit timer/event counter that can be used in various ways. TMP can perform the following operations. • PWM output • Interval timer • External event counter (operation not possible when clock is stopped) •...
Page 229: Configuration
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Configuration TMP includes the following hardware. Table 7-1. Configuration of TMP0 to TMP5 Item Configuration Timer register 16-bit counter Registers TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1) TMPn counter register (TPnCNT) CCR0 buffer register, CCR1 buffer register 2 ×...
Page 230 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (1) TMPn capture/compare register 0 (TPnCCR0) The TPnCCR0 register is a 16-bit register that functions both as a capture register and as a compare register. Whether this register functions as a capture register or as a compare register can be controlled with the TPnCCSS0 bit of the TPnOPT0 register, but only in the free-running mode.
Page 231 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (2) TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register is a 16-bit register that functions both as a capture register and as a compare register. Whether this register functions as a capture register or as a compare register can be controlled with the TPnCCS1 bit of the TPnOPT0 register, but only in the free-running mode.
Page 232 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (3) TMPn counter register (TPnCNT) The TPnCNT register is a read buffer register that can read 16-bit counter values. This register is read-only, in 16-bit units. Reset input clears this register to 0000H. After reset: 0000H Address: TP0CNT FFFFF59AH, TP1CNT FFFFF5AAH, TP2CNT FFFFF5BAH, TP3CNT FFFFF5CAH,...
Page 233: Control Registers
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Control Registers (1) TMPn control register 0 (TPnCTL0) The TPnCTL0 register is an 8-bit register that controls the operation of timer P. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 234 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (2) TMPn control register 1 (TPnCTL1) The TPnCTL1 register is an 8-bit register that controls the operation of timer P. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: TP0CTL1 FFFFF591H, TP1CTL1 FFFFF5A1H, TP2CTL1 FFFFF5B1H, TP3CTL1 FFFFF5C1H,...
Page 235 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (3) TMPn I/O control register 0 (TPnIOC0) The TPnIOC0 register is an 8-bit register that controls the timer output (TOPn0, TOPn1). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: TP0IOC0 FFFFF592H, TP1IOC0 FFFFF5A2H, TP2IOC0 FFFFF5B2H, TP3IOC0 FFFFF5C2H,...
Page 236 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (4) TMPn I/O control register 1 (TPnIOC1) The TPnIOC1 register is an 8-bit register that controls the valid edge for the external input signals (TIPn0, TIPn1). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 237 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (5) TMPn I/O control register 2 (TPnIOC2) The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIPn0) and external trigger input signal (TIPn0). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 238 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (6) TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect overflow. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 239: Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Operation Timer P can perform the following operations. Operation TPnEST TIPn0 Capture/Compare Compare Write (Software Trigger Bit) (External Trigger Input) Write Interval timer mode Invalid Invalid Compare only Anytime write Note 1 External event count mode Invalid Invalid Compare only...
Page 240 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-2. Flowchart of Basic Operation for Anytime Write START Initial settings Timer operation enable (TPnCE = 1) → Transfer of TPnCCR0, TPnCCR1 values to CCR0 buffer register and CCR1 buffer register TPnCCR0 rewrite →...
Page 241 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-3. Timing Diagram for Anytime Write TPnCE = 1 16-bit counter TPnCCR0 CCR0 buffer 0000H register TPnCCR1 CCR1 buffer 0000H register INTTPnCC0 INTTPnCC1 Remarks 1. D : Setting values of TPnCCR0 register (0000H to FFFFH) : Setting values of TPnCCR1 register (0000H to FFFFH) 2.
Page 242 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (2) Reload When the TPnCCR0 and TPnCCR1 registers is written during timer operation via the CCRm buffer register, the write data is used as the 16-bit counter comparison value. The TPnCCR0 register and the TPnCCR1 register can be rewritten when TPnCE = 1.
Page 243 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-5. Timing Chart for Reload TPnCE = 1 16-bit counter TPnCCR0 CCR0 buffer 0000H register Note Same value write TPnCCR1 CCR1 buffer 0000H register Note INTTPnCC0 INTTPnCC1 Note Reload is not performed because the TPnCCR1 register was not rewritten. Remarks 1.
Page 244: Interval Timer Mode (Tpnmd2 To Tpnmd0 = 000)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P 7.5.2 Interval timer mode (TPnMD2 to TPnMD0 = 000) In the interval timer mode, an interrupt request signal (INTTPnCC0) is output upon a match between the setting value of the TPnCCR0 register and the value of the 16-bit counter, and the 16-bit counter is cleared. The TPnCCR0 register can be rewritten when TPnCE = 1, and when a value is set to the TPnCCR0 register with a write instruction from the CPU, it is transferred to the CCR0 buffer register through anytime write, and is used as the value for comparison with the 16-bit counter value.
Page 245 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-7. Basic Operation Timing in Interval Timer Mode (1/2) (a) D > D > D ; rewrite of TPnCCR0 register only; no TOPn0, TOPn1 output TPnCE = 1 FFFFH 16-bit counter TPnCCR0 CCR0 buffer 0000H register TPnCCR1...
Page 246 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-7. Basic Operation Timing in Interval Timer Mode (2/2) (b) D ; no TPnCCR0, TPnCCR1 rewrite; TOPn1 output TPnCE = 1 FFFFH 16-bit counter TPnCCR0 CCR0 buffer 0000H register TPnCCR1 CCR1 buffer 0000H register INTTPnCC0 INTTPnCC1...
Page 247: External Event Count Mode (Tpnmd2 To Tpnmd0 = 001)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P 7.5.3 External event count mode (TPnMD2 to TPnMD0 = 001) In the external event count mode, external event count input (TIPn0 pin input) is used as a count-up signal. When the external event count mode is set, count-up is performed using external event count input (TIPn0 pin input), regardless of the setting of the TPnEEE bit of the TPnCTL0 register.
Page 248 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-8. Flowchart of Basic Operation in External Event Count Mode START Initial settings • External event count mode setting (TPnCTL0: TPnMD2 to TPnMD0 = Note 1 001) • Valid edge setting (TPnIOC2: TPnEES1, TPnEES0) •...
Page 249 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-9. Basic Operation Timing in External Event Count Mode (1/2) (a) D > D > D ; rewrite of TPnCCR0 only; no TOPn0, TOPn1 output TPnCE = 1 FFFFH 16-bit counter TPnCCR0 CCR0 buffer 0000H register TPnCCR1...
Page 250 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-9. Basic Operation Timing in External Event Count Mode (2/2) (b) D ; no TPnCCR0, TPnCCR1 rewrite; TOPn0, TOPn1 output TPnCE = 1 FFFFH 16-bit counter TPnCCR0 CCR0 buffer 0000H register TPnCCR1 CCR1 buffer 0000H register INTTPnCC0...
Page 251: External Trigger Pulse Mode (Tpnmd2 To Tpnmd0 = 010)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P 7.5.4 External trigger pulse mode (TPnMD2 to TPnMD0 = 010) In the external trigger pulse mode, setting TPnCE = 1 causes external trigger input (TIPn0 pin input) wait with the 16-bit counter stopped at FFFFH. The count-up operation starts upon detection of the external trigger input (TIPn0 pin input) edge.
Page 252 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-10. Flowchart of Basic Operation in External Trigger Pulse Output Mode START Initial settings • Clock selection (TPnCTL1: TPnEEE = 0) (TPnCTL0: TPnCKS2 to TPnCKS0) External trigger • External trigger pulse output mode (TIPn0 pin) input setting (TPnCTL1: TPnMD2 to TPnMD0 = 010)
Page 253 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-11. Basic Operation Timing in External Trigger Pulse Output Mode TPnCE = 1 FFFFH 16-bit counter External trigger (TIPn0 pin) TPnCCR0 CCR0 buffer 0000H register TPnCCR1 CCR1 buffer 0000H register TOPn0 TOPn1 Remarks 1. D : Setting value of TPnCCR0 register (0000H to FFFFH) : Setting value of TPnCCR1 register (0000H to FFFFH) 2.
Page 254: One-Shot Pulse Mode (Tpnmd2 To Tpnmd0 = 011)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P 7.5.5 One-shot pulse mode (TPnMD2 to TPnMD0 = 011) In the one-shot pulse mode, setting TPnCE = 1 causes TPnEST bit setting (1) or TIPn0 pin edge detection trigger wait with the 16-bit counter held at FFFFH. The 16-bit counter starts counting up upon trigger input, and upon a match between the value of the 16-bit counter and the value of the CCR1 buffer register transferred from the TPnCR1 register, TOPn1 becomes high level;...
Page 255 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-12. Flowchart of Basic Operation in One-Shot Pulse Mode START Initial settings • Clock selection (TPnCTL1: TPnEEE = 0) (TPnCTL0: TPnCKS2 to TPnCKS0) • One-shot pulse mode setting (TPnCTL1: TPnMD2 to TPnMD0 = 011) •...
Page 256 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-13. Timing of Basic Operation in One-Shot Pulse Mode TPnCE = 1 TPnEST = 1 FFFFH Note 16-bit counter External trigger (TIPn0 pin) TPnCCR0 CCR0 buffer 0000H register TPnCCR1 CCR1 buffer 0000H register INTTPnCC0 INTTPnCC1 TOPn1...
Page 257: Pwm Mode (Tpnmd2 To Tpnmd0 = 110)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P 7.5.6 PWM mode (TPnMD2 to TPnMD0 = 110) In the PWM mode, TMPn capture/compare register 1 (TPnCCR1) is used as the duty setting register and TMPn capture/compare register 0 (TPnCCR0) is used as the cycle setting register. Variable duty PWM is output by setting these two registers and operating the timer.
Page 258 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-14. Flowchart of Basic Operation in PWM Mode (1/2) (a) Values of TPnCCR0, TPnCCR1 registers not rewritten during timer operation START Initial settings • Clock selection (TPnCTL0: TPnCKS2 to TPnCKS0) • PWM mode settings (TPnCTL1: TPnMD2 to TPnMD0 = 100) •...
Page 259 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-14. Flowchart of Basic Operation in PWM Mode (2/2) (b) Values of TPnCCR0, TPnCCR1 registers rewritten during timer operation START Initial settings • Clock selection (TPnCTL0: TPnCKS2 to TPnCKS0) • PWM mode setting (TPnCTL1: TPnMD2 to TPnMD0 = 100) •...
Page 260 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-15. Basic Operation Timing in PWM Mode (1/2) (a) TPnCCR1 value rewritten TPnCE = 1 FFFFH 16-bit counter TPnCCR0 CCR0 buffer 0000H register TPnCCR1 CCR1 buffer 0000H register TOPn1 TOPn0 Remarks 1. D : Setting value of TPnCCR0 register (0000H to FFFFH) : Setting values of TPnCCR1 register (0000H to FFFFH) 2.
Page 261 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-15. Basic Operation Timing in PWM Mode (2/2) (b) TPnCCR0, TPnCCR1 values rewritten TPnCE = 1 FFFFH 16-bit counter TPnCCR0 Note CCR0 buffer 0000H register Same value write TPnCCR1 Note CCR1 buffer 0000H register TOPn1 TOPn0...
Page 262: Free-Running Mode (Tpnmd2 To Tpnmd0 = 101)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P 7.5.7 Free-running mode (TPnMD2 to TPnMD0 = 101) In the free-running mode, both the interval function and the compare function can be realized by operating the 16- bit counter as a free-running counter and selecting capture/compare operation with the TPnCCS1 and TPnCCS0 bits. The settings of the TPnCCS1 and TPnCCS0 bits of the TPnOPT0 register are valid only in the free-running mode.
Page 263 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-16. Flowchart of Basic Operation in Free-Running Mode START Initial settings • Clock selection (TPnCTL0: TPnCKS2 to TPnCKS0) • Free-running mode setting (TPnCTL1: TPnMD2 to TPnMD0 = 101) TPnCCS1, TPnCCS0 setting TPnCCS1 = 0 TPnCCS1 = 1 TPnCCS1 = 0 TPnCCS1 = 1...
Page 264 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (1) TPnCCS1 = 0, TPnCCS0 = 0 settings (interval function description) When TPnCE = 1 is set, the 16-bit counter counts from 0000H to FFFFH and the free-running count-up operation continues until TPnCE = 0 is set. In this mode, when a value is written to the TPnCCR0 and TPnCCR1 registers, they are transferred to the CCR0 buffer register and the CCR1 buffer register (anytime write).
Page 265 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (2) TPnCCS1 = 1, TPnCCS0 = 1 settings (capture function description) When TPnCE = 1, the 16-bit counter counts from 0000H to FFFFH and free-running count-up operation continues until TPnCE = 0 is set. During this time, values are captured by capture trigger operation and are written to the TPnCCR0 and TPnCCR1 registers.
Page 266 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (3) TPnCCS1 = 1, TPnCCS0 = 0 settings When TPnCE = 1 is set, the counter counts from 0000H to FFFFH and free-running count-up operation continues until TPnCE = 0 is set. The TPnCCR0 register is used as a compare register. An interrupt signal is output upon a match between the value of the 16-bit counter and the setting value transferred to the CCR0 buffer register from the TPnCCR0 register as an interval function.
Page 267 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (4) TPnCCS1 = 0, TPnCCS0 = 1 settings When TPnCE is set to 1, the 16-bit counter counts from 0000H to FFFFH and free-running count-up operation continues until TPnCE = 0 is set. The TPnCCR1 register is used as a compare register. An interrupt signal is output upon a match between the value of the 16-bit counter and the setting value of the TPnCCR1 register as an interval function.
Page 268: Pulse Width Measurement Mode (Tpnmd2 To Tpnmd0 = 110)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P 7.5.8 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110) In the pulse width measurement mode, free-running count is performed, and upon detection of both the rising and falling edges of TIPn0 pin, the 16-bit counter value is saved to capture register 0 (TPnCCR0) and the 16-bit counter is cleared to 0000H.
Page 269 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P Figure 7-22. Basic Operation Timing in Pulse Width Measurement Mode TPnCE = 1 FFFFH FFFFH 16-bit counter TIPn0 TPnCCR0 0000H INTTPnCC0 Cleared by writing 0 TPnOVF from CPU INTTPnOV Remarks 1. D : Values captured to TPnCCR0 register (0000H to FFFFH) 2.
Page 270: Chapter 8 16-Bit Timer/Event Counter Q
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Features Timer Q (TMQ) is a 16-bit timer/event counter that can be used in various ways. TMQ can perform the following operations. • PWM output • Interval timer • External event count (operation not possible when clock is stopped) •...
Page 271: Configuration
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Configuration TMQ includes the following hardware. Table 8-1. TMQ Configuration Item Configuration 16-bit counter × 1 Timer register Registers TMQ0 timer capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) TMQ0 read buffer register (TQ0CNT) CCR0 buffer register to CCR3 buffer register Note Timer input...
Page 272 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (1) TMQ0 capture/compare register 0 (TQ0CCR0) The TQ0CCR0 register is a 16-bit register that functions both as a capture register and as a compare register. Whether this register functions as a capture register or as a compare register can be controlled with the TQ0CCS0 bit of the TQ0OPT0 register, but only in the free-running mode.
Page 273 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (2) TMQ0 capture/compare register 1 (TQ0CCR1) The TQ0CCR1 register is a 16-bit register that functions both as a capture register and as a compare register. Whether this register functions as a capture register or as a compare register can be controlled with the TQ0CCS1 bit of the TQ0OPT0 register, but only in the free-running mode.
Page 274 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (3) TMQ0 capture/compare register 2 (TQ0CCR2) The TQ0CCR2 register is a 16-bit register that functions both as a capture register and as a compare register. Whether this register functions as a capture register or as a compare register can be controlled with the TQ0CCS2 bit of the TQ0OPT0 register, but only in the free-running mode.
Page 275 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (4) TMQ0 capture/compare register 3 (TQ0CCR3) The TQ0CCR3 register is a 16-bit register that functions both as a capture register and as a compare register. Whether this register functions as a capture register or as a compare register can be controlled with the TQ0CCS3 bit of the TQ0OPT0 register, but only in the free-running mode.
Page 276: Control Registers
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Control Registers (1) TMQ0 control register 0 (TQ0CTL0) The TQ0CTL0 register is an 8-bit register that controls the operation of timer Q. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 277 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (2) TMQ0 control register 1 (TQ0CTL1) After reset: 00H Address: FFFFF541H <6> <5> TQ0CTL1 TQ0EST TQ0EEE TQ0MD2 TQ0MD1 TQ0MD0 TQ0EST Software trigger control No operation In one-shot pulse mode: One-shot pulse software trigger In external trigger pulse output mode: Pulse output software trigger The TQ0EST bit functions as a software trigger in the one-shot pulse mode and the external trigger pulse output mode.
Page 278 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (3) TMQ0 I/O control register 0 (TQ0IOC0) The TQ0IOC0 register is an 8-bit register that controls the timer output. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF542H <7>...
Page 279 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (4) TMQ0 I/O control register 1 (TQ0IOC1) The TQ0IOC1 register is an 8-bit register that controls the valid edge for the external input signals (TIQ00 to TIQ03). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 280 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (5) TMQ0 I/O control register 2 (TQ0IOC2) The TQ0IOC2 register is an 8-bit register that controls the valid edge for external event counter input signal (TIQ00) and external trigger input signal (TIQ00). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 281 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (6) TMQ0 option register 0 (TQ0OPT0) The TQ0OPT0 register is an 8-bit register used to set the capture/compare operation and detect overflow. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 282: Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Operation Timer Q can perform the following operations. Operation TQ0EST TIQ00 Capture/Compare Compare Write (Software Trigger Bit) (External Trigger Input) Write Interval timer mode Invalid Invalid Compare only Anytime write Note 1 External event count mode Invalid Invalid Compare only...
Page 283 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-2. Flowchart of Basic Operation for Anytime Write START Initial settings Timer operation enable (TQ0CE = 1) → Transfer of TQ0CCRn value to CCRn buffer register (n = 0 to 3) TQ0CCR0 rewrite → Transfer to CCR0 buffer register TQ0CCR1 rewrite →...
Page 284 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-3. Timing Diagram for Anytime Write TQ0CE = 1 16-bit counter TQ0CCR0 CCR0 0000H buffer register INTTQ0CC0 TQ0CCR1 CCR1 0000H buffer register INTTQ0CC1 TQ0CCR2 CCR2 0000H buffer register INTTQ0CC2 TQ0CCR3 CCR3 0000H buffer register INTTQ0CC3 Remarks 1.
Page 285 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (2) Reload When the TQ0CCRn register is written during timer operation via the CCRn buffer register, the write data is used as the 16-bit counter comparison value. The TQ0CCRn register can be rewritten when TQ0CE = 1. In order for the setting value when the TQ0CCRn register is rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be reloaded to the CCRn buffer register), it is necessary to rewrite TQ0CCR0 and finally write to the TQ0CCR1 register before the 16-bit counter value and the CCRn...
Page 286 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-5. Timing Chart for Reload TQ0CE = 1 16-bit counter TQ0CCR0 CCR0 0000H buffer register Note Same value write TQ0CCR1 CCR1 0000H buffer register Note TQ0CCR2 CCR2 0000H buffer register TQ0CCR3 CCR3 0000H buffer register Note INTTQ0CC0...
Page 287: Interval Timer Mode (Tq0Md2 To Tq0Md0 = 000)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q 8.5.2 Interval timer mode (TQ0MD2 to TQ0MD0 = 000) In the interval timer mode, an interrupt request signal (INTTQ0CC0) is output upon a match between the setting value of the TQ0CCR0 register and the value of the 16-bit counter, and the 16-bit counter is cleared. The TQ0CCRn register can be rewritten when TQ0CE = 1, and when a value is set to TQ0CCRn with a write instruction from the CPU, it is transferred to the CCRn buffer register through anytime write, and is used as the value for comparison with the 16-bit counter value.
Page 288 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-7. Basic Operation Timing in Interval Timer Mode (1/2) Rewrite of TQ0CCR0 register only; no TOQ0n output TQ0CE = 1 FFFFH 16-bit counter TQ0CCR0 CCR0 0000H buffer register TQ0CCR1 CCR1 0000H buffer register TQ0CCR2 CCR2 0000H...
Page 289 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-7. Basic Operation Timing in Interval Timer Mode (2/2) ; rewrite of TQ0CCR1 only; TOQ0n output TQ0CE = 1 FFFFH 16-bit counter TQ0CCR0 CCR0 0000H buffer register TQ0CCR1 CCR1 0000H buffer register TQ0CCR2 CCR2 0000H buffer register...
Page 290: External Event Count Mode (Tq0Md2 To Tq0Md0 = 001)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q 8.5.3 External event count mode (TQ0MD2 to TQ0MD0 = 001) In the external event count mode, external event count input (TIQ00 pin input) is used as a count-up signal. When the external event count mode is set, count-up is performed using external event count input (TIQ00 pin input), regardless of the setting of the TQ0EEE bit of the TQ0CTL0 register.
Page 291 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-8. Flowchart of Basic Operation in External Event Count Mode START Initial settings • External event count mode setting (TQ0CTL0: TQ0MD2 to TQ0MD0 = Note 1 001) • Valid edge setting (TQ0IOC2: TQ0EES1, TQ0EES0) •...
Page 292 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-9. Basic Operation Timing in External Event Count Mode (1/2) (a) Rewrite of TQ0CCR0 only; no TOQ0n output TQ0CE = 1 FFFFH 16-bit counter TQ0CCR0 CCR0 0000H buffer register TQ0CCR1 CCR1 0000H buffer register TQ0CCR2 CCR2 0000H...
Page 293 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-9. Basic Operation Timing in External Event Count Mode (2/2) (b) D ; rewrite of TQ0CCR1 only; TOQ0n output TQ0CE = 1 FFFFH 16-bit counter TQ0CCR0 CCR0 0000H buffer register TQ0CCR1 CCR1 0000H buffer register TQ0CCR2 CCR2...
Page 294: External Trigger Pulse Mode (Tq0Md2 To Tq0Md0 = 010)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q 8.5.4 External trigger pulse mode (TQ0MD2 to TQ0MD0 = 010) In the external trigger pulse mode, setting TQ0CE = 1 causes external trigger input (TIQ00 pin input) wait with the 16-bit counter stopped at FFFFH. The count-up operation starts upon detection of the external trigger input (TIQ00 pin input) edge.
Page 295 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-10. Flowchart of Basic Operation in External Trigger Pulse Output Mode START Initial settings • Clock selection (TQ0CTL1: TQ0EEE = 0) (TQ0CTL0: TQ0CKS2 to TQ0CKS0) • External trigger pulse output mode External trigger setting (TIQ00 pin) input (TQ0CTL1: TQ0MD2 to TQ0MD0 = 010)
Page 296 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-11. Basic Operation Timing in External Trigger Pulse Output Mode TQ0CE = 1 FFFFH 16-bit counter Output trigger (TIQ00 pin) TQ0CCR0 CCR0 0000H buffer register TQ0CCR1 CCR1 0000H buffer register TQ0CCR2 CCR2 0000H buffer register TQ0CCR3 CCR3...
Page 297: One-Shot Pulse Mode (Tq0Md2 To Tq0Md0 = 011)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q 8.5.5 One-shot pulse mode (TQ0MD2 to TQ0MD0 = 011) In the one-shot pulse mode, setting TQ0CE = 1 causes TQ0EST bit setting (1) or TIQ00 pin edge detection trigger wait with the 16-bit counter held at FFFFH. The 16-bit counter starts counting up upon trigger input, and upon a match between the value of the 16-bit counter and the value of the CCRm buffer register transferred from the TQ0CCRm register, TOQ0m becomes high level;...
Page 298 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-12. Flowchart of Basic Operation in One-Shot Pulse Mode START Initial settings • Clock selection (TQ0CTL1: TQ0EEE = 0) (TQ0CTL0: TQ0CKS2 to TQ0CKS0) • One-shot pulse mode setting (TQ0CTL1: TQ0MD2 to TQ0MD0 = 011) •...
Page 299 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-13. Timing of Basic Operation in One-Shot Pulse Mode TQ0CE = 1 TQ0EST = 1 FFFFH Note 16-bit counter External trigger (TQ000 pin) TQ0CCR0 CCR0 0000H buffer register TQ0CCR1 CCR1 0000H buffer register TQ0CCR2 CCR2 0000H...
Page 300: Pwm Mode (Tq0Md2 To Tq0Md0 = 110)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q 8.5.6 PWM mode (TQ0MD2 to TQ0MD0 = 110) In the PWM mode, TMQ0 capture/compare register m (TQ0CCRm) is used as the duty setting register and TMQ0 capture/compare register 0 (TQ0CCR0) is used as the cycle setting register. Variable duty PWM is output by setting these two registers and operating the timer.
Page 301 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-14. Flowchart of Basic Operation in PWM Mode (1/2) (i) Value of TQ0CCRn register not rewritten during timer operation START Initial settings • Clock selection (TQ0CTL0: TQ0CKS2 to TQ0CKS0) • PWM mode settings (TQ0CTL1: TQ0MD2 to TQ0MD0 = 100) •...
Page 302 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-14. Flowchart of Basic Operation in PWM Mode (2/2) (ii) Value of TQ0CCRn register rewritten during timer operation START Initial settings • Clock selection (TQ0CTL0: TQ0CKS2 to TQ0CKS0) • PWM mode setting (TQ0CTL1: TQ0MD2 to TQ0MD0 = 100) •...
Page 303 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-15. Basic Operation Timing in PWM Mode (1/2) (i) TQ0CCR1 to TQ0CCR3 values rewritten TQ0CE = 1 FFFFH 16-bit counter TQ0CCR0 CCR0 0000H buffer register Same value write TQ0CCR1 CCR1 0000H buffer register TQ0CCR2 CCR2 0000H...
Page 304 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-15. Basic Operation Timing in PWM Mode (2/2) (ii) TQ0CCR0 to TQ0CCR3 values rewritten TQ0CE = 1 FFFFH 16-bit counter TQ0CCR0 CCR0 0000H buffer register Same value write TQ0CCR1 CCR1 0000H buffer register TQ0CCR2 Note CCR2...
Page 305: Free-Running Mode (Tq0Md2 To Tq0Md0 = 101)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q 8.5.7 Free-running mode (TQ0MD2 to TQ0MD0 = 101) In the free-running mode, both the interval function and the compare function can be realized by operating the 16- bit counter as a free-running counter and selecting capture/compare operation with the TQ0CCS3 to TQ0CCS0 bits of the TQ0OPT0 register.
Page 306 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-16. Flowchart of Basic Operation in Free-Running Mode START Initial settings • Clock selection (TQ0CTL0: TQ0CKS2 to TQ0CKS0) • Free-running mode setting (TQ0CTL1: TQ0MD2 to TQ0MD0 = 101) TQ0CCSn setting TQ0CCSn = 0 TQ0CCSn = 1 (compare) (capture)
Page 307 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (1) TQ0CCSn = 0 setting (interval function description) When TQ0CE = 1 is set, the 16-bit counter counts from 0000H to FFFFH and the free-running count-up operation continues until TQ0CE = 0 is set. In this mode, when a value is written to the TQ0CCRn register, it is transferred to the CCRn buffer register (anytime write).
Page 308 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-17. Basic Operation Timing in Free-Running Mode (TQ0CCS3 = 0, TQ0CCS2 = 0, TQ0CCS1 = 0, TQ0CCS0 = 0) TQ0CE = 1 FFFFH 16-bit counter TQ0CCR0 CCR0 0000H buffer register INTTQ0CC0 match interrupt TOQ00 TQ0CCR1 CCR1...
Page 309 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-18. Basic Operation Timing in Free-Running Mode (TQ0CCS3 = 1, TQ0CCS2 = 1, TQ0CCS1 = 1, TQ0CCS0 = 1) TQ0CE = 1 FFFFH 16-bit counter TIQ00 TQ0CCR0 0000H INTTQ0CC0 capture interrupt TIQ01 TQ0CCR1 0000H INTTQ0CC1 capture interrupt...
Page 310 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-19. Basic Operation Timing in Free-Running Mode (TQ0CCS3 = 1, TQ0CCS2 = 1, TQ0CCS1 = 1, TQ0CCS0 = 0) TQ0CE = 1 FFFFH 16-bit counter TIQ00 INTTQ0CC0 0000H INTTQ0CC0 capture interrupt TIQ01 TQ0CCR1 0000H INTTQ0CC1 capture interrupt...
Page 311 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-20. Basic Operation Timing in Free-Running Mode (TQ0CCS3 = 1, TQ0CCS2 = 0, TQ0CCS1 = 0, TQ0CCS0 = 1) TQ0CE = 1 FFFFH 16-bit counter TIQ00 TQ0CCR0 0000H INTTQ0CC0 capture interrupt TQ0CCR1 CCR1 0000H buffer register INTTQ0CC1...
Page 312: Pulse Width Measurement Mode (Tq0Md2 To Tq0Md0 = 110)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q 8.5.8 Pulse width measurement mode (TQ0MD2 to TQ0MD0 = 110) In the pulse width measurement mode, free-running count is performed, and upon detection of both the rising and falling edges of TIQ00, the 16-bit counter value is saved to capture register n (TQ0CCRn) and the 16-bit counter is cleared to 0000H.
Page 313 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q Figure 8-22. Basic Operation Timing in Pulse Width Measurement Mode TQ0CE = 1 FFFFH FFFFH 16-bit counter TIQ00 TQ0CCR0 0000H INTTQ0CC0 Cleared by writing 0 TQ0OVF from CPU INTTQOV Remarks 1. D : Values captured to TQ0CCR0 register (0000H to FFFFH) 2.
Page 314: Chapter 9 16-Bit Interval Timer M
CHAPTER 9 16-BIT INTERVAL TIMER M Outline • Interval function • 8 clocks selectable • Simple counter × 1 (The simple counter is a counter that does not use a counter read buffer and cannot be read during timer count operation.) •...
Page 315: Configuration
CHAPTER 9 16-BIT INTERVAL TIMER M Configuration TMM includes the following hardware. Table 9-1. Configuration of TMM Item Configuration Timer register 16-bit counter Register TMM compare register 0 (TM0CMP0) Control register TMM0 control register (TM0CTL0) Figure 9-1. Block Diagram of TMM Internal bus TM0CTL0 TM0CE TM0CKS2 TM0CKS1TM0CKS0...
Page 316: Control Register
CHAPTER 9 16-BIT INTERVAL TIMER M Control Register (1) TMM0 control register (TM0CTL0) The TM0CTL0 register is an 8-bit register that controls the timer operation. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. The same value can always be written to the TM0CTL0 register by software.
Page 317: Operation
CHAPTER 9 16-BIT INTERVAL TIMER M Operation 9.4.1 Interval timer mode In the interval timer mode, a match interrupt signal (INTTM0EQ0) is output when the value of TMM0 compare register 0 (TM0CMP0) and the 16-bit counter value match, and at the same timing the counter is cleared to 0000H and the count-up operation is started again.
Page 318: Chapter 10 Real-Time Output Function (Rto)
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) 10.1 Function The real-time output function transfers preset data to real-time output buffer registers 0L and 0H (RTBL0 and RTBH0), and then transfers this data by hardware to an external device via the output latches, upon occurrence of an external interrupt or external trigger.
Page 319: Configuration
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) 10.2 Configuration RTO consists of the following hardware. Table 10-1. Configuration of RTO Item Configuration Registers Real-time output buffer registers 0L, 0H (RTBL0, RTBH0) Control registers Real-time output port mode register 0 (RTPM0) Real-time output port control register 0 (RTPC0) (1) Real-time output buffer registers 0L, 0H (RTBL0, RTBH0) The RTBL0 and RTBH0 registers are 4-bit registers that hold output data in advance.
Page 320: Control Registers
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) 10.3 Control Registers RTO is controlled using the following two registers. • Real-time output port mode register 0 (RTPM0) • Real-time output port control register 0 (RTPC0) (1) Real-time output port mode register 0 (RTPM0) The RTPM0 register selects the real-time output port mode or port mode in 1-bit units.
Page 321 CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register 0 (RTPC0) The RTPC0 register is a register that sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Table 10-3.
Page 322: Operation
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) 10.4 Operation If the real-time output operation is enabled by setting the RTPOE0 bit of the RTPC0 register to 1, the data of real- time output buffer registers 0L and 0H (RTBH0 and RTBL0) is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the EXTR0 and BYTE0 bits of the RTPC0 register).
Page 323: Usage
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) 10.5 Usage (1) Disable real-time output. Clear the RTPOE0 bit of the RTPC0 register to 0. (2) Perform initialization as follows. • Set the alternate-function pins of port 5 Set the PFC5.PFC5n bit and PFCE5.PFCE5n bit to 1, and then set the PMC5.PMC5n bit to 1 (n = 0 to 5). •...
Page 324: Chapter 11 Watch Timer Functions
CHAPTER 11 WATCH TIMER FUNCTIONS 11.1 Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and interval timer functions can be used at the same time. Figure 11-1. Block Diagram of Watch Timer Clear 5-bit counter INTWT...
Page 325 CHAPTER 11 WATCH TIMER FUNCTIONS Figure 11-2. Block Diagram of Prescaler 3 3-bit prescaler BGCS 8-bit counter Match Output control Prescaler compare register (PRSCM0) Prescaler mode register (PRSM0) BGCE0 BGCS01 BGCS00 Remark f : Prescaler 3 count clock frequency BGCS : Prescaler 3 output frequency Oscillation frequency (1) Watch timer...
Page 326: Configuration
CHAPTER 11 WATCH TIMER FUNCTIONS 11.2 Configuration The watch timer consists of the following hardware. Table 11-2. Configuration of Watch Timer Item Configuration 5 bits × 1 Counter 11 bits × 1 Prescaler Control register Watch timer operation mode register (WTM) Preliminary User’s Manual U16541EJ1V0UM...
Page 327: Control Registers
CHAPTER 11 WATCH TIMER FUNCTIONS 11.3 Control Registers the watch timer operation mode register (WTM) controls the watch timer. Before operating the watch timer, set the count clock and the interval time. (1) Watch timer operation mode register (WTM) The WTM register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag.
Page 328 CHAPTER 11 WATCH TIMER FUNCTIONS (2/2) WTM7 WTM3 WTM2 Selection of set time of watch flag (0.5 s: f (0.25 s: f µ (977 s: f µ (488 s: f (0.5 s: f (0.25 s: f µ (977 s: f µ...
Page 329: Operation
CHAPTER 11 WATCH TIMER FUNCTIONS 11.4 Operation 11.4.1 Operation as watch timer The watch timer generates an interrupt request at fixed time intervals. The watch timer operates using time intervals of 0.5 seconds with the subclock (32.768 kHz) or prescaler 3 (at 32.768 kHz). The count operation starts when the WTM1 and WTM0 bits of the WTM register are set to 11.
Page 330: Cautions
CHAPTER 11 WATCH TIMER FUNCTIONS Figure 11-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock or f Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T)
Page 331: Prescaler 3
CHAPTER 11 WATCH TIMER FUNCTIONS 11.5 Prescaler 3 The prescaler 3 has the following function. • Generation of watch timer count clock (source clock: main oscillation clock) 11.5.1 Control register (1) Prescaler mode register 0 (PRSM0) The PRSM0 register controls the generation of the watch timer count clock. This register can be read or written in 8-bit or 1-bit units.
Page 332: Generation Of Watch Timer Count Clock
CHAPTER 11 WATCH TIMER FUNCTIONS (2) Prescaler compare register 0 (PRSCM0) The PRSCM0 register is an 8-bit compare register. This register can be read or written in 8-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF8B1H PRSCM0 PRSCM07 PRSCM06 PRSCM05 PRSCM04 PRSCM03 PRSCM02 PRSCM01 PRSCM00...
Page 333: Chapter 12 Functions Of Watchdog Timer 2
CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 12.1 Functions Watchdog timer 2 has the following functions. • Default start watchdog timer Note 1 → Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDT2RES signal) → Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 (generation of Note 2 INTWDT2 signal) •...
Page 334: Configuration
CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 12.2 Configuration Watchdog timer 2 consists of the following hardware. Table 12-1. Configuration of Watchdog Timer 2 Item Configuration Control registers Oscillation stabilization time select register (OSTS) Watchdog timer mode register 2 (WDTM2) Watchdog timer enable register (WDTE) 12.3 Control Registers (1) Oscillation stabilization time select register (OSTS)
Page 335 CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 (2) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and operation clock of watchdog timer 2. This register can be read or written in 8-bit units. This register can be read any number of times, but it is write- only once following reset release.
Page 336 CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 Table 12-2. Watchdog Timer 2 Clock Selection WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Selected clock 100 kHz (MIN.) 200 kHz (TYP.) 400 kHz (MAX.) 41.0 ms 20.5 ms 10.2 ms 81.9 ms 41.0 ms 20.5 ms 163.8 ms 81.9 ms...
Page 337 CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 (3) Watchdog timer enable register (WDTE) The counter of the watchdog timer 2 is cleared and counting restarted by writing “ACH” to the WDTE register. The WDTE register can be read or written in 8-bit units. Reset input sets this register to 9AH.
Page 338: Operation
CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 12.4 Operation (1) Oscillation stabilization time selection function The wait time until the oscillation stabilizes after the software STOP mode is released is controlled by the OSTS register. The OSTS register can be read or written 8-bit units. Reset input sets this register to 06H.
Page 339 CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2 (2) Operation as watchdog timer 2 Watchdog timer 2 automatically starts in the reset mode following reset release. The WDTM2 register can be written to only once following reset using byte access. To use watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction.
Page 340: Chapter 13 A/D Converter
CHAPTER 13 A/D CONVERTER 13.1 Functions The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 12 channels of analog input signals (ANI0 to ANI11). The A/D converter has the following features. 10-bit resolution 12 channels Successive approximation method...
Page 341 CHAPTER 13 A/D CONVERTER The block diagram of the A/D converter is shown below. Figure 13-1. Block Diagram of A/D Converter REF0 ADA0CE bit ANI0 Sample & hold circuit ANI1 ANI2 ANI9 ADA0CE bit ANI10 Voltage comparator ANI11 ADA0TMD1 bit ADA0TMD0 bit INTAD INTTP2CC0...
Page 342: Configuration
CHAPTER 13 A/D CONVERTER 13.2 Configuration The A/D converter includes the following hardware. Table 13-1. Configuration of A/D Converter Item Configuration Analog inputs 12 channels (ANI0 to ANI11 pins) Registers Successive approximation register (SAR) A/D conversion result registers 0 to 11 (ADA0CR0 to ADA0CR11) A/D conversion result registers 0H to 11H (ADCR0H to ADCR11H): Only higher 8 bits can be read Control registers...
Page 343 CHAPTER 13 A/D CONVERTER (4) Sample & hold circuit The sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the sampled data to the voltage comparator. This circuit also holds the sampled analog input signal voltage during A/D conversion.
Page 344: Control Registers
CHAPTER 13 A/D CONVERTER 13.3 Control Registers The A/D converter is controlled by the following registers. • A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2) • A/D converter channel specification register 0 (ADA0S) • Power-fail compare mode register (ADA0PFM) The following registers are also used.
Page 345 CHAPTER 13 A/D CONVERTER (1) A/D converter mode register 0 (ADA0M0) The ADA0M0 register is an 8-bit register that specifies the operation mode and controls conversion operation. This register can be read or written in 8-bit or 1-bit units. However, bit 0 is read-only. Reset input clears this register to 00H.
Page 346 CHAPTER 13 A/D CONVERTER (2) A/D converter mode register 1 (ADA0M1) The ADA0M1 register is an 8-bit register that specifies the conversion time. This register can be read or written in 8-bit or 1-bit units. Reset input clears this bit to 00H. After reset: 00H Address: FFFFF201H ADA0M1...
Page 347 CHAPTER 13 A/D CONVERTER (3) A/D converter mode register (ADA0M2) The ADA0M2 register specifies the hardware trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: Address: FFFFF203H ADA0M2 ADA0TMD1 ADA0TMD0...
Page 348 CHAPTER 13 A/D CONVERTER (4) Analog input channel specification register 0 (ADA0S) The ADA0S register is a register that specifies the port for inputting the analog voltage to be converted into a digital signal. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 349 CHAPTER 13 A/D CONVERTER (5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) The ADA0CRn and ADA0CRnH registers store A/D conversion results. These registers are read-only, in 16-bit or 8-bit units. However, specify the ADA0CRn register for 16-bit access and the ADA0CRnH register for 8-bit access. The 10 bits of the conversion result can be read from the higher 10 bits of the ADA0CRn register, and 0 can be read from the lower 6 bits.
Page 350 CHAPTER 13 A/D CONVERTER The relationship between the analog voltage input to the analog input pins (ANI0 to ANI11) and the A/D conversion result (of A/D conversion result register n (ADA0CRn)) is as follows: × ADA0CR 1,024 0.5) REF0 REF0 REF0 −...
Page 351 CHAPTER 13 A/D CONVERTER (6) Power-fail compare mode register (ADA0PFM) The ADA0PFM register is an 8-bit register that sets the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: Address: FFFFF204H...
Page 352: Operation
CHAPTER 13 A/D CONVERTER 13.4 Operation 13.4.1 Basic operation <1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set, conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external timer trigger mode.
Page 353 CHAPTER 13 A/D CONVERTER Figure 13-3. A/D Converter Basic Operation Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADA0CRn result INTAD Preliminary User’s Manual U16541EJ1V0UM...
Page 354: Trigger Mode
CHAPTER 13 A/D CONVERTER 13.4.2 Trigger mode The timing of starting the conversion operation is specified by setting a trigger mode. The trigger mode includes a software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode.
Page 355 CHAPTER 13 A/D CONVERTER (3) Timer trigger mode In this mode, converting the signal of the analog input pin (ANI0 to ANI11 pin) specified by the ADA0S register is started by the compare match interrupt request signal (INTTP2CC0 or INTTP2CC1) of the capture/compare register connected to the timer.
Page 356: Operation Mode
CHAPTER 13 A/D CONVERTER 13.4.3 Operation mode Four operation modes are available as modes to set the ANI0 to ANI11 pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. The operation mode is selected by the ADA0MD1 and ADA0MD0 bits of the ADA0M0 register. (1) Continuous select mode In this mode, the voltage of one analog input pin selected by the ADA0S register is continuously converted into a digital value.
Page 357 CHAPTER 13 A/D CONVERTER (2) Continuous scan mode In this mode, the voltages on the analog input pins specified by the ADA0S register are sequentially selected, starting from the ANI0 pin, and converted into digital values. The result of conversion is stored in the ADA0CRn register corresponding to the analog input pin. When conversion of the signals on the analog input pins selected by the ADA0S register is complete, the A/D conversion end interrupt request signal (INTAD) is generated, and A/D conversion is started again from the ANI0 pin, unless the ADA0CE bit of the ADA0M0 register is cleared to 0 (n = 0 to 11).
Page 358 CHAPTER 13 A/D CONVERTER Figure 13-5. Timing Example of Continuous Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data 1 Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7...
Page 359 CHAPTER 13 A/D CONVERTER (3) One-shot select mode In this mode, the voltage on one analog input pin specified by the ADA0S register is converted into a digital value only once. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin and an ADA0CRn register correspond on a one-to-one basis.
Page 360 CHAPTER 13 A/D CONVERTER (4) One-shot scan mode In this mode, the voltages on the analog input pins specified by the ADA0S register are sequentially selected and converted into digital values, starting from the ANI0 pin. The A/D conversion result is stored in the ADA0CRn register corresponding to the analog input pin. When the voltages on the analog input pins specified by the ADA0S register have been converted, the A/D conversion end interrupt request signal (INTAD) is generated.
Page 361 CHAPTER 13 A/D CONVERTER Figure 13-7. Timing Example of One-Shot Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data Data 1 ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 conversion (ANI0) (ANI1)
Page 362: Power-Fail Compare Mode
CHAPTER 13 A/D CONVERTER 13.4.4 Power-fail compare mode The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and ADA0PFT registers. • When the ADA0PFE bit = 0, the INTAD signal is generated each time conversion has been completed (normal use of the A/D converter).
Page 363 CHAPTER 13 A/D CONVERTER (2) Continuous scan mode In this mode, the voltages on the analog input pins specified by the ADA0S register are sequentially selected, starting from the ANI0 pin, and converted into digital values, and the set value of the ADA0CR0H register of channel 0 is compared with the value of the ADA0PFT register.
Page 364 CHAPTER 13 A/D CONVERTER Figure 13-9. Timing Example of Continuous Scan Mode Operation (When Power-Fail Compare Is Made: ADA0S Register = 03H) (b) Timing example ANI0 Data Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 Data 5...
Page 365 CHAPTER 13 A/D CONVERTER (3) One-shot select mode In this mode, the result of converting the voltage of one analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail compare matches the condition set by the ADA0PFC bit of the ADA0PFM register, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated.
Page 366 CHAPTER 13 A/D CONVERTER (4) One-shot scan mode The voltages on the analog input pins selected by the ADA0S register are sequentially converted and the results of conversion are sequentially stored, starting from the ANI0 pin, and the set value of the ADA0CR0H register of channel 0 is compared with the set value of the ADA0PFT register.
Page 367 CHAPTER 13 A/D CONVERTER Figure 13-11. Timing Example of One-Shot Scan Mode Operation (When Power-Fail Compare Is Made: ADA0S Register = 03H) (a) Timing example ANI0 Data Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 conversion...
Page 368: Cautions
CHAPTER 13 A/D CONVERTER 13.5 Cautions (1) When A/D converter is not used When the A/D converter is not used, the power consumption can be reduced by clearing the ADA0CE bit of the ADA0M0 register to 0. (2) Input range of ANI0 to ANI11 pins Input the voltage within the specified range to the ANI0 to ANI11 pins.
Page 369 CHAPTER 13 A/D CONVERTER (5) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADA0S register is rewritten.
Page 370 CHAPTER 13 A/D CONVERTER (6) AV REF0 (a) The AV pin is also used as the power supply pin of the A/D converter and supplies power to the port REF0 with which it is multiplexed. In an application where a backup power supply is used, be sure to supply the same voltage as V to the AV pin as shown in Figure 13-14.
Page 371: How To Read A/D Converter Characteristics Table
CHAPTER 13 A/D CONVERTER 13.6 How to Read A/D Converter Characteristics Table This section describes the terms related to the A/D converter. (1) Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit).
Page 372 CHAPTER 13 A/D CONVERTER (3) Quantization error This is an error of ±1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D converter converts analog input voltages in a range of ±1/2 LSB into the same digital codes, a quantization error is unavoidable.
Page 373 CHAPTER 13 A/D CONVERTER (5) Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1…110 to 0…111 (full scale − 3/2 LSB). Figure 13-18. Full-Scale Error Full-scale error 2 AV REF0 −...
Page 374 CHAPTER 13 A/D CONVERTER (7) Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relations. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0.
Page 375: Chapter 14 D/A Converter
CHAPTER 14 D/A CONVERTER 14.1 Functions The D/A converter has the following functions. 8-bit resolution × 2 channels (DA0CS0, DA0CS1) R-2R radder method Conversion time: 20 µ s max. (AV = 3.0 to 3.6 V) REF1 × m/256 (m = 0 to 255; value set to DA0CSn register) Analog output voltage: AV REF1 Operation modes: Normal mode, real-time output mode...
Page 376: Control Registers
CHAPTER 14 D/A CONVERTER The D/A converter consists of the following hardware. Table 14-1. Configuration of D/A Converter Item Configuration Control registers D/A converter mode register (DA0M) D/A conversion value setting registers 0, 1 (DA0CS0, DA0CS1) 14.3 Control Registers The registers that control the D/A converter are as follows. •...
Page 377 CHAPTER 14 D/A CONVERTER (2) D/A conversion value setting registers 0, 1 (DA0CS0, DA0CS1) The DA0CS0 and DA0CS1 registers set the analog voltage value output to the ANO0 and ANO1 pins. These registers can be read or written in 8-bit units. Reset input clears these registers to 00H.
Page 378: Operation
CHAPTER 14 D/A CONVERTER 14.4 Operation 14.4.1 Operation in normal mode D/A conversion is performed using a write operation to the DA0CSn register as the trigger. The setting method is described below. <1> Set the DA0MDn bit of the DA0M register to 0 (normal mode). <2>...
Page 379: Cautions
CHAPTER 14 D/A CONVERTER 14.4.3 Cautions Observe the following cautions when using the D/A converter of the V850ES/SG2. (1) Do not change the set value of the DA0CSn register while the trigger signal is being issued in the real-time output mode. (2) Before changing the operation mode, be sure to clear the DA0CEn bit of the DA0M register to 0.
Page 380: Chapter 15 Asynchronous Serial Interface A (Uarta)
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.1 Mode Switching of UARTA and Other Serial Interfaces 15.1.1 CSIB4 and UARTA0 mode switching In the V850ES/SG2, CSIB4 and UARTA0 are alternate functions of the same pin and therefore cannot be used simultaneously.
Page 381: Uarta2 And I 2 C00 Mode Switching
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.1.2 UARTA2 and I C00 mode switching In the V850ES/SG2, UARTA2 and I C00 are alternate functions of the same pin and therefore cannot be used simultaneously. UARTA2 and I C00 switching must be set in advance using the PMC3 and PFC3 registers. Caution The transmit/receive operation of UARTA2 and I C00 is not guaranteed if these functions are switched during transmission or reception.
Page 382: Uarta1 And I 2 C02 Mode Switching
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.1.3 UARTA1 and I C02 mode switching In the V850ES/SG2, UARTA1 and I C02 are alternate functions of the same pin and therefore cannot be used simultaneously. UARTA1 and I C02 switching must be set in advance using the PMC9, PFC9, and PMCE9 registers. Caution The transmit/receive operation of UARTA1 and I C02 is not guaranteed if these functions are switched during transmission or reception.
Page 383: Features
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.2 Features Transfer speed: 300 bps to 312.5 kbps (using internal system clock of 20 MHz and dedicated baud rate generator) Full-duplex communication: Internal UARTA receive data register n (UAnRX) Internal UARTA transmit data register n (UAnTX) 2-pin configuration: TXDAn: Transmit data output pin RXDAn: Receive data input pin...
Page 384: Configuration
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.3 Configuration (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register used to specify the asynchronous serial interface operation. (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register used to select the input clock for the asynchronous serial interface. (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register used to control the baud rate for the asynchronous serial interface.
Page 385 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-4. Block Diagram of Asynchronous Serial Interface n Internal bus INTUAnT INTUAnR Transmission Reception unit UAnTX UAnRX unit Receive Transmit Transmission Reception shift register shift register controller controller Filter Baud rate Baud rate Selector TXDAn generator...
Page 386: Control Registers
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.4 Control Registers (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 10H.
Page 387 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) UAnDIR Transfer direction selection MSB-first transfer LSB-first transfer This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit = the UAnRXE bit = 0. Parity selection during transmission Parity selection during reception UAnPS1 UAnPS0 No parity output...
Page 388 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) For details, see 15.7 (2) UARTAn control register 1 (UAnCTL1). (3) UARTAn control register 2 (UAnCTL2) For details, see 15.7 (3) UARTAn control register 2 (UAnCTL2). (4) UARTAn option control register 0 (UAnOPT0) The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTAn register.
Page 389 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) UAnSLS2 UAnSLS1 UAnSLS0 SBF length selection 13-bit output (reset value) 14-bit output 15-bit output 16-bit output 17-bit output 18-bit output 19-bit output 20-bit output This register can be set when the UAnPWR bit of the UAnCTL0 register = 0 or when the UAnRXE bit of the UAnCTL0 register = 0.
Page 390 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (5) UARTAn status register (UAnSTR) The UAnSTR register is an 8-bit register that displays the UARTAn transfer status and reception error contents. This register can be read or written in 8-bit or 1-bit units, but the UAnTSF bit is a read-only bit, while the UAnPE, UAnFE, and UAnOVE bits can both be read and written.
Page 391 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) After reset: 00H Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H, UA2STR FFFFFA24H <2> <1> <7> <0> UAnTSF UAnSTR UAnPE UAnFE UAnOVE (n = 0 to 2) UAnTSF Transfer status flag • When the UAnPWR bit of the UAnCTL0 register = 0 or the UAnTXE bit of the UAnCTL0 register = 0 has been set.
Page 392 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) UARTAn receive data register (UAnRX) The UAnRX register is an 8-bit buffer register that stores parallel data converted by receive shift register. The data stored in the receive shift register is transferred to the UAnRX register upon completion of reception of 1 byte of data.
Page 393: Interrupt Request Signals
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.5 Interrupt Request Signals The following two interrupt request signals are generated from UARTAn. • Reception complete interrupt request signal (INTUAnR) • Transmission enable interrupt request signal (INTUAnT) The default priority for these two interrupt request signals is highest for the reception complete interrupt request signal.
Page 394: Operation
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6 Operation 15.6.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 15-5, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s).
Page 395 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-5. UARTA Transmit/Receive Data Format (a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start Parity Stop (b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start Parity...
Page 396: Sbf Transmission/Reception Format
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.2 SBF transmission/reception format The V850ES/SG2 has an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN (Local Interconnect Network) function. Figure 15-6. LIN Transmission Manipulation Outline Wake-up Synch Check signal break...
Page 397 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-7. LIN Reception Manipulation Outline Wake-up Synch Check signal break Synch Ident DATA DATA frame field field field field field field Sleep Note 2 Data Data Note 5 SF reception ID reception 13 bits transmission transmission...
Page 398: Sbf Transmission
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.3 SBF transmission When the UAnPWR bit = the UAnTXE bit of the UAnCTL0 register = 1, the transmission enabled status is entered, and SBF transmission is started by setting (to 1) the SBF transmission trigger (UAnSTT bit of UAnOPT0 register). Thereafter, a low-level width of bits 13 to 20 specified by the UAnSLS2 to UAnSLS0 bits of the UAnOPT0 register is output.
Page 399: Sbf Reception
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.4 SBF reception The reception enabled status is achieved by setting the UAnPWR bit of the UAnCTL0 register to 1 and then setting the UAnRX bit of the UAnCTL0 register to 1. The SBF reception wait status is set by setting the SBF reception trigger (UAnSTR bit of the UAnOPT0 register) to In the SBF reception wait status, similarly to the UART reception wait status, the RXDAn pin is monitored and start bit detection is performed.
Page 400: Uart Transmission
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.5 UART transmission A high level is output to the TXDAn pin by setting the UAnPWR bit of the UAnCTL0 register to 1. Next, the transmission enabled status is set by setting the UAnTXE bit of the UAnCTL0 register to 1, and transmission is started by writing transmit data to the UAnTX register.
Page 401: Continuous Transmission Procedure
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.6 Continuous transmission procedure UARTA can write the next transmit data to the UAnTX register when the UARTAn transmit shift register starts the shift operation. The transfer timing of the UARTAn transmit shift register can be judged from the transmission enable interrupt request signal (INTUAnT).
Page 402 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-12. Continuous Transfer Operation Timing (a) Transmission start Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXDAn UAnTX Data (1) Data (2) Data (3) Transmission Data (2) Data (1) shift register INTUAnT UAnTSF...
Page 403: Uart Reception
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.7 UART reception The reception wait status is set by setting the UAnPWR bit of the UAnCTL0 register to 1 and then setting the UAnRX bit of the UAnCTL0 register to 1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed.
Page 404: Reception Error
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.8 Reception error Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. A data reception result error flag is set to the UAnSTR register and a reception complete interrupt request signal (INTUAnR) is output.
Page 405: Parity Types And Operations
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.9 Parity types and operations Caution When using the LIN function, fix the UAnPS1 and UAnPS0 bits of the UAnCTL0 register to 00. The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side.
Page 406: Receive Data Noise Filter
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.10 Receive data noise filter This filter performs the RXDAn pin sampling using the internal system clock (f When the same sampling value is read twice, the match detector output changes and sampling as the input data is performed.
Page 407: Dedicated Baud Rate Generator
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.7 Dedicated Baud Rate Generator The dedicated baud rate generator is configured of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel.
Page 408 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register that selects the UARTAn clock. This register can be read or written in 8-bit units. Reset input clears this register to 00H. After reset: 00H Address: UA0CTL1 FFFFFA01H, UA1CTL1 FFFFFA11H, UA2CTL1 FFFFFA21H...
Page 409 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTAn. This register can be read or written in 8-bit units. Reset input sets this register to FFH.
Page 410 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (4) Baud rate The baud rate is obtained by the following equation. XCLK Baud rate = [bps] 2 × k = Frequency of base clock (Clock) selected by bits UAnCKS3 to UAnCKS0 of UAnCTL1 register XCLK k = Value set using bits UAnBRS7 to UAnBRS0 of UAnCTL2 register (k = 4, 5, 6, ..., 255) (5) Baud rate error...
Page 411 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) Baud rate setting example Table 15-2. Baud Rate Generator Setting Data Baud Rate = 20 MHz = 16 MHz = 10 MHz (bps) UAnCTL1 UAnCTL2 ERR (%) UAnCTL1 UAnCTL2 ERR (%) UAnCTL1 UAnCTL2 ERR (%) 300 09H...
Page 412 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (7) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution The baud rate error during reception must be set within the allowable error range using the following equation.
Page 413 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Therefore, the maximum baud rate that can be received by the destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, obtaining the following maximum allowable transfer rate yields the following. 21k −...
Page 414 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (8) Baud rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 clocks longer. However, timing initialization is performed through start bit detection by the receiving side, so this has no influence on the transfer result.
Page 415: Chapter 16 3-Wire Variable-Length Serial I/O (Csib)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.1 Mode Switching of CSIB and Other Serial Interfaces 16.1.1 CSIB4 and UARTA0 mode switching In the V850ES/SG2, CSIB4 and UARTA0 are alternate functions of the same pin and therefore cannot be used simultaneously.
Page 416 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) Figure 16-1. CSIB4 and UARTA0 Mode Switch Settings After reset: 0000H Address: FFFFF446H, FFFFF447H PMC3 PMC39 PMC38 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 After reset: 0000H Address: FFFFF466H, FFFF467H PFC3 PFC39 PFC38 PFC37 PFC36...
Page 417: Csib0 And I 2 C01 Mode Switching
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.1.2 CSIB0 and I C01 mode switching In the V850ES/SG2, CSIB0 and I C01 are alternate functions of the same pin and therefore cannot be used simultaneously. CSIB0 and I C01 switching must be set in advance using the PMC4 and PFC4 registers. Caution The transmit/receive operation of CSIB0 and I C01 is not guaranteed if these functions are switched during transmission or reception.
Page 418: Features
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.2 Features Master mode and slave mode selectable 8-bit to 16-bit transfer, 3-wire serial interface Interrupt request signals (INTCBnT, INTCBnR) × 2 Serial clock and data phase switchable Transfer data length selectable in 1-bit units between 8 and 16 bits Transfer data MSB-first/LSB-first switchable 3-wire transfer SOBn: Serial data output...
Page 419 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) Figure 16-3. Block Diagram of CSIB Internal bus CBnCTL1 CBnCTL0 CBnCTL2 CBnSTR INTCBnT Controller INTCBnR Phase control BRGm CBnTX SCKBn Phase SO latch SOBn control SIBn Shift register CBnRX Remarks n = 0 to 4 m = 1 (n = 0, 1) m = 2 (n = 2, 3) m = 3 (n = 4)
Page 420 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) CSIBn receive data register (CBnRX) The CBnRX register is a 16-bit buffer register that holds receive data. This register is read-only, in 16-bit units. The receive operation is started by reading the CBnRX register in the reception enabled status. If the transfer data length is 8 bits, this register is read-only as the CBnRXL register for lower 8 bits of the CBnRX register in 8-bit units.
Page 421: Control Registers
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.4 Control Registers The following registers are used to control CSIB. • CSIBn control register 0 (CBnCTL0) • CSIBn control register 1 (CBnCTL1) • CSIBn control register 2 (CBnCTL2) • CSIBn status register (CBnSTR) (1) CSIBn control register 0 (CBnCTL0) The CBnCTL0 register is a register that controls the CSIB serial transfer operation.
Page 422 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) Note CBnDIR Specification of transfer direction mode (MSB/LSB) MSB first LSB first Note CBnTMS Transfer mode specification Single transfer mode Continuous transfer mode • When the CBnTMS bit = 0, single transfer results, so continuous transmission/ continuous reception are not supported.
Page 423 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) CSIBn control register 1 (CB0CTL1) The CB0CTL1 is an 8-bit register that controls the CSIB serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. Caution The CBnCTL1 register can be rewritten when the CBnPWR bit of the CBnCTL0 register = 0 or when both the CBnTXE and CBnRXE bits = 0.
Page 424 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (3) CSIBn control register 2 (CBnCTL2) The CBnCTL2 register is an 8-bit register that controls the number of CSIB serial transfer bits. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 425 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (a) Transfer data length change function The CSIB transfer data length can be set in 1-bit units between 8 and 16 bits using bits CBnCL3 to CBnCL0 of the CBnCTL2 register. When the transfer bit length is set to a value other than 16 bits, set the data to the CBnTX or CBnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB.
Page 426 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (4) CSIBn status register (CBnSTR) The CBnSTR register is an 8-bit register that displays the CSIB status. This register can be read or written in 8-bit or 1-bit units, but the CBnSTF flag is a read-only. Reset input clears this register to 00H.
Page 427: Operation
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.5 Operation 16.5.1 Single transfer (master mode, transmission/reception mode) MSB first (CBnDIR bit of CBnCTL0 register = 0), the CBnCKP bit of the CBnCTL1 register = 0, MSB first (CBnDIR bit of CBnCTL0 register = 0), the CBnDAP bit of the CBnCTL1 register = 0, transfer data length = 8 bits (CBnCL3 to CBnCL0 bits of CBnCTL2 register = 0, 0, 0, 0) CBnTX write (55H) CBnRX read (AAH)
Page 428: Single Transfer Mode (Master Mode, Reception Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.5.2 Single transfer mode (master mode, reception mode) MSB first (CBnDIR bit of CBnCTL0 register = 0), the CBnCKP bit of the CBnCTL1 register = 0, MSB first (CBnDIR bit of CBnCTL0 register = 0), the CBnDAP bit of the CBnCTL1 register = 0, transfer data length = 8 bits (CBnCL3 to CBnCL0 bits of CBnCTL2 register = 0, 0, 0, 0) CBnRX read (55H) CBnRX read (AAH)
Page 429: Continuous Mode (Master Mode, Transmission/Reception Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.5.3 Continuous mode (master mode, transmission/reception mode) MSB first (CBnDIR bit of CBnCTL0 register = 0), the CBnCKP bit of the CBnCTL1 register = 1, the CBnDAP bit of the CBnCTL1 register = 0, transfer data length = 8 bits (CBnCL3 to CBnCL0 bits of CBnCTL2 register = 0, 0, 0, 0) CBnTX SCKBn SOBn...
Page 430: Continuous Mode (Master Mode, Reception Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.5.4 Continuous mode (master mode, reception mode) MSB first (CBnDIR bit of CBnCTL0 register = 0), the CBnCKP bit of the CBnCTL1 register = 0, the CBnDAP bit of the CBnCTL1 register = 1, transfer data length = 8 bits (CBnCL3 to CBnCL0 bits of CBnCTL2 register = 0, 0, 0, 0) SCKBn CBnSCE SIBn...
Page 431: Continuous Reception Mode (Error)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.5.5 Continuous reception mode (error) MSB first (CBnDIR bit of CBnCTL0 register = 0), the CBnCKP bit of the CBnCTL1 register = 0, the CBnDAP bit of the CBnCTL1 register = 1, transfer data length = 8 bits (CBnCL3 to CBnCL0 bits of CBnCTL2 register = 0, 0, 0, 0) SCKBn SIBn INTCBnR...
Page 432: Continuous Mode (Slave Mode, Transmission/Reception Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.5.6 Continuous mode (slave mode, transmission/reception mode) MSB first (CBnDIR bit of CBnCTL0 register = 0), the CBnCKP bit of the CBnCTL1 register = 0, the CBnDAP bit of the CBnCTL1 register = 1, transfer data length = 8 bits (CSnCL3 to CBnCL0 bits of CBnCTL2 register = 0, 0, 0, 0) CBnTX SCKBn SOBn...
Page 433: Continuous Mode (Slave Mode, Reception Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.5.7 Continuous mode (slave mode, reception mode) MSB first (CBnDIR bit of CBnCTL0 register = 0), the CBnCKP bit of the CBnCTL1 register = 0, the CBnDAP bit of the CBnCTL1 register = 0, transfer data length = 8 bits (CSnCL3 to CBnCL0 bits of CBnCTL2 register = 0, 0, 0, 0) SCKBn SIBn INTCBnR...
Page 434: Clock Timing
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.5.8 Clock timing (1/2) (i) CBnCKP = 0, CBnDAP = 0 SCKBn SIBn capture SOBn Reg-R/W INTCBnT interrupt INTCBnR interrupt CBnTSF (ii) CBnCKP = 1, CBnDAP = 0 SCKBn SIBn capture SOBn Reg-R/W INTCBnT interrupt INTCBnR...
Page 435 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (iii) CBnCKP = 0, CBnDAP = 1 SCKBn SIBn capture SOBn Reg-R/W INTCBnT interrupt INTCBnR interrupt CBnTSF (iv) CBnCKP = 1, CBnDAP = 1 SCKBn SIBn capture SOBn Reg-R/W INTCBnT interrupt INTCBnR interrupt CBnTSF Preliminary User’s Manual U16541EJ1V0UM...
Page 436: Output Pins
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6 Output Pins (1) SCKBn pin When CSIBn operation is disabled (CBnPWR bit of CBnCTL0 register = 0), the SCKBn pin output status is as follows. CBnCKP SCKBn Pin Output Fixed to high level Fixed to low level Remarks 1.
Page 437: Operation Flow
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.7 Operation Flow (1) Single transmission START Initial settings Note CBnCTL0 /CBnCTL1, etc. CBnTX write (Transfer start) INTCBnR = 1 Transfer data exists? Note Set the CBnSCE bit to 1 as part of the initial settings. Preliminary User’s Manual U16541EJ1V0UM...
Page 438 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Single reception (master) START Initial settings Note CBnCTL0 /CBnCTL1, etc. CBnRX dummy read INTCBnR = 1 Last data? CBnCTL0: CBnSCE = 0 CBnRX read CBnRX read CBnCTL0: CBnSCE = 1 Note Set the CBnSCE bit to 1 as part of the initial settings. Preliminary User’s Manual U16541EJ1V0UM...
Page 439 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (3) Single reception (slave) START Initial settings CBnCTL0/CBnCTL1, etc. CBnRX dummy read INTCBnR = 1 CBnRX read Last data? Preliminary User’s Manual U16541EJ1V0UM...
Page 440 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (4) Continuous transmission START Initial settings Note CBnCTL0 /CBnCTL1, etc. CBnTX write (Transfer start) INTCBnT = 1 Data to be transferred next exists? Note Set the CBnSCE bit to 1 as part of the initial settings. Remark The steps below the broken line constitute the transmission flow.
Page 441 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (5) Continuous reception (master) START Initial settings Note CBnCTL0 /CBnCTL1, etc. CBnRX dummy read INTCBnR = 1 Data currently transmitted = last data? CBnCTL0: CBnSCE = 0 CBnRX read CBnRX read INTCBnR = 1 CBnRX read CBnCTL0: CBnSCE = 1...
Page 442 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (6) Continuous reception (slave) START Initial settings Note CBnCTL0 /CBnCTL1, etc. CBnRX dummy read INTCBnR = 1 CBnRX read Last data? Note Set the CBnSCE bit to 1 as part of the initial settings. Preliminary User’s Manual U16541EJ1V0UM...
Page 443: Baud Rate Generator
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.8 Baud Rate Generator The BRG1 to BRG3 and CSIB0 to CSIB4 baud rate generators are connected as shown in the following block diagram. BRG1 CSIB0 CSIB1 BRG2 CSIB2 CSIB3 BRG3 CSIB4 (1) Prescaler mode registers 1 to 3 (PRSM1 to PRSM3) The PRSM1 to PRSM3 registers control generation of the baud rate signal for CSIB.
Page 444: Baud Rate Generation
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Prescaler compare registers 1 to 3 (PRSCM1 to PRSCM3) The PRSCM1 to PRSCM3 registers are 8-bit compare registers. These registers can be read or written in 8-bit units. Reset input clears these registers to 00H. After reset: 00H Address: PRSCM1 FFFFF321H, PRSCM2 FFFFF325H, PRSCM3 FFFFF329H...
Page 445: Chapter 17 I C Bus
CHAPTER 17 I C BUS To use the I C bus function, set the P38/SDA00, P39/SCL00, P40/SDA01, P41/SCL01, P90/SDA02, and P91/SCL02 pins to N-ch open-drain output. 17.1 Mode Switching of I C Bus and Other Serial Interfaces 17.1.1 UARTA2 and I C00 mode switching In the V850ES/SG2, UARTA2 and I C00 are alternate functions of the same pin and therefore cannot be used...
Page 446: Csib0 And I C01 Mode Switching
CHAPTER 17 I C BUS 17.1.2 CSIB0 and I C01 mode switching In the V850ES/SG2, CSIB0 and I C01 are alternate functions of the same pin and therefore cannot be used simultaneously. CSIB0 and I C01 switching must be set in advance using the PMC4 and PFC4 registers. Caution The transmit/receive operation of CSIB0 and I C01 is not guaranteed if these functions are switched during transmission or reception.
Page 447: Uarta1 And I C02 Mode Switching
CHAPTER 17 I C BUS 17.1.3 UARTA1 and I C02 mode switching In the V850ES/SG2, UARTA1 and I C02 are alternate functions of the same pin and therefore cannot be used simultaneously. UARTA1 and I C02 switching must be set in advance using the PMC9, PFC9, and PMCE9 registers. Caution The transmit/receive operation of UARTA1 and I C02 is not guaranteed if these functions are switched during transmission or reception.
Page 448: Features
CHAPTER 17 I C BUS 17.2 Features C00 to I C02 have the following two modes. • Operation stopped mode • I C (Inter IC) bus mode (multimasters supported) (1) Operation stopped mode In this mode, serial transfers are not performed, thus enabling a reduction in power consumption. (2) I C bus mode (multimaster support) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock pin (SCL0n) and a...
Page 449 CHAPTER 17 I C BUS Figure 17-4. Block Diagram of I Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n (IICCn) IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn Slave address Start condition Clear register n (SVAn)
Page 450 CHAPTER 17 I C BUS A serial bus configuration example is shown below. Figure 17-5. Serial Bus Configuration Example Using I C Bus Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2 Slave CPU3 Address 3 Slave IC...
Page 451: Configuration
CHAPTER 17 I C BUS 17.3 Configuration C0n includes the following hardware (n = 0 to 2). Table 17-1. Configuration of I Item Configuration Registers IIC shift register n (IICn) Slave address register n (SVAn) Control registers IIC control register n (IICCn) IIC status register n (IICSn) IIC flag register n (IICF0n) IIC clock select register n (IICCLn)
Page 452 CHAPTER 17 I C BUS (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I C interrupt is generated following either of two triggers. • Eighth or ninth clock of the serial clock (set by WTIMn bit of IICCn register) •...
Page 453: Control Registers
CHAPTER 17 I C BUS 17.4 Control Registers C0 to I C2 are controlled by the following registers. • IIC control registers 0 to 2 (IICC0 to IICC2) • IIC status registers 0 to 2 (IICS0 to IICS2) • IIC flag registers 0 to 2 (IICF0 to IICF2) •...
Page 454 CHAPTER 17 I C BUS (1/4) After reset: 00H Address: IICC0 FFFFFD82H, IICC1 FFFFFD92H, IICC2 FFFFFDA2H <7> <6> <5> <4> <3> <2> <1> <0> IICCn IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn (n = 0 to 2) IICEn Specification of I Cn operation enable/disable Operation stopped.
Page 455 CHAPTER 17 I C BUS (2/4) WTIMn Control of wait and Interrupt request generation Interrupt request is generated at the eighth clock’s falling edge. Master mode: After output of eight clocks, clock output is set to low level and wait is set. Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
Page 456 CHAPTER 17 I C BUS (3/4) STTn Start condition trigger Start condition is not generated. When bus is released (in STOP mode): Generates a start condition (for starting as master). The SDA0n line is changed from high level to low level and then the start condition is generated. Next, after the rated amount of time has elapsed, the SCL0n line is changed to low level.
Page 457 CHAPTER 17 I C BUS (4/4) SPTn Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDA0n line goes to low level, either set the SCL0n line to high level or wait until it goes to high level.
Page 458 CHAPTER 17 I C BUS (2) IIC status registers 0 to 2 (IICS0 to IICS2) The IICS0 to IICS2 registers indicate the status of the I C0n bus (n = 0 to 2). These registers are read-only, 8-bit or 1-bit units. Reset input clears these registers to 00H.
Page 459 CHAPTER 17 I C BUS (2/3) COIn Matching addresses detection Addresses do not match. Addresses match. Condition for clearing (COIn bit = 0) Condition for setting (COIn bit = 1) • When a start condition is detected • When the received address matches the local •...
Page 460 CHAPTER 17 I C BUS (3/3) STDn Start condition detection Start condition was not detected. Start condition was detected. This indicates that the address transfer period is in effect Condition for clearing (STDn bit = 0) Condition for setting (STDn bit = 1) •...
Page 461 CHAPTER 17 I C BUS (3) IIC flag registers 0 to 2 (IICF0 to IICF2) The IICF0 to IICF2 registers set the I C0n operation mode and indicate the I C bus status. These registers can be read or written in 8-bit or 1-bit units. However, the STCFn and IICBSYn bits are read- only.
Page 462 CHAPTER 17 I C BUS Note After reset: 00H Address: IICF0 FFFFFD8AH, IICF1 FFFFFD9AH, IICF2 FFFFFDAAH <7> <6> <1> <0> IICFn STCFn IICBSYn STCENn IICRSVn (n = 0 to 2) STCFn STTn bit clear Start condition issued The STTn bit cleared Condition for clearing (STCFn bit = 0) Condition for setting (STCFn bit = 1) •...
Page 463 CHAPTER 17 I C BUS (4) IIC clock select registers 0 to 2 (IICCL0 to IICCL2) The IICCL0 to IICCL2 registers set the transfer clock for the I C0n bus. These registers can be read or written in 8-bit or 1-bit units. However, the CLDn and DADn bits are read-only. The SMCn, CLn1, and CLn0 bits are set by the combination of the CLXn bit of the IICXn register and the OCKSm1 and OCKSm0 bits of the OCKSm register (see 17.4 (6) I C0n transfer clock setting method) (n = 0...
Page 464 CHAPTER 17 I C BUS (5) IIC function expansion registers 0 to 2 (IICX0 to IICX2) The IICX0 to IICS2 registers set I C0n function expansion (valid only in the high-speed mode). These registers can be read or written in 8-bit or 1-bit units. However, the CLDn and DADn bits are read-only. Setting of the CLXn bit is performed in combination with the SMCn, CLn1, and CLn0 bits of the IICCLn register and the OCKSm1 and OCKSm0 bits of the OCKSm register (see 17.4 (6) I C0n transfer clock...
Page 465 CHAPTER 17 I C BUS Table 17-2. Clock Settings (1/2) IICX0 IICCL0 Selection Clock Transfer Settable Main Clock Operating Clock Frequency (f ) Range Mode Bit 0 Bit 3 Bit 1 Bit 0 CLX0 SMC0 CL01 CL00 2.00 MHz ≤ f ≤...
Page 466 CHAPTER 17 I C BUS Table 17-2. Clock Settings (2/2) IICX IICCLm Selection Clock Transfer Settable Main Clock Operating Clock Frequency (f ) Range Mode Bit 0 Bit 3 Bit 1 Bit 0 CLXm SMCm CLm1 CLm0 2.00 MHz ≤ f ≤...
Page 467 CHAPTER 17 I C BUS (7) IIC division clock select registers 0, 1 (OCKS0, OCKS1) The OCKS0 and OCKS1 registers control the I C0n division clock. These registers can be read or written in 8-bit or 1-bit units. Reset input clears these registers to 00H. After reset: 01H Address: OCKS0 FFFFF340H, OCKS1 FFFFF344H OCKSm...
Page 468: I C Bus Mode Functions
CHAPTER 17 I C BUS 17.5 I C Bus Mode Functions 17.5.1 Pin configuration The serial clock pin (SCL0n) and serial data bus pin (SDA0n) are configured as follows (n = 0 to 2). SCL0n ....This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices.
Page 469: I C Bus Definitions And Control Methods
CHAPTER 17 I C BUS 17.6 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the signals used by the I bus. The transfer timing for the “start condition”, “data”, and “stop condition” output via the I C bus’s serial data bus is shown below.
Page 470: Addresses
CHAPTER 17 I C BUS 17.6.2 Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines.
Page 471: Transfer Direction Specification
CHAPTER 17 I C BUS 17.6.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device.
Page 472: Acknowledge Signal (Ack)
CHAPTER 17 I C BUS 17.6.4 Acknowledge signal (ACK) The acknowledge signal (ACK) is used by the transmitting and receiving devices to confirm serial data reception. The receiving device returns one ACK signal for each 8 bits of data it receives. The transmitting device normally receives an ACK signal after transmitting 8 bits of data.
Page 473: Stop Condition
CHAPTER 17 I C BUS 17.6.5 Stop condition When the SCL0n pin is high level, changing the SDA0n pin from low level to high level generates a stop condition (n = 0 to 2). A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed.
Page 474: Wait Signal (Wait)
CHAPTER 17 I C BUS 17.6.6 Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0n pin to low level notifies the communication partner of the wait status. When the wait status has been canceled for both the master and slave devices, the next data transfer can begin (n = 0 to 2).
Page 475 CHAPTER 17 I C BUS Figure 17-13. Wait Signal (2/2) (2) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn bit = 1) Master and slave both wait Master after output of ninth clock. IICn data write (cancel wait) IICn SCL0n...
Page 476: I C Interrupt Request Signals (Intiicn)
CHAPTER 17 I C BUS 17.7 I C Interrupt Request Signals (INTIICn) The following shows the value of the IICSn register at the INTIICn interrupt request signal generation timing and at the INTIICn signal timing (n = 0 to 2). 17.7.1 Master device operation (1) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1>...
Page 477 CHAPTER 17 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn bit = 0 STTn bit = 1 SPTn bit = 1 ↓ ↓ AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆7...
Page 478 CHAPTER 17 I C BUS (3) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn bit = 0 SPTn bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 ∆5 L1: IICSn register = 1010X110B L2: IICSn register = 1010X000B L3: IICSn register = 1010X000B (WTIMn bit = 1) L4: IICSn register = 1010XX00B...
Page 479: Slave Device Operation (When Receiving Slave Address Data (Matches With Address))
CHAPTER 17 I C BUS 17.7.2 Slave device operation (when receiving slave address data (matches with address)) (1) Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICSn register = 0001X110B L2: IICSn register = 0001X000B...
Page 480 CHAPTER 17 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, match with address) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn register = 0001X110B L2: IICSn register = 0001X000B...
Page 481 CHAPTER 17 I C BUS (3) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn register = 0001X110B L2: IICSn register = 0001X000B...
Page 482 CHAPTER 17 I C BUS (4) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, mismatch with address (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆4...
Page 483: Slave Device Operation (When Receiving Extension Code)
CHAPTER 17 I C BUS 17.7.3 Slave device operation (when receiving extension code) (1) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICSn register = 0010X010B L2: IICSn register = 0010X000B L3: IICSn register = 0010X000B ∆...
Page 484 CHAPTER 17 I C BUS (2) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, match with address) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn register = 0010X010B L2: IICSn register = 0010X000B...
Page 485 CHAPTER 17 I C BUS (3) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICSn register = 0010X010B L2: IICSn register = 0010X000B...
Page 486 CHAPTER 17 I C BUS (4) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, mismatch with address (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆4...
Page 487: Operation Without Communication
CHAPTER 17 I C BUS 17.7.4 Operation without communication (1) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 ∆1 ∆ 1: IICSn register = 00000001B Remarks 1. ∆: Generated only when SPIEn bit = 1 2.
Page 488 CHAPTER 17 I C BUS (2) When arbitration loss occurs during transmission of extension code <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICSn register = 0110X010B (Example: when ALDn bit is read during interrupt servicing) L2: IICSn register = 0010X000B L3: IICSn register = 0010X000B ∆...
Page 489: Operation When Arbitration Loss Occurs (No Communication After Arbitration Loss)
CHAPTER 17 I C BUS 17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) (1) When arbitration loss occurs during transmission of slave address data AD6 to AD0 D7 to D0 D7 to D0 ∆2 L1: IICSn register = 01000110B (Example: when ALDn bit is read during interrupt servicing) ∆...
Page 490 CHAPTER 17 I C BUS (3) When arbitration loss occurs during data transfer <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆3 L1: IICSn register = 10001110B L2: IICSn register = 01000000B (Example: when ALDn bit is read during interrupt servicing) ∆...
Page 491 CHAPTER 17 I C BUS (4) When arbitration loss occurs due to restart condition during data transfer <1> Not extension code (Example: mismatches with address) AD6 to AD0 D7 to Dn AD6 to AD0 D7 to D0 ∆3 L1: IICSn register = 1000X110B L2: IICSn register = 01000110B (Example: when ALDn bit is read during interrupt servicing) ∆...
Page 492 CHAPTER 17 I C BUS (5) When arbitration loss occurs due to stop condition during data transfer AD6 to AD0 D7 to Dn ∆2 L1: IICSn register = 1000X110B ∆ 2: IICSn register = 01000001B Remarks 1. L: Always generated ∆: Generated only when SPIEn bit = 1 X: don’t care 2.
Page 493 CHAPTER 17 I C BUS (7) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition When WTIMn bit = 1 STTn bit = 1 ↓ AD6 to AD0 D7 to D0 ∆3 L1: IICSn register = 1000X110B L2: IICSn register = 1000XX00B ∆...
Page 494: Interrupt Request Signal (Intiicn) Generation Timing And Wait Control
CHAPTER 17 I C BUS 17.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control The setting of the WTIMn bit of the IICCn register determines the timing by which the INTIICn register is generated and the corresponding wait control, as shown below (n = 0 to 2). Table 17-3.
Page 495: Address Match Detection Method
CHAPTER 17 I C BUS 17.9 Address Match Detection Method In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. The INTIICn signal occurs when a local address has been set to the SVAn register and when the address set to the SVAn register matches the slave address sent by the master device, or when an extension code has been received (n = 0 to 2).
Page 496: Arbitration
CHAPTER 17 I C BUS 17.12 Arbitration When several master devices simultaneously output a start condition (when IICCn.STTn bit is set to 1 before IICSn.STDn bit is set to 1), communication among the master devices is performed while the number of clocks are being adjusted until the data differs.
Page 497: Wakeup Function
CHAPTER 17 I C BUS Table 17-5. Status During Arbitration and Interrupt Request Signal Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 During address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission...
Page 498: Communication Reservation
CHAPTER 17 I C BUS 17.14 Communication Reservation 17.14.1 When communication reservation function is enabled (IICRSVn bit of IICFn register = 0) To start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used.
Page 499 CHAPTER 17 I C BUS Table 17-6. Wait Periods Selection Clock CLXn SMCn CLn1 CLn0 Wait Period (when OCKSm = 14H set) 26 clocks /2 (when OCKSm = 10H set) 52 clocks /3 (when OCKSm = 11H set) 78 clocks /4 (when OCKSm = 12H set) 104 clocks /5 (when OCKSm = 13H set)
Page 500 CHAPTER 17 I C BUS Figure 17-15. Communication Reservation Timing STTn Write to Program processing IICn Set SPDn Communication Hardware processing reservation and INTIICn STDn SCL0n SDA0n Output by master with bus access IICn: IIC shift register n STTn: Bit 1 of IIC control register n (IICCn) STDn: Bit 1 of IIC status register n (IICSn) SPDn: Bit 0 of IIC status register n (IICSn)
Page 501 CHAPTER 17 I C BUS The communication reservation flowchart is illustrated below. Figure 17-17. Communication Reservation Flowchart SET1 STTn Sets STTn bit (communication reservation). Define communication Defines that communication reservation is in effect reservation (defines and sets user flag to any part of RAM). Secures wait period set by software (see Table 17-16).
Page 502: When Communication Reservation Function Is Disabled (Iicrsvn Bit Of Iicfn Register = 1)
CHAPTER 17 I C BUS 17.14.2 When communication reservation function is disabled (IICRSVn bit of IICFn register = 1) When the STTn bit of the IICCn register is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated.
Page 503: Cautions
CHAPTER 17 I C BUS 17.15 Cautions (1) When STCENn bit of IICFn register = 0 Immediately after the I C0n operation is enabled, the bus communication status (IICBSYn bit of IICFn register = 1) is recognized regardless of the actual bus status. To execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication.
Page 504: Communication Operations
CHAPTER 17 I C BUS 17.16 Communication Operations 17.16.1 Master operation 1 The following shows the flowchart for master communication when the communication reservation function is enabled (IICRSVn bit of IICFn register = 0) and the master operation is started after a stop condition is detected (STCENn bit of IICFn register = 0).
Page 505 CHAPTER 17 I C BUS Figure 17-18. Master Operation Flowchart (1) START ← ××H IICCLn Select transfer clock ← ××H IICCn IICEn = SPIEn = WTIMn = 1 INTIICn = 1? Yes (stop condition detection) STTn = 1 Wait time is secured by Wait software (see Table 17-6) Communication reservation...
Page 506: Master Operation 2
CHAPTER 17 I C BUS 17.16.2 Master operation 2 The following shows the flowchart for master communication when the communication reservation function is disabled (IICRSVn bit = 1) and the master operation is started without detecting a stop condition (STCENn bit = 1). Figure 17-19.
Page 507: Slave Operation
CHAPTER 17 I C BUS 17.16.3 Slave operation The following shows the flowchart for slave communication. Figure 17-20. Slave Operation Flowchart START ← ××H IICCn IICEn = 1 INTIICn = 1? EXCn = 1? Communicate? COIn = 1? LRELn = 1 No (receive) TRCn = 1? WTIMn = 0...
Page 508: Timing Of Data Communication
CHAPTER 17 I C BUS 17.17 Timing of Data Communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRCn bit of the IICSn register, which specifies the data transfer direction, and then starts serial communication with the slave device.
Page 509 CHAPTER 17 I C BUS Figure 17-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ Address Processing by master device ← ← IICn IICn address IICn data ACKDn STDn SPDn...
Page 510 CHAPTER 17 I C BUS Figure 17-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device ← ← IICn IICn data IICn data ACKDn STDn SPDn WTIMn ACKEn MSTSn...
Page 511 CHAPTER 17 I C BUS Figure 17-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IICn IICn data IICn address ACKDn STDn SPDn WTIMn ACKEn...
Page 512 CHAPTER 17 I C BUS Figure 17-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ Address Processing by master device ← ← IICn IICn address IICn FFH Note ACKDn STDn SPDn...
Page 513 CHAPTER 17 I C BUS Figure 17-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IICn ← FFH Note IICn ← FFH Note IICn ACKDn STDn SPDn WTIMn...
Page 514 CHAPTER 17 I C BUS Figure 17-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IICn IICn FFH Note IICn address ACKDn STDn SPDn WTIMn...
Page 515: Chapter 18 Iebus Controller
CHAPTER 18 IEBus CONTROLLER IEBus (Inter Equipment Bus) is a small-scale digital data transfer system that transfers data between units. To implement IEBus with the V850ES/SG2, an external IEBus driver and receiver are necessary because they are not provided. The internal IEBus controller of the V850ES/SG2 is of negative logic. The following models of the V850ES/SG2 have an on-chip IEBus controller.
Page 516: Determination Of Bus Mastership (Arbitration)
CHAPTER 18 IEBus CONTROLLER 18.1.2 Determination of bus mastership (arbitration) An operation to occupy the bus is performed when a unit connected to the IEBus controls the other units. This operation is called arbitration. When two or more units simultaneously start transmission, arbitration is used to grant one of the units the permission to occupy the bus.
Page 517: Broadcast Communication
CHAPTER 18 IEBus CONTROLLER 18.1.5 Broadcast communication Normally, transmission or reception is performed between the master unit and its partner slave unit on a one-to- one basis. During broadcast communication, however, two or more slave units exist and the master unit executes transmission to these slave units.
Page 518 CHAPTER 18 IEBus CONTROLLER (2) Broadcast bit This bit indicates whether the master selects one slave (individual communication) or multiple slaves (broadcast communication) as the other party of communication. When the broadcast bit is 0, it indicates broadcast communication; when it is 1, individual communication is indicated.
Page 519 CHAPTER 18 IEBus CONTROLLER (4) Slave address field The master outputs the address of the unit with which it is to communicate. Figure 18-3 shows the configuration of the slave address field. A parity bit is output after a 12-bit slave address has been transmitted in order to prevent a wrong slave address from being received by mistake.
Page 520 CHAPTER 18 IEBus CONTROLLER Table 18-2. Contents of Control Bits Note 1 Bit 3 Bit 2 Bit 1 Bit 0 Function Read slave status Undefined Undefined Note 2 Read data and lock Note 3 Read lock address (lower 8 bits) Note 3 Read lock address (higher 4 bits) Note 2...
Page 521 CHAPTER 18 IEBus CONTROLLER If the control bit received from the master unit is not as shown in Table 18-3, the unit locked by the master unit rejects acknowledging the control bit, and outputs the NACK signal. Table 18-3. Control Field for Locked Slave Unit Note 1 Bit 3 Bit 2...
Page 522 Table 18-5. Acknowledge Signal Output Condition of Control Field (a) If received control data is AH, BH, EH, or FH Communication Type Communication Target Lock Status Master Unit Slave Transmission Slave Reception Received Control Data (USR.ALLTRANS bit) (USR.SLVRQ bit) (USR.LOCK bit) Identification (Match Enable Enable...
Page 523 CHAPTER 18 IEBus CONTROLLER (6) Telegraph length field This field is output by the transmission side to inform the reception side of the number of bytes of the transmit data. The configuration of the telegraph length field is as shown in Figure 18-5. Table 18-6 shows the relationship between the telegraph length bit and the number of transmit data.
Page 524 CHAPTER 18 IEBus CONTROLLER (7) Data field This is data output by the transmission side. The master unit transmits or receives data to or from a slave unit by using the data field. The configuration of the data field is as shown below. Figure 18-6.
Page 525 CHAPTER 18 IEBus CONTROLLER (b) When master receives data When the master unit reads data from a slave unit, the master unit outputs a sync signal corresponding to all the read bits. The slave unit outputs the contents of the data and parity bits to the bus in response to the sync signal from the master unit.
Page 526 CHAPTER 18 IEBus CONTROLLER (b) Last acknowledge bit of control field The last acknowledge bit of the control field serves as a NACK signal in any of the following cases, and transmission is stopped. • If the parity of the control bit is incorrect •...
Page 527: Transfer Data
CHAPTER 18 IEBus CONTROLLER 18.1.7 Transfer data (1) Slave status The master unit can learn why the slave unit did not return the ACK signal by reading the slave status. The slave status is determined according to the result of the last communication the slave unit has executed. All the slave units can supply information on the slave status.
Page 528 CHAPTER 18 IEBus CONTROLLER (2) Lock address When the lock address is read (control bit: 4H or 5H), the address (12 bits) of the master unit that has issued the lock instruction is configured in 1-byte units as shown below and read. Figure 18-8.
Page 529: Bit Format
CHAPTER 18 IEBus CONTROLLER Table 18-7. Lock Setting Conditions Control Data Broadcast Communication Individual Communication Communication End Frame End Communication End Frame End Note 3H, 6H Cannot be locked Lock set AH, BH Cannot be locked Cannot be locked Cannot be locked Lock set 0H, 4H, 5H, EH, FH Cannot be locked...
Page 530: Configuration
CHAPTER 18 IEBus CONTROLLER 18.2 Configuration The block diagram of the IEBus controller is shown below. Figure 18-10. IEBus Controller Block Diagram Internal bus SSR, USR, RAR, UAR, BCR, PSR, ISR OCKS2 FSR, SCR, ESR, CDR, DLR, DR Internal register block Prescaler to f Prescaler block...
Page 531 CHAPTER 18 IEBus CONTROLLER (a) Interrupt control block This control block transfers interrupt request signals from the IEBus controller to the CPU. (b) Internal registers These registers set data to the control registers and fields that control IEBus (for the internal registers, refer to 18.3 Control Registers).
Page 532: Control Registers
CHAPTER 18 IEBus CONTROLLER 18.3 Control Registers The registers that control the IEBus controller are shown below. Table 18-9. Control Registers of IEBus Controller Address Function Register Name Symbol Bit Unit for Manipulation After Reset √ FFFFF348H IEBus clock select register OCKS2 √...
Page 533 CHAPTER 18 IEBus CONTROLLER (1) IEBus control register (BCR) The BCR register is an 8-bit register that controls the operations of the IEBus controller. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H RW Address: FFFFF360H <7>...
Page 534 CHAPTER 18 IEBus CONTROLLER (a) Communication enable flag (ENIEBUS)...Bit 7 <Set/clear conditions> Set: By software Clear: By software The IEBus controller participates in communication differently depending on the timing of setting the ENIEBUS bit (1), as follows. Table 18-10. Timing of Setting ENIEBUS Bit and Participation in Communication Timing of Setting ENIEBUS Bit How IEBus Controller Participates in Communication If communication is not performed on IEBus...
Page 535 CHAPTER 18 IEBus CONTROLLER (b) Master request flag (MSTRQ)...Bit 6 <Set/clear conditions> Set: By software Clear: Cleared (0) by hardware when master communication is started and immediately before the start interrupt of the master occurs. Cleared (0) by hardware before a communication error occurs. When the ENIEBUS bit is cleared.
Page 536 CHAPTER 18 IEBus CONTROLLER (d) Slave transmission enable flag (ENSLVTX)...Bit 4 <Set/clear conditions> Set: By software Clear: By software Cautions 1. The ENSLVTX bit must be set before the parity bit in the control field is received. 2. Clear the ENSLVTX bit (0) before setting the MSTRQ bit (1) when making a master request.
Page 537 CHAPTER 18 IEBus CONTROLLER (2) IEBus power save register (PSR) The PSR register is an 8-bit register that controls the internal clock and communication mode of the IEBus controller. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 538 CHAPTER 18 IEBus CONTROLLER (3) IEBus slave status register (SSR) The SSR register is an 8-bit register that indicates the communication status of the slave unit. After receiving a slave status transmission request from the master, read this register by software, and write a slave status to the DR register to transmit the slave status.
Page 539 CHAPTER 18 IEBus CONTROLLER (4) IEBus unit status register (USR) The USR register is an 8-bit register that indicates the IEBus unit status. This register is read-only, in 8-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF363H SLVRQ ARBIT...
Page 540 CHAPTER 18 IEBus CONTROLLER (a) Slave request flag (SLVRQ)...Bit 6 A flag indicating whether there has been a slave request from the master. <Set/clear conditions> Set: When the unit is requested as a slave (if the condition in Table 18-13 Slave Request Condition (SLVRQ Bit Setting Condition) is satisfied), this flag is set (1) by hardware when the acknowledge period of the slave address field starts.
Page 541 CHAPTER 18 IEBus CONTROLLER (c) Broadcast communication flag (ALLTRNS)...Bit 4 Flag indicating whether the unit is performing broadcast communication. The contents of the flag are updated in the broadcast field of each frame. Except for initialization (reset) by system reset, the set/clear conditions vary depending on the receive data of the broadcast field bit.
Page 542 CHAPTER 18 IEBus CONTROLLER (5) IEBus interrupt status register (ISR) The ISR register indicates the interrupt source when IEBus issues an interrupt request signal. This register is read to generate an interrupt request signal, after which the specified interrupt processing is carried out. This register can be read or written in 8-bit or 1-bit units.
Page 543 CHAPTER 18 IEBus CONTROLLER (a) Communication error flag (IEERR)...Bit 6 A flag that indicates a communication error has occurred. When a communication error occurs, the INTIE2 and INTERR interrupt request signals are generated. <Set/clear conditions> Set: The flag is set (1) if a timing error, parity error (except in the data field), NACK reception error (except in the data field), underrun error, overrun error (that occurs during broadcast communication reception), or write error occurs.
Page 544 CHAPTER 18 IEBus CONTROLLER (e) Frame end flag (ENDFRAM)...Bit 2 A flag that indicates whether communication ends after the maximum number of bytes (mode 1: 32 bytes, mode 2: 128 bytes) have been transferred. <Set/clear conditions> Set: This flag is set (1) when the count value of the CCR register is 00H. Clear: This flag is cleared (0) if the start interrupt, status transmission interrupt, communication end interrupt (if the frame end interrupt does not occur), or INTIE1 interrupt request signal is generated Cautions 1.
Page 545 CHAPTER 18 IEBus CONTROLLER (6) IEBus error status register (ESR) The ESR register indicates the source of the communication error interrupt request signal of IEBus. Each bit of this register is set (1) as soon as the communication error flag (ISR.IEERR bit) is set (1). The source of a communication error, if any, can be identified by checking the contents of this register.
Page 546 CHAPTER 18 IEBus CONTROLLER (a) Timing error occurrence flag (TERR)…Bit 7 <Set/clear conditions> Set: This flag is set (1) if a timing error occurs. Clear: By software A timing error occurs if the high-/low-level width of the communication bit is not the defined value. The defined value of the high- and low-level width is set to the bit processing block and monitored by the internal timer.
Page 547 CHAPTER 18 IEBus CONTROLLER (d) Underrun error occurrence flag (UERR) … Bit 4 <Set/clear conditions> Set: This flag is set (1) if an underrun error occurs. Clear: By software An underrun error occurs if the next data is not transmitted to the DR register in time before the ACK signal is received.
Page 548 CHAPTER 18 IEBus CONTROLLER (e) Overrun error occurrence flag (OERR) … Bit 3 <Set/clear conditions> Set: This flag is set (1) if an overrun error occurs. Clear: By software If 1-byte data is stored in the DR register while the IEBus controller serves as a receiver unit, the data request interrupt request signal (INTIE1) is generated, and the DR register is read by means of DMA or by software.
Page 549 CHAPTER 18 IEBus CONTROLLER (f) Write error occurrence flag (WERR) … Bit 2 <Set/clear conditions> Set: This flag is set (1) if a write error occurs. Clear: By software A write error occurs if the data written to the DR register is not transmitted in the data field during unit transmission.
Page 550 CHAPTER 18 IEBus CONTROLLER (7) IEBus unit address register (UAR) The UAR register sets the unit address of an IEBus unit. This register must always be set before starting communication. Sets the unit address (12 bits) to bits 11 to 0. This register can be read or written in 16-bit units.
Page 551 CHAPTER 18 IEBus CONTROLLER (10) IEBus receive slave address register (RSA) The RSA register stores the slave address value received in the slave address field regardless of whether the unit is operating as the master or a slave. This register is read-only, in 16-bit units. Reset input clears this register to 0000H.
Page 552 CHAPTER 18 IEBus CONTROLLER After reset: 00H Address: FFFFF36EH SELCL2 SELCL1 SELCL0 SELCL2 SELCL1 SELCL0 Function Read slave status Undefined Undefined Read data and lock Read lock address (lower 8 bits) Read lock address (lower 4 bits) Read slave status and unlock Read data Undefined Undefined...
Page 553 CHAPTER 18 IEBus CONTROLLER (c) Slave status return operation When IEBus receives a request to transfer from master to slave status or a lock address request (control data: 0H, 6H), whether the ACK/NACK signal in the control field is returned or not depends on the status of the IEBus unit.
Page 554 CHAPTER 18 IEBus CONTROLLER Figure 18-17. Interrupt Request Signal Generation Timing (for (2) and (5)) Control field IEBus sequence Control bit (4 bits) Parity bit (1 bit) Acknowledge bit (1 bit) Terminated by communication error INTIE2 INTSTA INTERR Set by reception of 0H, 4H, 5H, 6H Cleared by software STATUSF...
Page 555 CHAPTER 18 IEBus CONTROLLER Figure 18-19. Timing of INTIE2 and INTSTA Interrupt Request Signal Generation in Locked State (for (3)) Broad- Start Master address Slave address Control Telegraph length Data IEBus sequence cast (12 + P) (12 + P + A) (4 + P + A) (8 + P + A) (8 + P + A)
Page 556 CHAPTER 18 IEBus CONTROLLER (12) IEBus telegraph length register (DLR) The DLR register can be read or written in 8-bit units. Reset input sets this register to 01H. (a) When transmission unit ... Master transmission, slave transmission The data of this register is reflected in the data transmitted in the telegraph length field and indicates the number of bytes of the transmit data.
Page 557 CHAPTER 18 IEBus CONTROLLER (13) IEBus data register (DR) The DR register sets the communication data (8 bits) to bits 7 to 0. This register can be read or written in 8-bit units. Reset input clears this register to 00H. Remark The DR register consists of a write register and a read register.
Page 558 CHAPTER 18 IEBus CONTROLLER (14) IEBus field status register (FSR) The FSR register stores the status of the field status of the IEBus controller if an interrupt request signal (INTIE1, INTIE2, INTSTA, or INTERR) is generated. This register is read-only, in 8-bit units. Reset input clears this register to 00H.
Page 559 CHAPTER 18 IEBus CONTROLLER (15) IEBus success count register (SCR) The SCR register indicates the number of remaining communication bytes. The count value of the counter in which the value set by the DLR register is decremented by the ACK signal in the data field is read from this register.
Page 560 CHAPTER 18 IEBus CONTROLLER (16) IEBus communication count register (CCR) The CCR register indicates the number of bytes remaining from the communication byte number specified by the communication mode. This register indicates the number of transfer bytes. The maximum number of transmitted bytes per frame defined in each mode (mode 1: 32 bytes, mode 2: 128 bytes) is preset to this register.
Page 561 CHAPTER 18 IEBus CONTROLLER (17) IEBus clock select register (OCKS2) The OCKS2 register selects the clock of IEBus. The main clock frequencies that can be used are shown below. No other main clock frequencies can be used. This register can be read or written in 8-bit units. Reset input clears this register to 00H.
Page 562: Interrupt Operations Of Iebus Controller
CHAPTER 18 IEBus CONTROLLER 18.4 Interrupt Operations of IEBus Controller 18.4.1 Interrupt control block Interrupt request signal <1> Communication error IEERR (i) Timing error: TERR (ii) Parity error: PERR (iii) NACK receive error: NERR (iv) Underrun error: UERR (v) Overrun error: OERR (vi) Write error: WERR...
Page 563 CHAPTER 18 IEBus CONTROLLER Figure 18-20. Configuration of Interrupt Control Block TERR PERR NERR INTERR UERR OERR WERR INTIE2 STARTF STATUSF INTSTA ENDTRNS ENDFRAM STATTX INTIE1 STATRX Interrupt control block INTC of V850ES/SG2 IEBus controller Cautions 1. The logical sum (OR) output of the STATRX and STATTX signals is treated as an interrupt request signal (INTIE1).
Page 564: Example Of Identifying Interrupt
CHAPTER 18 IEBus CONTROLLER 18.4.2 Example of identifying interrupt The IEBus controller processes interrupts in the following two ways. • Using three interrupt request signals: INTIE1, INTERR, and INTSTA • Using two interrupt request signals: INTIE1 and INTIE2 Caution Mask the interrupt sources that are not used so that the interrupts do not occur. How an interrupt is identified in each of the above cases is explained below.
Page 565 CHAPTER 18 IEBus CONTROLLER Figure 18-23. Example of Identifying INTSTA Signal Interrupt (When INTIE1, INTERR, and INTSTA Signals Are Used) INTSTA signal generated register STARTF Start interrupt occurs register Arbitration loss detection ARBIT Remaster processing SLVRQ Slave request identification STATUSF Status transmission identification Status transmission processing register...
Page 566 CHAPTER 18 IEBus CONTROLLER Figure 18-25. Example of Identifying INTIE2 Signal Interrupt (When INTIE1 and INTIE2 Signals Are Used) INTIE2 signal generated register IEERR Communication error identification Error source identification register TEER PEER NEER UEER OEER WEER STARTF Start interrupt occurs register Arbitration loss detection ARBIT...
Page 567: Interrupt Source List
CHAPTER 18 IEBus CONTROLLER 18.4.3 Interrupt source list The interrupt request signals of the internal IEBus controller in the V850ES/SG2 can be classified into vector interrupts and DMA transfer interrupts. These interrupt request signals can be specified via software manipulation. The interrupt sources are listed below.
Page 568: Communication Error Source Processing List
CHAPTER 18 IEBus CONTROLLER 18.4.4 Communication error source processing list The following table shows the occurrence conditions of the communication errors (timing error, NACK reception error, overrun error, underrun error, parity error, and write error), error processing by the IEBus controller, and examples of processing by software.
Page 569 CHAPTER 18 IEBus CONTROLLER Table 18-18. Communication Error Source Processing List (2/2) Overrun Error Underrun Error/Write Error Occurrence Unit status Reception Transmission condition Occurrence DR register cannot be read in time before the DR register cannot be written in time before condition next data is received.
Page 570: Interrupt Request Signal Generation Timing And Main Cpu Processing
CHAPTER 18 IEBus CONTROLLER 18.5 Interrupt Request Signal Generation Timing and Main CPU Processing 18.5.1 Master transmission Initial preparation processing: Sets a unit address, slave address, control data, telegraph length, and the first byte of the transmit data. Communication start processing: Set the BCR register (enable communication, master request, and slave reception).
Page 571 CHAPTER 18 IEBus CONTROLLER (1) Slave reception processing If a slave reception request is confirmed during vector interrupt servicing, the data transfer direction of the macro service must change from RAM → on-chip peripheral I/O to on-chip peripheral I/O → RAM until the first data is received.
Page 572: Master Reception
CHAPTER 18 IEBus CONTROLLER 18.5.2 Master reception Before performing master reception, it is necessary to notify the unit that will be the slave of slave transmission. Therefore, more than two communication frames are necessary for master reception. The slave unit prepares the transmit data, sets (1) the slave transmission enable flag (BCR.ENSLVTX bit), and waits. Initial preparation processing: Set a unit address, slave address, and control data.
Page 573 CHAPTER 18 IEBus CONTROLLER (1) Interrupt request signal (INTIE1) occurrence If the NACK signal is transmitted (hardware processing) in the data field, an interrupt request signal (INTIE1) is not issued to the INTC, and the same data is retransmitted from the slave. If the receive data is not read by the time the next data is received, the hardware automatically transmits the NACK signal.
Page 574: Slave Transmission
CHAPTER 18 IEBus CONTROLLER 18.5.3 Slave transmission Initial preparation processing: Set a unit address, telegraph length, and the first byte of the transmit data. Communication start processing: Set the BCR register (enable communication, slave transmission, and slave reception). Figure 18-28. Slave Transmission µ...
Page 575 CHAPTER 18 IEBus CONTROLLER (1) Interrupt request signal (INTIE1) occurrence If the NACK signal is received from the master in the data field, an interrupt request signal (INTIE1) is not issued to the INTC, and the same data is retransmitted by hardware. If the transmit data is not written in time during the period of writing the next data, a communication error interrupt request signal (INTERR) occurs due to occurrence of underrun, and communication is abnormally ended.
Page 576: Slave Reception
CHAPTER 18 IEBus CONTROLLER 18.5.4 Slave reception Initial preparation processing: Set a unit address. Communication start processing: Set the BCR register (enable communication, disables slave transmission, and enables slave reception). Figure 18-29. Slave Reception µ Approx. 1,014 s (mode 1, at 6.29 MHz) <1>...
Page 577 CHAPTER 18 IEBus CONTROLLER (1) Interrupt request signal (INTIE1) occurrence If the NACK signal is transmitted in the data field, an interrupt request signal (INTIE1) is not issued to the INTC, and the same data is retransmitted from the master. If the receive data is not read by the time the next data is received, the NACK signal is automatically transmitted.
Page 578: Interval Of Occurrence Of Interrupt Request Signal For Iebus Control
CHAPTER 18 IEBus CONTROLLER 18.5.5 Interval of occurrence of interrupt request signal for IEBus control Each control interrupt request signal must occur at each point of communication and perform the necessary processing until the next interrupt request signal occurs. Therefore, the IEBus control block is controlled by software, taking the shortest time of this interrupt request signal occurrence interval into consideration.
Page 579 CHAPTER 18 IEBus CONTROLLER (2) Master reception Figure 18-31. Master Reception (Interval of Interrupt Request Signal Occurrence) Telegraph Broad- Start bit Slave address Control Data Master address cast length Communication starts Communication start interrupt Data Data Data End of communication End of frame Remarks 1.
Page 580 CHAPTER 18 IEBus CONTROLLER (3) Slave transmission Figure 18-32. Slave Transmission (Interval of Interrupt Request Signal Occurrence) Broad- Telegraph Start bit Master address Slave address Control Data cast length Communication starts Communication Status request start interrupt Data Data Data End of communication End of frame Remarks 1.
Page 581 CHAPTER 18 IEBus CONTROLLER (4) Slave reception Figure 18-33. Slave Reception (Interval of Interrupt Request Signal Occurrence) Telegraph Broad- Start bit Master address Slave address Control Data cast length Communication starts Communication start interrupt Data Data Data End of communication End of frame Remarks 1.
Page 582: Chapter 19 Can Controller
CHAPTER 19 CAN CONTROLLER 19.1 Outline The V850ES/SG2 features an on-chip 1-channel CAN (Controller Area Network) controller that complies with the CAN protocol as standardized in ISO 11898. The V850ES/SG2 products with an on-chip CAN controller are as follows. • µ PD703280, 703280Y, 703281, 703281Y, 703282, 703282Y, 703283, 703283Y, 70F3281, 70F3281Y, 70F3283, 70F3283Y 19.1.1 Features •...
Page 583: Overview Of Functions
CHAPTER 19 CAN CONTROLLER 19.1.2 Overview of functions Table 19-1 presents an overview of CAN controller functions. Table 19-1. Overview of Functions Function Description Protocol CAN Protocol ISO 11898 (standard and extended frame transmission/reception) Maximum 1 Mbps (@CAN clock input ≥ 8 MHz) Baud rate Data storage 32 message buffers/channel...
Page 584: Configuration
The CAN controller is composed of the following four blocks. (1) NPB interface This functional block provides an NPB (NEC peripheral I/O bus) interface and a means of transmitting and receiving signals between the CAN and the host CPU. (2) MAC (Memory Access Controller) This functional block controls access to the CAN protocol layer and to the CAN RAM within the CAN module.
Page 585: Can Protocol
CHAPTER 19 CAN CONTROLLER 19.2 CAN Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications. The CAN specification is generally divided into two layers: a physical layer and a data link layer. In turn, the data link layer includes logical link control and medium access control.
Page 586: Frame Types
CHAPTER 19 CAN CONTROLLER 19.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 19-2. Frame Types Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Overload frame...
Page 587 CHAPTER 19 CAN CONTROLLER (2) Remote frame A remote frame is composed of six fields. Figure 19-4. Remote Frame Remote frame <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Remarks 1.
Page 588 CHAPTER 19 CAN CONTROLLER <2> Arbitration field The arbitration field is used to evaluate the priority between data frames, remote frames, and frame formats (standard or extended identifier). Figure 19-6. Arbitration Field (in Standard Format Mode) Arbitration field (Control field) Identifier (r1) ID28 ·...
Page 589 CHAPTER 19 CAN CONTROLLER <3> Control field The control field sets “N” as the number of data bytes in the data field (N = 0 to 8). Figure 19-8. Control Field (Arbitration field) Control field (Data field) DLC3 DLC2 DLC1 DLC0 (IDE) Remark...
Page 590 CHAPTER 19 CAN CONTROLLER <4> Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. Figure 19-9. Data Field (Control field) Data field (CRC field) Data Data (8 bits)
Page 591 CHAPTER 19 CAN CONTROLLER <6> ACK field The ACK field is used to confirm normal reception. Figure 19-11. ACK Field (CRC field) ACK field (End of frame) ACK slot ACK delimiter (1 bit) (1 bit) Remark D: Dominant = 0 R: Recessive = 1 •...
Page 592 CHAPTER 19 CAN CONTROLLER <8> Interframe space The interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. • The length of this field differs depending on the error status. (a) Error active node The error active node inserts a 3-bit intermission field before bus idle is encountered or another frame is transmitted.
Page 593 CHAPTER 19 CAN CONTROLLER • Operation in error status Table 19-6. Operation in Error Status Error Status Operation Error active Any node in this state is able to start a transmission whenever the bus is idle. Error passive Any node in this state has to wait for 11 consecutive recessive bits before initiating a transmission.
Page 594: Error Frame
CHAPTER 19 CAN CONTROLLER 19.2.4 Error frame • This frame is sent from a node if an error is detected. • The type of error frame is defined by its error flag: an active error flag or passive error flag. Which kind of flag a node transmits after detecting an error condition depends on the internal count of the error counters of each node.
Page 595: Overload Frame
CHAPTER 19 CAN CONTROLLER 19.2.5 Overload frame An overload frame is transmitted under the following conditions. • When the receiving node is not yet ready to receive. • If a dominant level is detected at the first two bits in intermission mode. •...
Page 596: Functions
CHAPTER 19 CAN CONTROLLER 19.3 Functions 19.3.1 Arbitration If two or more nodes happen to start transmission at the same time, the access conflict is solved by a bit-wise arbitration mechanism during transmission of the arbitration field. (1) When a node starts transmission During bus idle, the node having the output data can transmit.
Page 597: Bit Stuffing
CHAPTER 19 CAN CONTROLLER 19.3.2 Bit stuffing When the same level continues for more than 5 bits, bit stuffing (inserting 1 bit with the inverse level) takes place. • Due to this, resynchronization of the bit timing can be done at least every 10 bits. •...
Page 598: Error Control Function
CHAPTER 19 CAN CONTROLLER 19.3.6 Error control function (1) Error types Table 19-12. Error Types Type Description of Error Detection State Detection Method Detection Transmission/ Field/Frame Condition Reception Bit error Comparison of output level and Mismatch of levels Transmission/ Bit that output data on the bus level on the bus (except stuff bit) reception node at the start of frame to the end...
Page 599 CHAPTER 19 CAN CONTROLLER (4) Error state (a) Types of error state • There are three types of error state: error active, error passive and bus off. • The transmission error counter (TEC) and the reception error counter (REC) control the error state. •...
Page 600 CHAPTER 19 CAN CONTROLLER (b) Error counter • The error counter counts up when an error has occurred, and counts down upon successful transmission and reception. The error counters are updated at the first bit of an error flag. Table 19-15. Error Counter State Transmission Error Reception Error Counter...
Page 601: Baud Rate Control Function
CHAPTER 19 CAN CONTROLLER 19.3.7 Baud rate control function (1) Nominal bit time (8 to 25 time quanta) • The definition of 1 data bit time is as follows. Figure 19-17. Nominal Bit Time (8 to 25 Time Quanta) Nominal bit time Sync Prop Phase...
Page 602 CHAPTER 19 CAN CONTROLLER (2) Adjusting synchronization of the data bit • The transmission node transmits data synchronized with the transmission node bit timing. • The reception node adjusts synchronization at recessive to dominant edges on the bus. Depending on the protocol this synchronization can be a hard or soft synchronization. (a) Hard synchronization This type of synchronization is performed when the reception node detects a start of frame in the bus idle state.
Page 603 CHAPTER 19 CAN CONTROLLER (b) Soft synchronization When a recessive to dominant level change on the bus is detected, a soft synchronization is performed. • If the phase error is larger than the programmed SJW value, the node will adjust the timing by applying this SJW value.
Page 604: State Transition Chart
CHAPTER 19 CAN CONTROLLER 19.3.8 State transition chart Figure 19-20. Transmission State Transition Chart Reception Start of frame Bit error Arbitration field RTR = 1 Bit error Control field Reception RTR = 0 Bit error Data field Bit error CRC field ACK error ACK field Bit error...
Page 605 CHAPTER 19 CAN CONTROLLER Figure 19-21. Reception State Transition Chart Transmission Start of frame Transmission Stuff error Arbitration field RTR = 1 Stuff error Control field RTR = 0 Stuff error Data field CRC error, stuff error CRC field ACK error, bit error ACK field Bit error, form error End of frame...
Page 606 CHAPTER 19 CAN CONTROLLER Figure 19-22. Error State Transition Chart (a) Transmission Error active TEC > TEC < 127 Error passive TEC > Bus off TEC = 0 (b) Reception Error active REC > 128 Error passive REC < 127 Preliminary User’s Manual U16541EJ1V0UM...
Page 607: Connection With Target System
CHAPTER 19 CAN CONTROLLER 19.4 Connection with Target System The CAN module has to be connected to the CAN bus using an external transceiver. Figure 19-23. Connection to CAN Bus CTxD CANL CAN module Transceiver CRxD CANH Preliminary User’s Manual U16541EJ1V0UM...
Page 608: Internal Registers Of Can Controller
CHAPTER 19 CAN CONTROLLER 19.5 Internal Registers of CAN Controller 19.5.1 CAN controller configuration Table 19-17. List of CAN Controller Registers Item Configuration Control registers CAN0 module control register (C0GMCTRL) CAN0 module clock selection register (C0GMCS) CAN0 automatic block transmission register (C0GMABT) CAN0 automatic block transmission delay register (C0GMABTD) CAN0 module mask 1 registers (C0MASK1L, C0MASK1H) CAN0 module mask 2 registers (C0MASK2L, C0MASK2H)
Page 609: Register Access Type
CHAPTER 19 CAN CONTROLLER 19.5.2 Register access type Table 19-18. Control Register Access Types Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC000H CAN0 module control register C0GMCTRL 0000H √ FFFEC002H CAN0 module clock selection register C0GMCS √...
Page 610 CHAPTER 19 CAN CONTROLLER Table 19-19. Message Buffer Register Access Types (1/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC100H CAN0 message data byte 01 register 00 C0MDATA0100 Undefined √ FFFEC100H CAN0 message data byte 0 register 00 C0MDATA000 Undefined...
Page 611 CHAPTER 19 CAN CONTROLLER (2/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC140H CAN0 message data byte 01 register 02 C0MDATA0102 Undefined √ FFFEC140H CAN0 message data byte 0 register 02 C0MDATA002 Undefined √...
Page 612 CHAPTER 19 CAN CONTROLLER (3/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC180H CAN0 message data byte 01 register 04 C0MDATA0104 Undefined √ FFFEC180H CAN0 message data byte 0 register 04 C0MDATA004 Undefined √...
Page 613 CHAPTER 19 CAN CONTROLLER (4/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC1C0H CAN0 message data byte 01 register 06 C0MDATA0106 Undefined √ FFFEC1C0H CAN0 message data byte 0 register 06 C0MDATA006 Undefined √...
Page 614 CHAPTER 19 CAN CONTROLLER (5/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC200H CAN0 message data byte 01 register 08 C0MDATA0108 Undefined √ FFFEC200H CAN0 message data byte 0 register 08 C0MDATA008 Undefined √...
Page 615 CHAPTER 19 CAN CONTROLLER (6/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC240H CAN0 message data byte 01 register 10 C0MDATA0110 Undefined √ FFFEC240H CAN0 message data byte 0 register 10 C0MDATA010 Undefined √...
Page 616 CHAPTER 19 CAN CONTROLLER (7/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC280H CAN0 message data byte 01 register 12 C0MDATA0112 Undefined √ FFFEC280H CAN0 message data byte 0 register 12 C0MDATA012 Undefined √...
Page 617 CHAPTER 19 CAN CONTROLLER (8/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC2C0H CAN0 message data byte 01 register 14 C0MDATA0114 Undefined √ FFFEC2C0H CAN0 message data byte 0 register 14 C0MDATA014 Undefined √...
Page 618 CHAPTER 19 CAN CONTROLLER (9/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC300H CAN0 message data byte 01 register 16 C0MDATA0116 Undefined √ FFFEC300H CAN0 message data byte 0 register 16 C0MDATA016 Undefined √...
Page 619 CHAPTER 19 CAN CONTROLLER (10/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC340H CAN0 message data byte 01 register 18 C0MDATA0118 Undefined √ FFFEC340H CAN0 message data byte 0 register 18 C0MDATA018 Undefined √...
Page 620 CHAPTER 19 CAN CONTROLLER (11/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC380H CAN0 message data byte 01 register 20 C0MDATA0120 Undefined √ FFFEC380H CAN0 message data byte 0 register 20 C0MDATA020 Undefined √...
Page 621 CHAPTER 19 CAN CONTROLLER (12/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC3C0H CAN0 message data byte 01 register 22 C0MDATA0122 Undefined √ FFFEC3C0H CAN0 message data byte 0 register 22 C0MDATA022 Undefined √...
Page 622 CHAPTER 19 CAN CONTROLLER (13/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC400H CAN0 message data byte 01 register 24 C0MDATA0124 Undefined √ FFFEC400H CAN0 message data byte 0 register 24 C0MDATA024 Undefined √...
Page 623 CHAPTER 19 CAN CONTROLLER (14/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC440H CAN0 message data byte 01 register 26 C0MDATA0126 Undefined √ FFFEC440H CAN0 message data byte 0 register 26 C0MDATA026 Undefined √...
Page 624 CHAPTER 19 CAN CONTROLLER (15/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC480H CAN0 message data byte 01 register 28 C0MDATA0128 Undefined √ FFFEC480H CAN0 message data byte 0 register 28 C0MDATA028 Undefined √...
Page 625 CHAPTER 19 CAN CONTROLLER (16/16) Address Register Name Symbol Bit Manipulation Units After Reset 1 Bit 8 Bits 16 Bits √ FFFEC4C0H CAN0 message data byte 01 register 30 C0MDATA0130 Undefined √ FFFEC4C0H CAN0 message data byte 0 register 30 C0MDATA030 Undefined √...
Page 626: Control Bits Of Message Buffers
CHAPTER 19 CAN CONTROLLER 19.5.3 Control bits of message buffers Table 19-20. Control Bits of Control Registers (1/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 FFFEC000H C0GMCTRL(W) cGOM FFFEC001H sEFSD sGOM FFFEC000H...
Page 627 CHAPTER 19 CAN CONTROLLER Table 19-20. Control Bits of Control Registers (2/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 FFFEC054H C0ERC TEC[7:0] FFFEC055H REC[7:0] FFFEC056H C0IE (W) cCIE5 cCIE4 cCIE3 cCIE2 cCIE1...
Page 628 CHAPTER 19 CAN CONTROLLER Table 19-21. Control Bits of Message Buffers Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 FFFECxx0H C0MDATA01m Message data (byte 0) FFFECxx1H Message data (byte 1) FFFECxx0H C0MDATA0m Message data (byte 0)
Page 629: Control Registers
CHAPTER 19 CAN CONTROLLER 19.6 Control Registers (1) CAN0 module control register (C0GMCTRL) (1/2) (a) Read Address Initial value C0GMCTRL MBON FFFEC001H EFSD FFFEC000H (b) Write C0GMCTRL FFFEC001H EFSD Clear FFFEC000H (a) Read MBON Access Enable Bit for Message Buffers Write access and read access to the message buffers is impossible because CAN module is in CAN sleep and/or CAN stop mode.
Page 630 CHAPTER 19 CAN CONTROLLER (2/2) (b) Write Set EFSD EFSD Bit Setting No change in EFSD bit’s value EFSD bit set (1) Caution When the EFSD bit is set (1), the subsequent CPU access to the CAN module has to clear the GOM bit (0). If the GOM bit is not cleared (0) in the subsequent access, the EFSD bit is cleared (0) automatically (forced shutdown request is invalid).
Page 631 CHAPTER 19 CAN CONTROLLER (2) CAN0 module clock selection register (C0GMCS) Address Initial value C0GMCS MBON CCP3 CCP2 CCP1 CCP0 FFFEC002H (Read/Write) CCP3 CCP2 CCP1 CCP1 CAN Module System Clock (f CANMOD Remark f = Clock supply to CAN Preliminary User’s Manual U16541EJ1V0UM...
Page 632 CHAPTER 19 CAN CONTROLLER (3) CAN0 automatic block transmission register (C0GMABT) (1/2) (a) Read Address Initial value C0GMABT FFFEC007H ABTCLR ABTTRG FFFEC006H (b) Write C0GMABT FFFEC007H ABTCLR ABTTRG Clear FFFEC006H ABTTRG Caution Before switching from “normal operating mode with automatic block transmission” to the INIT mode, be sure to clear the bits in the C0GMABT register to their initial values.
Page 633 CHAPTER 19 CAN CONTROLLER (2/2) (b) Write Set ABTCLR ABTCLR Bit Setting No change in ABTCLR bit’s value ABTCLR bit set (1) Remarks 1. The ABTCLR bit must not be set (1) when the ABTTRG bit is set (1). 2. The ABTCLR bit is automatically cleared (0) by the internal ABT engine, when a clear request has been accepted by setting the AVTCLR bit (1).
Page 634 CHAPTER 19 CAN CONTROLLER (4) CAN0 automatic block transmission delay register (C0GMABTD) Address Initial value C0GMABT ABTD3 ABTD2 ABTD1 ABTD0 FFFEC008H (Read/Write) Data Frame Interval During Automatic Block Transmission ABTD3 ABTD2 ABTD1 ABTD0 (Unit = Bit Time; DBT) 0 DBT Other than above Setting prohibited Caution...
Page 635 CHAPTER 19 CAN CONTROLLER (5) CAN0 module mask register (C0MASKaL, C0MASKaH) (a = 1, 2, 3, 4) Figure 19-24. CAN0 Module Mask 1 Registers (C0MASK1L, C0MASK1H) Address Initial value C0MASK1L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 FFFEC041H Undefined (Read/Write) CMID7 CMID6...
Page 636 CHAPTER 19 CAN CONTROLLER Figure 19-27. CAN0 Module Mask 4 Registers (C0MASK4L, C0MASK4H) Address Initial value C0MASK4L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 FFFEC04DH Undefined (Read/Write) CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 FFFEC04CH Undefined C0MASK4H CMID28 CMID27 CMID26 CMID25 CMID24 FFFEC04FH Undefined (Read/Write) CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 FFFEC04EH...
Page 637 CHAPTER 19 CAN CONTROLLER (6) CAN0 module control register (C0CTRL) (1/4) (a) Read Address Initial value C0CTRL RSTAT TSTAT FFFEC051H CCERC VALID PSMODE PSMODE OPMODE OPMODE OPMODE FFFEC050H (b) Write C0CTRL FFFEC051H CCERC PSMODE PSMODE OPMODE OPMODE OPMODE Clear Clear Clear Clear Clear...
Page 638 CHAPTER 19 CAN CONTROLLER (2/4) TSTAT CAN Transmission Status Bit No transmission activity on the CAN bus Transmission activity on the CAN bus Remark The TSTAT bit is set (1) under the following conditions. • The SOF bit of a transmission frame is detected •...
Page 639 CHAPTER 19 CAN CONTROLLER (3/4) Power Save Mode PSMODE1 PSMODE0 No power save mode selected (CAN module is in INIT mode or in one of the operational modes) CAN sleep mode Setting prohibited CAN stop mode Operation Mode OPMODE2 OPMODE1 OPMODE0 No operational mode selected (CAN module is in INIT mode) Normal operating mode Normal operating mode with automatic block transmission...
Page 640 CHAPTER 19 CAN CONTROLLER (4/4) Set PSMODE2 Clear PSMODE2 PSMODE2 Bit Setting PSMODE2 bit cleared (0) PSMODE2 bit set (1) Other than above No change in PSMODE2 bit’s value Set OPMODE0 Clear OPMODE0 OPMODE0 Bit Setting OPMODE0 bit cleared (0) OPMODE0 bit set (1) Other than above No change in OPMODE0 bit’s value...
Page 641 CHAPTER 19 CAN CONTROLLER (7) CAN0 module last error code register (C0LEC) Address Initial value C0LEC LEC2 LEC1 LEC0 FFFEC052H (Read/Write) Remarks 1. Switching the CAN module from an operational mode to the INIT mode does not clear the actual content of C0LEC.
Page 642 CHAPTER 19 CAN CONTROLLER (8) CAN0 module information register (C0INFO) Address Initial value C0INFO BOFF TECS1 TECS0 RECS1 RECS0 FFFEC053H (Read Only) BOFF Bus-off Status Bit CAN is not in the bus-off state (transmission error counter < 255) CAN is in the bus-off state (transmission error counter ≥ 255) TECS1 TECS0 Transmit Error Counter Status Bit...
Page 643 CHAPTER 19 CAN CONTROLLER (10) CAN0 module interrupt enable register (C0IE) (1/2) (a) Read Address Initial value C0IE FFFEC057H CIE5 CIE4 CIE3 CIE2 CIE1 CIE0 FFFEC056H (b) Write C0IE FFFEC057H CIE5 CIE4 CIE3 CIE2 CIE1 CIE0 Clear Clear Clear Clear Clear Clear FFFEC056H...
Page 644 CHAPTER 19 CAN CONTROLLER (2/2) (b) Write Set CIE5 Clear CIE5 CIE5 Bit Setting CIE5 bit cleared (0) CIE5 bit set (1) Other than above No change in CIE5 bit’s value Set CIE4 Clear CIE4 CIE4 Bit Setting CIE4 bit cleared (0) CIE4 bit set (1) Other than above No change in CIE4 bit’s value...
Page 645 CHAPTER 19 CAN CONTROLLER (11) CAN0 module interrupt status register (C0INTS) (1/2) (a) Read Address Initial value C0INTS FFFEC059H CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 FFFEC058H (b) Write C0INTS FFFEC059H Clear Clear Clear Clear Clear Clear FFFEC058H CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0...
Page 646 CHAPTER 19 CAN CONTROLLER (2/2) (b) Write Clear CINT5 CINT5 Bit Setting CINT5 bit not changed CINT5 bit cleared (0) Clear CINT4 CINT4 Bit Setting CINT4 bit not changed CINT4 bit cleared (0) Clear CINT3 CINT3 Bit Setting CINT3 bit not changed CINT3 bit cleared (0) Clear CINT2 CINT2 Bit Setting...
Page 647 CHAPTER 19 CAN CONTROLLER (12) CAN0 module bit-rate prescaler register (C0BRP) Address Initial value C0BRP TQPRS7 TQPRS6 TQPRS5 TQPRS4 TQPRS3 TQPRS2 TQPRS1 TQPRS0 FFFEC05AH (Read/Write) TQPRS7 to CAN Protocol Layer Basic System Clock (f TQPRS0 CANMOD CANMOD /(n+1) CANMOD ..
Page 648 CHAPTER 19 CAN CONTROLLER (13) CAN0 module bit rate register (C0BTR) (1/2) Address Initial value C0BTR SJW1 SJW0 TSEG22 TSEG21 TSEG20 FFFEC05DH (Read/Write) TSEG13 TSEG12 TSEG11 TSEG10 FFFEC05CH Figure 19-29. Data Bit Time Data bit time (DBT) Sync segment Prop segment Phase segment 1 Phase segment 2 Time segment 1 (TSEG1)
Page 649 CHAPTER 19 CAN CONTROLLER (2/2) SJW1 SJW0 Length of Synchronization Jump Width 1 TQ 2 TQ 3 TQ 4 TQ TSEG22 TSEG21 TSEG20 Length of Time Segment 2 1 TQ 2 TQ 3 TQ 4 TQ 5 TQ 6 TQ 7 TQ 8 TQ TSEG13 TSEG12 TSEG11 TSEG10...
Page 650 CHAPTER 19 CAN CONTROLLER (14) CAN0 module last in-pointer register (C0LIPT) Address Initial value C0LIPT LIPT7 LIPT6 LIPT5 LIPT4 LIPT3 LIPT2 LIPT1 LIPT0 FFFEC05EH Undefined (Read-only) LIPT7 to LIPT0 Last In-Pointer of Receive History List Note 0..m Reading the C0LIPT register delivers the message buffer number in which the last data frame was max.
Page 651 CHAPTER 19 CAN CONTROLLER (15) CAN0 module receive history list register (C0RGPT) (1/2) (a) Read Address Initial value C0RGPT RGPT7 RGPT6 RGPT5 RGPT4 RGPT3 RGPT2 RGPT1 RGPT0 FFFEC06H1H Undefined RHPM ROVF FFFEC06H0H xxxxxx10B (b) Write C0RGPT FFFEC06H1H Clear FFFEC06H0H ROVF (a) Read RGPT7 to RGPT0 Receive History List Pointer Match...
Page 652 CHAPTER 19 CAN CONTROLLER (16) CAN0 module last out-pointer register (C0LOPT) Address Initial value C0LOPT LOPT7 LOPT6 LOPT5 LOPT4 LOPT3 LOPT2 LOPT1 LOPT0 FFFEC062H Undefined (Read-only) LOPT7 to LOPT0 Last Out-Pointer of Transmit History List Note 0..m Reading the C0LOPT register delivers the message buffer number from which the last message max.
Page 653 CHAPTER 19 CAN CONTROLLER (17) CAN0 module transmit history list register (C0TGPT) (a) Read Address Initial value C0TGPT TGPT7 TGPT6 TGPT5 TGPT4 TGPT3 TGPT2 TGPT1 TGPT0 FFFEC065H Undefined THPM TOVF FFFEC064H xxxxxx10B (b) Write C0TGPT FFFEC065H Clear FFFEC064H TOVF (a) Read TGPT7 to TGPT0 Transmit History List Pointer Match Note 1...
Page 654 CHAPTER 19 CAN CONTROLLER (18) CAN0 module time stamp register (C0TS) (1/2) (a) Read Address Initial value C0TS FFFEC067H TSLOCK TSSEL TSEN FFFEC066H (b) Write C0TS FFFEC067H TSLOCK TSSEL TSEN Clear Clear Clear FFFEC066H TSLOCK TSSEL TSEN Remark The basic time stamp function cannot be used when the CAN module operates in ‘normal operating mode with automatic block transmission’...
Page 655 CHAPTER 19 CAN CONTROLLER (2/2) (b) Write Set TSLOCK Clear TSLOCK TSLOCK Bit Setting TSLOCK bit cleared (0) TSLOCK bit set (1) Other than above No change in TSLOCK bit’s value Set TSSEL Clear TSSEL TSSEL Bit Setting TSSEL bit cleared (0) TSSEL bit set (1) Other than above No change in TSSEL bit’s value...
Page 656 CHAPTER 19 CAN CONTROLLER (19) CAN0 message data byte register (C0MDATA x m) (x = 0 to 7, m = 0 to 31) Address Initial value C0MDATA01m MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 FFFECxx0H Undefined FFFECxx1H Address Initial value C0MDATA0m MDATA0 FFFECxx0H Undefined...
Page 657 CHAPTER 19 CAN CONTROLLER (20) CAN0 message data length code register m (C0MDLCm) Address Initial value C0MDLCm MDLC3 MDLC2 MDLC1 MDLC0 FFFECxx8H 0000xxxxB MDLC3 MDLC2 MDLC1 MDLC0 Message Data Length Code 0 bytes 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes...
Page 658 CHAPTER 19 CAN CONTROLLER (21) CAN0 message configuration register (C0MCONFm) Address Initial value C0MCONFm FFFECxx9H xxxxxxxxB Overwrite Select Bit Note A newly received data frame does not overwrite the occupied message buffer . The newly received data frame is discarded. A newly received data frame overwrites an occupied message buffer Note An occupied message buffer means a receive message buffer into which a data frame has already been accepted (i.e.
Page 659 CHAPTER 19 CAN CONTROLLER (22) CAN0 message identifier registers (C0MIDLm, C0MIDHm) (m = 0 to 31) Address Initial value C0MIDLm ID15 ID14 ID13 ID12 ID11 ID10 FFFECxxBH Undefined (Read/Write) FFFECxxAH C0GMCTRL ID28 ID27 ID26 ID25 ID24 FFFECxxDH x00xxxxx xxxxxxxxB (Read/Write) ID23 ID22 ID21...
Page 660 CHAPTER 19 CAN CONTROLLER (23) CAN0 message control register m (C0MCTRLm) (1/3) (a) Read Address Initial value C0MCTRLm FFFECxxFH 00x00000H 000xx000B FFFECxxEH (b) Write C0MCTRLm FFFECxxFH Clear Clear Clear Clear Clear FFFECxxEH (a) Read Message Buffer Under Change Flag The assigned CAN module is not writing to the message buffer. The assigned CAN module is writing to the message buffer.
Page 661 CHAPTER 19 CAN CONTROLLER (2/3) Interrupt Enable for Message Buffer Interrupt Event Interrupt generation is disabled for the following events: • Interrupt events linked to the CINTS0 interrupt status bit in the C0INTS register (i.e. when MT2 to MT0 = 0, ‘Data frame successfully transmitted from message buffer m’, ‘Remote frame successfully transmitted from message buffer m’) •...
Page 662 CHAPTER 19 CAN CONTROLLER (3/3) (b) Write Clear MOW MOW Bit Setting MOW bit not changed MOW bit cleared (0) Set IE Clear IE IE Bit Setting IE bit cleared (0) IE bit set (1) Other than above No change in IE bit’s value Set DN Clear DN DN Bit Setting...
Page 663: Bit Set/Clear Function
CHAPTER 19 CAN CONTROLLER 19.7 Bit Set/Clear Function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values.
Page 664 CHAPTER 19 CAN CONTROLLER Figure 19-31. 16-Bit Data During Write Operation set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n Status of bit n after bit set/clear operation...
Page 665: Can Controller Initialization
CHAPTER 19 CAN CONTROLLER 19.8 CAN Controller Initialization 19.8.1 Initialization of CAN module Before the CAN module operation is enabled, the CAN module system clock needs to be set in CCP[3:0] of the C0GMCS register by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled.
Page 666: Transition From Init Mode In Operational Mode
CHAPTER 19 CAN CONTROLLER 19.8.3 Transition from INIT mode to operational mode The CAN module in each CAN I/F channel can be switched to the following operational modes. “Normal operating mode” “Normal operating mode with automatic block transmission” “Receive-only mode” “Single-shot mode”...
Page 667: Resetting Of Can Module Error Counter C0Erc In Init Mode
CHAPTER 19 CAN CONTROLLER 19.8.4 Resetting of CAN module error counter C0ERC in INIT mode For evaluation purposes, it is necessary to reset the CAN module error counter C0ERC and the CAN module information register C0INFO. Therefore it is possible to set the CCERC bit in the C0CTRL register (1) in INIT mode of the CAN module.
Page 668: Message Reception
CHAPTER 19 CAN CONTROLLER 19.9 Message Reception 19.9.1 Message reception In all the operational modes of the CAN module, when a data frame is received, whether the received data frame has to be stored in one of the message buffers that satisfy the following conditions is checked. •...
Page 669 CHAPTER 19 CAN CONTROLLER newly stored message. Therefore, after the ROVF bit is set (1), a recorded message buffer number in the RHL does not completely reflect the chronological order. Figure 19-33. Receive History List Receive history list (RHL) Receive history list (RHL) Message buffer #6 get (read) MSG # 8...
Page 670 CHAPTER 19 CAN CONTROLLER Figure 19-34. Message Reception Procedure Using Receive History List SW read data request RHPM bit cleared (0) CINTS1 bit set (1) ROVF bit set (1) Clear ROVF bit (0) SW read access to RGPT pointer SW clears DN bit (0) of particular message buffer SW read access to message buffer...
Page 671 CHAPTER 19 CAN CONTROLLER Figure 19-35. C0RGPT Pointer Handling with Respect to RHPM Bit Start RHPM = 1 Read access to the RGPT pointer Preliminary User’s Manual U16541EJ1V0UM...
Page 672: Mask Function
CHAPTER 19 CAN CONTROLLER 19.9.3 Mask function A mask function can be linked to each receive message buffer. This means that there is no need to distinguish between local masks and global masks. When the mask function is used, the identifier of a received message is compared with the identifier of the particular message buffer.
Page 673: Multi Buffer Receive Block Function
CHAPTER 19 CAN CONTROLLER <3> Mask setting for CAN module 1 (mask 1) (example) (Using CAN1 address mask 1 registers L and H (C1MASKL1 and C1MASKH1)) CMID28 CMID27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 CMID15 CMID14 CMID13 CMID12...
Page 674 CHAPTER 19 CAN CONTROLLER • When it has been enabled by setting the CIE1 enable bit in the C0IE register (1), the interrupt request signal INTC0TREC is generated. • The reception history list is updated with the message buffer number for which the received remote frame has been accepted •...
Page 675: Message Transmission
CHAPTER 19 CAN CONTROLLER 19.10 Message Transmission 19.10.1 Message transmission In the operational modes “normal operating mode”, “normal operating mode with ABT” and “single-shot mode” and “self-test mode” of the CAN module, the transmit message search machine is triggered when the TRQ bit is set to 1 in a message buffer that satisfies the following conditions.
Page 676 CHAPTER 19 CAN CONTROLLER Priority Conditions Description 1 (highest) 11 MSB identifier value rule The first 11 bits of the identifier (i.e. ID28 to ID18) are the first criteria [ID28 to ID18] used to judge which message frame has to be sent first. As a result, message frames with the lowest value represented by the 11 most significant bits of the identifier have to be sent first.
Page 677: Transmit History List Function
CHAPTER 19 CAN CONTROLLER 19.10.2 Transmit history list function The transmit history list (THL) function records the number of the message buffer for each transmitted message (data frame or remote frame). The THL consists of 7 elements and two pointers, the last out-message pointer (LOPT pointer) with the corresponding C0LOPT register and the transmit history list get pointer (TGPT pointer) with the corresponding C0TGPT register.
Page 678 CHAPTER 19 CAN CONTROLLER Figure 19-38. Message Transmission Procedure Using Transmit History List Start New message successfully transmitted: increment LOPT pointer LOPT = 1 TGPT-1 TOVF = 1 Preliminary User’s Manual U16541EJ1V0UM...
Page 679 CHAPTER 19 CAN CONTROLLER Figure 19-39. C0TGPT Pointer Handling with Respect to THPM Bit Start THPM = 1 Read access to the TGPT pointer Preliminary User’s Manual U16541EJ1V0UM...
Page 680: Automatic Block Transmission (Abt)
CHAPTER 19 CAN CONTROLLER 19.10.3 Automatic block transmission (ABT) The automatic block transmission (ABT) function can transfer data frames successively with no CPU interaction. The maximum number of transmit message buffers assigned to the ABT function is 8 (message buffer numbers 0 to 7).
Page 681 CHAPTER 19 CAN CONTROLLER In the case of an erroneous transmission, the position of the internal ABT pointer depends on the status of the TRQ bit of the last transmitted message buffer. • If the TRQ bit was cleared (0) in addition to the clear of ABTTRG (0), the internal ABT pointer points to the next message buffer.
Page 682: Power Saving Modes
CHAPTER 19 CAN CONTROLLER 19.11 Power Saving Modes 19.11.1 CAN sleep mode The CAN sleep mode can be used to set the CAN controller to standby mode in order to reduce power consumption. The CAN sleep mode can be entered from all operational modes of the CAN module. A release of the CAN sleep mode returns the CAN module to exactly the same operational mode from which the CAN sleep mode was entered.
Page 683 CHAPTER 19 CAN CONTROLLER (1) Entering CAN stop mode The CPU issues a CAN stop mode transition request by writing 10B to the PSMODE1, PSMODE0 bit string in the C0CTRL register. The CAN stop mode transition request is only accepted when the CAN module is in CAN sleep mode.
Page 684: Interrupt Function
CHAPTER 19 CAN CONTROLLER 19.12 Interrupt Function 19.12.1 Interrupts generated by CAN module Each CAN module of a CAN I/F channel provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals are generated from the six sources.
Page 685: Diagnosis Functions And Special Operational Modes
CHAPTER 19 CAN CONTROLLER 19.13 Diagnosis Functions and Special Operational Modes The CAN module provides the receive-only mode, single-shot mode, and self-test mode to support CAN bus diagnosis or the operation of specific CAN communication methods. 19.13.1 Receive-only mode The “receive-only mode” can be used for CAN bus analysis nodes, which have to receive all messages without causing any interference on the CAN bus.
Page 686: Single-Shot Mode
CHAPTER 19 CAN CONTROLLER A CAN module in the “receive-only mode” is also not able to generate a dominant bit on the CAN bus in the ACK slot of the ACK field upon a valid reception of a message frame. Furthermore, in “receive-only mode”, no overload frames can be generated.
Page 687: Self-Test Mode
CHAPTER 19 CAN CONTROLLER 19.13.3 Self-test mode In the “self-test mode”, message frame transmission and message frame reception can be tested without connecting the CAN node to the CAN bus or without affecting the CAN bus. In the operational mode “self-test mode”, the CAN module of a CAN I/F channel is completely disconnected from the CAN bus, but internal switches connect the transmit path with the receive path.
Page 688: Time Stamp Function
CHAPTER 19 CAN CONTROLLER 19.14 Time Stamp Function CAN is an asynchronous, serial protocol. All nodes connected to the bus have a local, autonomous clock. As a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may even have different frequencies).
Page 689: Rules For Setting Baud Rate
CHAPTER 19 CAN CONTROLLER 19.15 Rules for Setting Baud Rate Always make sure that the settings are within the range of limit values for ensuring correct operation of the CAN controller as follows. (a) 5 TQ ≤ SPT (sampling point) ≤ 17 TQ SPT = TSEG1 + 1 (b) 8 TQ ≤...
Page 690 CHAPTER 19 CAN CONTROLLER Given the above limit values, the following two settings are possible. Prescaler SPT(MAX.) TSEG1 TSEG2 Calculated SPT 13/16 = 81% 5/8 = 62.5% = 1 × 16 8 MHz/500 kHz = 16 <1> = 2 × 8 <2>...
Page 691 CHAPTER 19 CAN CONTROLLER (ii) TSEG1 setting TSEG1 is calculated as shown below. • TSEG1 = (a + 1)TQ : [1 ≤ a ≤ 15] Value a is set using bits 3 to 0 (TSEG1[3:0]) of the C0BTR register. TSEG1 = 12TQ = (a + 1)TQ thus a = 11 Therefore, the C0BTR register’s bits 3 to 0 = 1011B...
Page 692 CHAPTER 19 CAN CONTROLLER Figure 19-43. C0BTR Register Settings C0BTR TSEG13 TSEG12 TSEG11 TSEG10 Setting SJW1 SJW0 TSEG22 TSEG21 TSEG20 Setting Preliminary User’s Manual U16541EJ1V0UM...
Page 693: Operation Of Can Controller
CHAPTER 19 CAN CONTROLLER 19.16 Operation of CAN Controller Figure 19-44. Initialization START CGMCS register Set GOM = 1 C0BRP register C0BTR register C0IE register C0MASK register Initialize message buffers OPMODE Remark OPMODE: Normal operating mode, normal operating mode with ABT, receive-only mode, single-shot mode, self-test mode.
Page 694 CHAPTER 19 CAN CONTROLLER Figure 19-45. Reinitialization START Clear OPMODE INIT mode Redefine C0BRP register message buffers C0BTR register C0ERC and C0INFO C0IE register clear? C0MASK register CCERC OPMODE Caution Before a message buffer is initialized, the RDY bit must be cleared. Remark OPMODE: Normal operating mode, normal operating mode with ABT, receive-only mode, single-shot mode, self-test mode.
Page 695 CHAPTER 19 CAN CONTROLLER Figure 19-46. Message Buffer Initialization START C0MCONFm C0MIDHm, C0MIDLm Transmit message buffer? C0MDLCm Clear C0MDATAm C0MCTRLm Preliminary User’s Manual U16541EJ1V0UM...
Page 696 CHAPTER 19 CAN CONTROLLER Figure 19-47. Message Buffer Redefinition START RDY = 1? Clear RDY = 1 RDY = 0? message buffers Set RDY = 1 Preliminary User’s Manual U16541EJ1V0UM...
Page 697 CHAPTER 19 CAN CONTROLLER Figure 19-48. Transmit Preparation (Normal Mode) START TRQ = 0? Clear RDY = 1 Write data Set RDY = 1 Set TRQ = 1 Caution The TRQ bit should be set after the RDY bit is set. The TRQ bit and RDY bit should not be set at the same time.
Page 698 CHAPTER 19 CAN CONTROLLER Figure 19-49. Transmit Preparation (ABT Mode) START Clear RDY = 1 Write data Set RDY = 1 Set ABTTRG = 1 Preliminary User’s Manual U16541EJ1V0UM...
Page 699 CHAPTER 19 CAN CONTROLLER Figure 19-50. Transmission via Interrupt (C0LOPT) START Transmit interrupt Read C0LOPT Clear RDY = 1 Write data Set RDY = 1 Set TRQ = 1 Clear CINTS0 = 1 Caution The TRQ bit should be set after the RDY bit is set. The TRQ bit and RDY bit should not be set at the same time.
Page 700 CHAPTER 19 CAN CONTROLLER Figure 19-51. Transmission via Interrupt (C0TGPT) START Transmit interrupt Read C0TGPT TOVF = 1? Set RDY = 1 Clear TOVF = 1 Set TRQ = 1 Read C0TGPT THPM = 1? Clear RDY = 1 Clear CINTS0 = 1 Write data Caution The TRQ bit should be set after the RDY bit is set.
Page 701 CHAPTER 19 CAN CONTROLLER Figure 19-52. Transmit Software Polling START CINTS0 = 1? Read C0TGPT TOVF = 1? Set RDY = 1 Clear TOVF = 1 Set TRQ = 1 Read C0TGPT THPM = 1? Clear RDY = 1 Clear CINTS0 = 1 Write data Caution The TRQ bit should be set after the RDY bit is set.
Page 702 CHAPTER 19 CAN CONTROLLER Figure 19-53. Transmission Request Abort Process (Normal Mode) START Clear TRQ = 1 Note Check C0TGPT C0TGPT points to aborted message buffer? Transmit abort request was successful Transmission successful Note The user must decide when to check. Preliminary User’s Manual U16541EJ1V0UM...
Page 703 CHAPTER 19 CAN CONTROLLER Figure 19-54. Transmission Request Abort Process (ABT Mode) START Clear ABTTRG = 1 ABTTRG = 0? Transmission abort Start point clear? Set ABTCLR = 1 Preliminary User’s Manual U16541EJ1V0UM...
Page 704 CHAPTER 19 CAN CONTROLLER Figure 19-55. Reception via Interrupt (C0LIPT) START Receive interrupt Read C0LIPT Clear DN = 1 Read data DN = 0 Note MUC = 0 Clear CINTS1 = 1 Note Check the MUC bit and DN bit using one read access. Preliminary User’s Manual U16541EJ1V0UM...
Page 705 CHAPTER 19 CAN CONTROLLER Figure 19-56. Reception via Interrupt (C0RGPT) START Receive interrupt Read C0RGPT ROVF = 1? Clear ROVF = 1 DN = 0 Read C0RGPT Note MUC = 0 Clear DN = 1 RHPM = 1? Read data Clear CINTS1 = 1 Note Check the MUC bit and DN bit using one read access.
Page 706 CHAPTER 19 CAN CONTROLLER Figure 19-57. Receive Software Polling START CINTS1 = 1? Read C0RGPT ROVF = 1? Clear ROVF = 1 DN = 0 Read C0RGPT Note MUC = 0 Clear DN = 1 RHPM = 1? Read data Clear CINTS1 = 1 Note Check the MUC bit and DN bit using one read access.
Page 707 CHAPTER 19 CAN CONTROLLER Figure 19-58. Setting CAN Sleep/Stop Mode START PSMODE0 = 1 PSMODE0 = 1? Sleep mode PSMODE1 = 1 PSMODE1 = 1? Stop mode Caution When accessing a message buffer after requesting shift to sleep mode, confirm that the MBON bit is set.
Page 708 CHAPTER 19 CAN CONTROLLER Figure 19-59. Clear CAN Sleep/Stop Mode START STOP mode Clear PSMODE1 = 1 Sleep mode Bus active PSMODE0 = 0 Clear PSMODE0 = 1 Clear CINTS5 = 1 Preliminary User’s Manual U16541EJ1V0UM...
Page 709 CHAPTER 19 CAN CONTROLLER Figure 19-60. Bus-Off Recovery START BOFF = 1? Clear OPMODE DN = 0 INIT mode? MUC = 0 Bus off clear? Set CCERC = 1 OPMODE Matched OPMODE clear bus-off condition Preliminary User’s Manual U16541EJ1V0UM...
Page 710 CHAPTER 19 CAN CONTROLLER Figure 19-61. Shutdown Process (Normal Shutdown) START All CAN modules in INIT mode Clear GOM = 0 Shutdown successful GOM = 0, EFSD = 0 Remark If the GOM bit is set after shutdown, the message buffer must be reinitialized before it is shifted to any operation mode.
Page 711 CHAPTER 19 CAN CONTROLLER Figure 19-62. Shutdown Process (Forcible Shutdown) START CAN module is OPMODE Set EFSD = 1 Must be a continuous write Clear GOM = 0 GOM = 0? Shutdown successful GOM = 0, EFSD = 0 Cautions 1. Do not read- or write-access any register between setting the EFSD bit and clearing the GOM bit.
Page 712 CHAPTER 19 CAN CONTROLLER Figure 19-63. Error Handling START Error interrupt CINTS2 = 1? Check error state Clear CINTS2 = 1 CINTS3 = 1? CINTS4 = 1? Check protocol error state Next operation Clear CINTS3 = 1 Clear CINTS4 = 1 Preliminary User’s Manual U16541EJ1V0UM...
Page 713 CHAPTER 19 CAN CONTROLLER Figure 19-64. Setting CPU Standby (from CAN Sleep Mode) START PSMODE0 = 1 DN = 0 PSMODE0 = 1? MUC = 0 Clear CINTS5 Sleep mode entered CINTS5 = 1? DN = 0 MBON = 0? MUC = 0 CPU standby mode Preliminary User’s Manual U16541EJ1V0UM...
Page 714 CHAPTER 19 CAN CONTROLLER Figure 19-65. Setting CPU Standby (from CAN Stop Mode) START PSMODE0 = 1 PSMODE0 = 1? Clear CINTS5 Sleep mode entered PSMODE1 = 1 PSMODE1 = 1? Stop mode entered MBON = 0? CPU standby mode Preliminary User’s Manual U16541EJ1V0UM...
Page 715: Chapter 20 Dma Functions (Dma Controller)
CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) The V850ES/SG2 include a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and I/O, between memories, or between I/Os based on DMA requests issued by the on-chip peripheral I/O (serial interface, real-time pulse unit, and A/D converter), interrupts from external input pins, or software triggers (memory refers to internal RAM or external memory).
Page 716: Configuration
CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) 20.2 Configuration On-chip Internal RAM peripheral I/O Internal bus On-chip peripheral I/O bus DMA source address Data Address register n (DSAnH/DSAnL) control control DMA destination address register n (DDAnH/DDAnL) DMA transfer count Count register n (DBCn) control DMA channel control register n (DCHCn)
Page 717: Control Registers
CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) 20.3 Control Registers 20.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) The DSA0 to DSA3 registers set the DMA source addresses (28 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DSAnH and DSAnL.
Page 718: Dma Destination Address Registers 0 To 3 (Dda0 To Dda3)
CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) 20.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) The DDA0 to DDA3 registers set the DMA destination address (28 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DDAnH and DDAnL. (1) DMA destination address registers 0H to 3H (DDA0H to DDA3H) The DDA0H to DDA3H registers can be read or written in 16-bit units.
Page 719: Dma Byte Count Registers 0 To 3 (Dbc0 To Dbc3)
CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) 20.3.3 DMA byte count registers 0 to 3 (DBC0 to DBC3) The DBC0 to DBC3 registers are 16-bit registers that set the byte transfer count for DMA channels n (n = 0 to 3). These registers store the remaining transfer count during DMA transfer.
Page 720: Dma Addressing Control Registers 0 To 3 (Dadc0 To Dadc3)
CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) 20.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n = 0 to 3). These registers cannot be accessed during DMA operation. These registers can be read or written in 16-bit units.
Page 721: Dma Channel Control Registers 0 To 3 (Dchc0 To Dchc3)
CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) 20.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) The DCHC0 to DCHC3 registers are 8-bit registers that control the DMA transfer operating mode for DMA channel n (n = 0 to 3). These registers can be read or written in 8-bit or 1-bit units.
Page 722: Dma Trigger Factor Registers 0 To 3 (Dtfr0 To Dtfr3)
CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) 20.3.6 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger through interrupt request signals from on-chip peripheral I/O. The interrupt request signals set with these registers serve as DMA transfer start factors.
Page 723 CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) Table 20-1. DMA Start Factor (1/2) IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source DMA request by interrupt disabled INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 INTTQ0OV INTTQ0CC0 INTTQ0CC1 INTTQ0CC2 INTTQ0CC3 INTTP0OV INTTP0CC0 INTTP0CC1 INTTP1OV INTTP1CC0...
Page 724 CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) Table 20-1. DMA Start Factor (2/2) IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source INTUA2T INTAD INTKR Note INTERR Note INTSTA Note INTIE1 Other than above Setting prohibited Note IEBus controller version only Remark n = 0 to 3 Preliminary User’s Manual U16541EJ1V0UM...
Page 725: Dma Bus States
CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) 20.4 DMA Bus States 20.4.1 Types of bus states The DMAC bus states consist of the following 10 states. (1) TI state The TI state is an idle state, during which no access request is issued. The DMA request signals are sampled at the rising edge of the CLKOUT signal.
Page 726: Dmac Bus Cycle State Transition
CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) 20.4.2 DMAC bus cycle state transition Each time the processing for a DMA transfer is completed, the bus mastership is released. Figure 20-1. DMAC Bus Cycle State Transition T1RI T2RI T1WI Preliminary User’s Manual U16541EJ1V0UM...
Page 727: Transfer Mode
CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) 20.5 Transfer Mode 20.5.1 Single transfer mode In single transfer mode, the DMAC releases the bus at each byte/halfword transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
Page 728: Transfer Object
CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) 20.7 Transfer Object 20.7.1 Transfer object Table 20-2 shows the relationship with transfer object (√: Transfer enabled, ×: Transfer disabled). Table 20-2. Relationship with Transfer Object Destination Internal ROM On-Chip Internal RAM External Memory Peripheral I/O ×...
Page 729: Dma Channel Priorities
CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) 20.8 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3 These priorities are valid in the TI state only. In the block transfer mode, the channel used for transfer is never switched.
Page 730: Precautions
CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) 20.11 Precautions (1) Memory boundary The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA objects (external memory, internal RAM, or on-chip peripheral I/O) during DMA transfer. (2) Transfer of misaligned data DMA transfer of 16-bit bus width misaligned data is not supported.
Page 731: Interrupt Factors
CHAPTER 20 DMA FUNCTIONS (DMA CONTROLLER) (b) Repeatedly setting INITn bit until DMA transfer is forcibly stopped [Procedure] <1> Clear the Enn bit of the DCHCn register of the channel to be forcibly stopped to 0. <2> Clear the Enn bit of the above channel to 0 again. If data is transferred from or to the internal RAM to or from the channel to be forcibly stopped, execute step <2>...
Page 732: Chapter 21 Crc Function
CHAPTER 21 CRC FUNCTION 21.1 Functions • CRC operation circuit for the detection of data block errors • Generation of 16-bit CRC code using a CRC-CCITT (X + 1) generating function for blocks of data of any length in 8-bit units •...
Page 733: Control Registers
CHAPTER 21 CRC FUNCTION 21.3 Control Registers (1) CRC input register (CRCIN) The CRCIN register is an 8-bit register for data setting. This register can be read or written in 8-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF310H CRCIN (2) CRC data register (CRCD)
Page 734: Operation
CHAPTER 21 CRC FUNCTION 21.4 Operation 21.4.1 CRC operation circuit operation example Figure 21-2. CRC Operation Circuit Operation Example (LSB First) (1) Setting of CRCIN = (01) 1st machine cycle (2) CRCD register read (1189) 2nd machine cycle CRC code is saved The code when (01) is send LSB first is (1000 0000).
Page 735: Operation Circuit Configuration
CHAPTER 21 CRC FUNCTION 21.4.2 Operation circuit configuration The CRC operation principle is division, but CRC code can be generated by hardware using a shift register and exclusive OR (EX-OR). Figure 21-3. Operation Circuit Configuration (CRC Data Register) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Shift register...
Page 736: Usage Method
CHAPTER 21 CRC FUNCTION 21.4.3 Usage method The usage method of the CRC operation circuit is described below. Figure 21-4. CRC Operation Flow Start Write of 0000H to CRCD register CRCIN register write Input data exists? CRCD register read [Basic usage method] <1>...
Page 737 CHAPTER 21 CRC FUNCTION Communication errors can easily be detected if the CRC code is transmitted/received along with transmit/receive data when transmitting/receiving data consisting of several bytes. The following is an illustration using the transmission of 12345678H (0001 0010 0011 0100 0101 0110 0111 1000B) LSB first as an example.
Page 738: Chapter 22 Interrupt/Exception Processing Function
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850ES/SG2 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 54 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 739 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-1. Interrupt Source List (1/3) Type Classification Default Name Trigger Generating Exception Handler Restored Interrupt Priority Unit Code Address Control Register − − Reset Interrupt RESET RESET pin input RESET 0000H 00000000H Undefined Reset input by internal source −...
Page 740 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-1. Interrupt Source List (2/3) Type Classification Default Name Trigger Generating Exception Handler Restored Interrupt Priority Unit Code Address Control Register Maskable Interrupt INTTP1CC0 TMP1 capture 0/compare 0 TMP1 01A0H 000001AH nextPC TP1CCIC0 match INTTP1CC1 TMP1 capture 1/compare 1 TMP1 01B0H...
Page 741 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-1. Interrupt Source List (3/3) Type Classification Default Name Trigger Generating Exception Handler Restored Interrupt Priority Unit Code Address Control Register Maskable Interrupt INTUA1R/ UARTA1 reception completion/ UARTA1/ 0330H 00000330H nextPC UA1RIC/ Note 1 INTIIC2 UARTA1 reception error/ IIC2...
Page 742: Non-Maskable Interrupts
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.2 Non-Maskable Interrupts A non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupt request signals.
Page 743 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation (2/2) (b) Non-maskable interrupt request signal generated during non-maskable interrupt servicing Non-maskable Non-maskable interrupt request signal generated during non-maskable interrupt servicing interrupt being INTWDT2 serviced • NMI request generated during NMI servicing •...
Page 744: Operation
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.2.1 Operation If a non-maskable interrupt request signal is generated, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3>...
Page 745: Restore
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.2.2 Restore (1) From NMI input Execution is restored from the NMI servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1>...
Page 746: Np Flag
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt servicing is under execution. This flag is set when a non-maskable interrupt request signal has been acknowledged, and masks non-maskable interrupt requests to prohibit multiple interrupts from being acknowledged.
Page 747 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt falling edge specification register 0 (INTF0) The INTF0 register is an 8-bit register that specifies detection of the falling edge of an NMI via bit 2. This register can be read or written in 8-bit or 1-bit units. Reset input cleats this register to 00H.
Page 748: Maskable Interrupts
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3 Maskable Interrupts Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/SG2 has 54 maskable interrupt sources. If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority.
Page 749 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-4. Maskable Interrupt Servicing INT input INTC accepted xxIF = 1 Interrupt requested? xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently being serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests...
Page 750: Restore
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. <1>...
Page 751: Priorities Of Maskable Interrupts
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.3 Priorities of maskable interrupts The INTC performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 752 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-6. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b (level 3) Interrupt request b is acknowledged because the (level 2) priority of b is higher than that of a and interrupts are...
Page 753 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-6. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k...
Page 754 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-7. Example of Servicing Interrupt Request Signals Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Servicing of interrupt request b Interrupt request b and c are Interrupt request c (level 1) acknowledged first according to their priorities.
Page 755: Interrupt Control Register (Xxicn)
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.4 Interrupt control register (xxICn) The xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 47H.
Page 756 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-3. Interrupt Control Register (xxICn) (1/2) Address Register <7> <6> FFFFF110H LVIIC LVIIF LVIMK LVIPR2 LVIPR1 LVIPR0 FFFFF112H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF114H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF116H PIC2 PIF2 PMK2 PPR22 PPR21...
Page 757 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-3. Interrupt Control Register (xxICn) (2/2) Address Register <7> <6> FFFFF162H UA0RIC/ UA0RIF/ UA0RMK/ UA0RPR2/ UA0RPR1/ UA0RPR0/ CB4RIC CB4RIF CB4RMK CB4RPR2 CB4RPR1 CB4RPR0 FFFFF164H UA0TIC/ UA0TIF/ UA0TMK/ UA0TPR2/ UA0TPR1/ UA0TPR0/ CB4TIC CB4TIF CB4TMK CB4TPR2 CB4TPR1 CB4TPR0 FFFFF166H...
Page 758: Interrupt Mask Registers 0 To 3 (Imr0 To Imr3)
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) The IMR0 to IMR3 registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR3 registers is equivalent to the xxMKn bit of the xxICn register. The IMRm register can be read or written in 16-bit units (m = 0 to 3).
Page 759: In-Service Priority Register (Ispr)
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.6 In-service priority register (ISPR) The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set to 1 and remains set while the interrupt is serviced.
Page 760: Id Flag
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.7 ID flag This flag controls the maskable interrupt’s operating state, and stores control information regarding enabling or disabling of interrupt request signals. An interrupt disable flag (ID) is incorporated, which is assigned to the PSW. After reset: 00000020H ID SAT CY OV...
Page 761: Watchdog Timer Mode Register 2 (Wdtm2)
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.8 Watchdog timer mode register 2 (WDTM2) The WDTM2 register is a special register and write-only in a specific sequence. This register can be read or written in 8-bit or 1-bit units (for details, see CHAPTER 12 FUNCTIONS OF WATCHDOG TIMER 2).
Page 762 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt falling edge specification register 0 (INTF0) The INTF0 register is an 8-bit register that specifies detection of the falling edge of the external interrupt pins (INTP0 to INTP3) by bits 3 to 6. This register can be read or written in 8-bit or 1-bit units.
Page 763 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) External interrupt falling edge specification register 3L (INTF3L) The INTF3L register is an 8-bit register that specifies detection of the falling edge of the external interrupt pin (INTP7). This register can be read or written in 8-bit or 1-bit units. Reset input cleats this register to 00H.
Page 764 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (5) External interrupt falling edge specification register 9H (INTF9H) The INTF9H register is an 8-bit register that specifies detection of the falling edge of the external interrupt pins (INTP4 to INTP6). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 765 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (7) Noise elimination control register Digital noise elimination can be selected for the INTP3 pin. The noise elimination settings are performed with the NFC register. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among /64, f /128, f /256, f...
Page 766: Software Exception
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. 22.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine.
Page 767: Restore
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.4.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. <2>...
Page 768: Ep Flag
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.4.3 EP flag The EP flag is bit 6 of the PSW, and is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. After reset: 00000020H NP EP ID SAT CY OV...
Page 769: Exception Trap
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.5 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/SG2, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 22.5.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B, and a sub-opcode (bit 16) of 0B.
Page 770 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-10. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC Restored PC DBPSW PSW.NP PSW.EP PSW.ID 00000060H Exception processing (2) Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC.
Page 771: Debug Trap
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.5.2 Debug trap A debug trap is an exception that is generated when the DBTRAP instruction is executed and is always acknowledged. Upon occurrence of a debug trap, the CPU performs the following processing. (1) Operation <1>...
Page 772 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restoration Restoration from a debug trap is executed with the DBRET instruction. With the DBRET instruction, the CPU performs the following steps and transfers control to the address of the restored PC. <1> The restored PC and PSW are read from DBPC and DBPSW. <2>...
Page 773: Interrupt Acknowledge Time Of Cpu
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.6 Interrupt Acknowledge Time of CPU Except the following cases, the interrupt acknowledge time of the CPU is 5 clocks minimum. To input interrupt request signals successively, input the next interrupt request signal at least 5 clocks after the preceding interrupt. •...
Page 774: Periods In Which Interrupts Are Not Acknowledged By Cpu
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.7 Periods in Which Interrupts Are Not Acknowledged by CPU An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending). The interrupt request non-sample instructions are as follows.
Page 775: Chapter 23 Key Interrupt Function
CHAPTER 23 KEY INTERRUPT FUNCTION 23.1 Function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the key return mode register (KRM). Table 23-1. Assignment of Key Return Detection Pins Flag Pin Description KRM0...
Page 776: Control Register
CHAPTER 23 KEY INTERRUPT FUNCTION 23.2 Control Register (1) Key return mode register (KRM) The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 777: Chapter 24 Standby Function
CHAPTER 24 STANDBY FUNCTION 24.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 24-1. Table 24-1.
Page 778 CHAPTER 24 STANDBY FUNCTION Figure 24-1. Status Transition Normal operation mode (operation with main clock) End of oscillation End of oscillation stabilization time count stabilization time count Note 1 Setup wait Setting of HALT mode Note 2 Interrupt End of oscillation stabilization time count Wait for stabilization Wait for stabilization...
Page 779 CHAPTER 24 STANDBY FUNCTION Figure 24-2. Status Transition (During Subclock Operation) Normal operation mode Wait for stabilization of oscillation (operation with main clock) End of oscillation stabilization time count Setting of subclock Setting of normal operation operation Note 1 Reset Subclock operation mode Setting of IDLE Note 2...
Page 780: Halt Mode
CHAPTER 24 STANDBY FUNCTION 24.2 HALT Mode 24.2.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues.
Page 781 CHAPTER 24 STANDBY FUNCTION (2) Releasing HALT mode by reset input The same operation as the normal reset operation is performed. Table 24-3. Operation Status in HALT Mode Setting of HALT Mode Operation Status Item When Subclock Is Not Used When Subclock Is Used Main clock oscillator Oscillation enabled...
Page 782: Idle1 Mode
CHAPTER 24 STANDBY FUNCTION 24.3 IDLE1 Mode 24.3.1 Setting and operation status The IDLE1 mode is set by clearing the PSM1 and PSM0 bits of the PSMR register to 00 and setting the STP bit of the PSC register to 1 in the normal operation mode. In the IDLE1 mode, the clock oscillator, PLL operation, and flash memory continue operating but clock supply to the CPU and other on-chip peripheral functions stops.
Page 783 CHAPTER 24 STANDBY FUNCTION Table 24-4. Operation After Releasing IDLE1 Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request Execution branches to the handler address after securing the prescribed setup time. signal Maskable interrupt request signal Execution branches to the handler address...
Page 784: Idle2 Mode
CHAPTER 24 STANDBY FUNCTION 24.4 IDLE2 Mode 24.4.1 Setting and operation status The IDLE2 mode is set by setting the PSM1 and PSM0 bits of the PSMR register to 10 and setting the STP bit of the PSC register to 1 in the normal operation mode. In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL operation, flash memory, and other on-chip peripheral functions stops.
Page 785 CHAPTER 24 STANDBY FUNCTION Table 24-6. Operation After Releasing IDLE2 Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request Execution branches to the handler address after securing the prescribed setup time. signal Maskable interrupt request signal Execution branches to the handler address...
Page 786: Securing Setup Time When Releasing Idle2 Mode
CHAPTER 24 STANDBY FUNCTION 24.4.3 Securing setup time when releasing IDLE2 mode Secure the setup time for the ROM (flash memory) after releasing the IDLE2 mode because the operation of the blocks other than the main clock oscillator stops after IDLE2 mode is set. (1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal Secure the specified setup time by setting the OSTS register.
Page 787: Software Stop Mode
CHAPTER 24 STANDBY FUNCTION 24.5 Software STOP Mode 24.5.1 Setting and operation status The software STOP mode is set by setting the PSM1 and PSM0 bits of the PSMR register to 01 and setting the STP bit of the PSC register to 1 in the normal operation mode. In the software STOP mode, the subclock oscillator continues operation but the main clock oscillator stops.
Page 788 CHAPTER 24 STANDBY FUNCTION Table 24-8. Operation After Releasing Software STOP Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Execution branches to the handler address after securing the oscillation stabilization time. Non-maskable interrupt request signal Maskable interrupt request signal Execution branches to the handler address...
Page 789: Securing Oscillation Stabilization Time When Releasing Software Stop Mode
CHAPTER 24 STANDBY FUNCTION 24.5.3 Securing oscillation stabilization time when releasing software STOP mode Secure the oscillation stabilization time for main clock oscillator after releasing the software STOP mode because the operation of the blocks other than the main clock oscillator stops after software STOP mode is set. (1) Releasing software STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal Secure the oscillation stabilization time by setting the OSTS register.
Page 790: Subclock Operation Mode
CHAPTER 24 STANDBY FUNCTION 24.7 Subclock Operation Mode 24.7.1 Setting and operation status The subclock operation mode is set by setting the CK3 bit of the PCC register to 1 in the normal operation mode. When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock.
Page 791 CHAPTER 24 STANDBY FUNCTION Table 24-10. Operation Status in Subclock Operation Mode Setting of Subclock Operation Mode Operation Status Item When Main Clock Is Oscillating When Main Clock Is Stopped Subclock oscillator Oscillation enabled Ring-OSC generator Oscillation enabled Note Operable Stops operation Operable Operable...
Page 792: Sub-Idle Mode
CHAPTER 24 STANDBY FUNCTION 24.8 Sub-IDLE Mode 24.8.1 Setting and operation status The sub-IDLE mode is set by setting the PSM1 and PSM0 bits of the PSMR register to 10 and setting the STP bit of the PSC register to 1 in the subclock operation mode. In this mode, the clock oscillator continues operation but clock supply to the CPU, flash memory, and the other on- chip peripheral functions is stopped.
Page 793 CHAPTER 24 STANDBY FUNCTION Table 24-11. Operation After Releasing Sub-IDLE Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request Execution branches to the handler address. signal Maskable interrupt request signal Execution branches to the handler address The next instruction is executed.
Page 794: Control Registers
CHAPTER 24 STANDBY FUNCTION 24.9 Control Registers (1) Power save control register (PSC) The PSC register is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the software STOP mode. This register is a special register (see 3.4.9 Special registers). Data can be written to this register only in a specific sequence so that its contents are not rewritten by mistake due to a program hang-up.
Page 795: Chapter 25 Reset Functions
CHAPTER 25 RESET FUNCTIONS 25.1 Overview The following reset functions are available. • Reset by RESET pin input • Reset by watchdog timer 2 overflow (WDT2RES) • System reset by low-voltage detector (LVI) • System reset by clock monitor (CLM) 25.2 Registers to Check Reset Source (1) Reset source flag register (RESF) The RESF register indicates from which source a reset signal is generated.
Page 796: Operation
CHAPTER 25 RESET FUNCTIONS 25.3 Operation 25.3.1 Reset operation via RESET pin When a low level is input to the RESET pin, the system is reset, and each hardware unit is initialized. When the level of the RESET pin is changed from low to high, the reset status is released. If the reset status is released by RESET pin input, the oscillation stabilization time elapses (reset value of OSTS register: 2 ) and then the CPU starts program execution.
Page 797 CHAPTER 25 RESET FUNCTIONS Figure 25-1. Timing of Reset Operation by RESET Pin Input Initialized to f /8 operation RESET Analog delay Analog delay Analog delay Analog delay (eliminated as noise) (eliminated as noise) Internal system reset signal Counting of oscillation stabilization time Oscillation stabilization timer overflows Figure 25-2.
Page 798: Reset Operation By Wdt2Res Signal
CHAPTER 25 RESET FUNCTIONS 25.3.2 Reset operation by WDT2RES signal When watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow (WDT2RES signal generation), a system reset is executed and the hardware is initialized to the initial status. Following watchdog timer 2 overflow, the reset status is entered and lasts the predetermined time (analog delay), and the reset status is then automatically released.
Page 799 CHAPTER 25 RESET FUNCTIONS Figure 25-3. Timing of Reset Operation by WDT2RES Signal Generation Initialized to f /8 operation WDT2RES Analog delay Internal system reset signal Analog delay Counting of oscillation stabilization time Oscillation stabilization timer overflow Preliminary User’s Manual U16541EJ1V0UM...
Page 800: Reset Operation By Low-Voltage Detector
CHAPTER 25 RESET FUNCTIONS 25.3.3 Reset operation by low-voltage detector If the supply voltage falls below the voltage detected by the low-voltage detector when LVI operation is enabled, a system reset is executed (when the LVIMD bit of the LVIM register is set to 1), and the hardware is initialized to the initial status.
Page 801 CHAPTER 25 RESET FUNCTIONS Figure 25-4. Timing of Reset Operation by Low-Voltage Detector Supply voltage detection voltage Time LVION reset signal Internal reset signal Preliminary User’s Manual U16541EJ1V0UM...
Page 802 CHAPTER 25 RESET FUNCTIONS (1) Low-voltage detection register (LVIM) The LVIM register is used to enable or disable low-voltage detection and select the operation mode. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF890H <7>...
Page 803 CHAPTER 25 RESET FUNCTIONS (2) Low-voltage detection level select register (LVIS) The LVIS register is used to select the low voltage level to be detected. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF891H LVIS...
Page 804: Clock Monitor
CHAPTER 25 RESET FUNCTIONS 25.3.4 Clock monitor (1) Function of clock monitor The clock monitor samples the main clock using the internal Ring-OSC and generates a reset request signal when oscillation of the main clock is stopped. Once the operation of the clock monitor has been enabled by the operation enable flag, it can be stopped only by reset.
Page 805 CHAPTER 25 RESET FUNCTIONS (2) Clock monitor mode register (CLM) The CLM register is used to select the operation mode of the clock monitor. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H Address: FFFFF870H <0>...
Page 806 CHAPTER 25 RESET FUNCTIONS (b) Operation in software STOP mode and after software STOP mode is released If the software STOP mode is set when the CLME bit = 1, the monitor operation is stopped in the software STOP mode and while the oscillation stabilization time is being counted. The monitor operation is automatically started after the oscillation stabilization time has elapsed.
Page 807: Chapter 26 Regulator
CHAPTER 26 REGULATOR 26.1 Outline The V850ES/SG2 include a regulator to reduce the power consumption and noise. This regulator supplies a stepped-down V power supply voltage to the oscillator block and internal logic circuits (except the A/D converter, D/A converter, and output buffer). The regulator output voltage is set to 2.5 V (±0.2 V). Figure 26-1.
Page 808: Operation
CHAPTER 26 REGULATOR 26.2 Operation The regulator of this product always operates in any mode (normal operation mode, HALT mode, IDLE1 mode, IDLE2 mode, software STOP mode, or during reset). Be sure to connect a capacitor (4.7 µ F (recommended value)) to the REGC pin to stabilize the regulator output. A diagram of the regulator pin connection method is shown below.
Page 809: Chapter 27 Rom Correction Function
CHAPTER 27 ROM CORRECTION FUNCTION 27.1 Overview The ROM correction function is used to replace part of the program in the mask ROM with the program of an external RAM or the internal RAM. By using this function, instruction bugs found in the mask ROM can be corrected at up to four places. Figure 27-1.
Page 810: Control Registers
CHAPTER 27 ROM CORRECTION FUNCTION 27.2 Control Registers (1) Correction address registers 0 to 3 (CORAD0 to CORAD3) The CORAD0 to CORAD3 registers set the first address (correction address) of the instruction to be corrected in the ROM. The program can be corrected at up to four places because four CORADn registers are provided (n = 0 to 3). The CORADn register can be read or written in 32-bit units.
Page 811 CHAPTER 27 ROM CORRECTION FUNCTION (2) Correction control register (CORCN) The CORCN register disables or enables the correction operation of each CORADn register (n = 0 to 3). Each channel can be enabled or disabled by this register. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
Page 812: Rom Correction Operation And Program Flow
CHAPTER 27 ROM CORRECTION FUNCTION 27.3 ROM Correction Operation and Program Flow <1> If the address to be corrected and the fetch address of the internal ROM match, the fetch code is replaced by the DBTRAP instruction. <2> When the DBTRAP instruction is executed, execution branches to address 00000060H. <3>...
Page 813 CHAPTER 27 ROM CORRECTION FUNCTION Figure 27-2. ROM Correction Operation and Program Flow Reset & start Initialize microcontroller Set CORADn register Load program for judgment Read data for setting ROM of ROM correction and correction from external memory correction codes Set CORCN register CORENn bit = 1? Execute fetch code...
Page 814: Chapter 28 Flash Memory
CHAPTER 28 FLASH MEMORY The following products are the flash memory versions of the V850ES/SG2. Caution There are differences in the amount of noise tolerance and noise radiation between flash memory versions and mask ROM versions. When considering changing from a flash memory version to a mask ROM version during the process from experimental manufacturing to mass production, make sure to sufficiently evaluate commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions.
Page 815: Features
CHAPTER 28 FLASH MEMORY 28.1 Features • 4-byte/1-clock access (in instruction fetch access) • Chip erase/block unit erase • Communication via serial interface with the dedicated flash programmer • Erase/write voltage: Can be erased/written with a single power supply (FLMD0 = V , FLMD1 = V •...
Page 816: Writing With Flash Programmer
CHAPTER 28 FLASH MEMORY 28.2 Writing with Flash Programmer Writing can be performed either on-board or off-board with the dedicated flash programmer. (1) On-board programming The contents of the flash memory are rewritten after the V850ES/SG2 is mounted on the target system. Mount connectors, etc., on the target system to connect the dedicated flash programmer.
Page 817: Communication Mode
CHAPTER 28 FLASH MEMORY 28.4 Communication Mode The communication between the dedicated flash programmer and the V850ES/SG2 is performed by serial communication using UARTA0 or CSIB0 of the V850ES/SG2. (1) UARTA0 Transfer rate: 4,800 to 76,800 bps Figure 28-2. Communication with Dedicated Flash Programmer (UARTA0) FLMD0, FLMD0 FLMD1...
Page 818 CHAPTER 28 FLASH MEMORY (3) CSIB0 + + + + HS Serial clock: Up to 1 MHz (MSB first) Figure 28-4. Communication with Dedicated Flash Programmer (CSIB0 + + + + HS) FLMD0 FLMD0 Axxxx Bxxxxx RESET RESET Cxxxxxx STATVE PG-FP4 SOB0 Dedicated flash...
Page 819: Pin Connection
CHAPTER 28 FLASH MEMORY 28.5 Pin Connection When performing on-board writing, mount a connector on the target system to connect to the dedicated flash programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode.
Page 820: Flmd1 Pin
CHAPTER 28 FLASH MEMORY 28.5.2 FLMD1 pin When 0 V is input to the FLMD0 pin, the FLMD1 pin does not function. When V is supplied to the FLMD0 pin, the flash memory programming mode is entered, so 0 V must be input to the FLMD1 pin. An FLMD1 pin connection example is shown below.
Page 821: Serial Interface Pin
CHAPTER 28 FLASH MEMORY 28.5.3 Serial interface pin The following shows the pins used by each serial interface. Table 28-3. Pins Used by Serial Interfaces Serial Interface Pins Used CSIB0 SOB0, SIB0, SCKB0 CSIB0 + HS SOB0, SIB0, SCKB0, PCM0 UARTA0 TXDA0, RXDA0 When connecting a dedicated flash programmer to a serial interface pin that is connected to another device on-...
Page 822 CHAPTER 28 FLASH MEMORY (2) Malfunction of other device When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction.
Page 823: Reset Pin
CHAPTER 28 FLASH MEMORY 28.5.4 RESET pin When the reset signals of the dedicated flash programmer are connected to the RESET pin that is connected to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator.
Page 824: Programming Method
CHAPTER 28 FLASH MEMORY 28.6 Programming Method 28.6.1 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 28-10. Procedure for Manipulating Flash Memory Start Switch to flash memory Supplies RESET pulse programming mode Select communication system Manipulate flash memory End? Preliminary User’s Manual U16541EJ1V0UM...
Page 825: Flash Memory Programming Mode
CHAPTER 28 FLASH MEMORY 28.6.2 Flash memory programming mode When rewriting the contents of flash memory using the dedicated flash programmer, set the V850ES/SG2 to the flash memory programming mode. When switching modes, set the FLMD0 and FLMD1 pins before releasing reset. When performing on-board writing, change modes using a jumper, etc.
Page 826: Selection Of Communication Mode
CHAPTER 28 FLASH MEMORY 28.6.3 Selection of communication mode In the V850ES/SG2, the communication mode is selected by inputting pulses (12 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer.
Page 827: Communication Command
CHAPTER 28 FLASH MEMORY 28.6.4 Communication command The V850ES/SG2 communicate with the dedicated flash programmer by means of commands. The command sent from the dedicated flash programmer to the V850ES/SG2 is called a “command”. The response signal sent from the V850ES/SG2 to the dedicated flash programmer is called a “response command”.

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