Restore - NEC V850E/Dx3 Preliminary User's Manual

Interrupt Controller (INTC)
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5.2.2 Restore

(1) NMI0
Execution is restored from the non-maskable interrupt (NMI0) processing by
the RETI instruction.
When the RETI instruction is executed, the CPU performs the following
processing, and transfers control to the address of the restored PC.
<1> Restores the values of the PC and the PSW from FEPC and FEPSW,
respectively, because the EP bit of the PSW is 0 and the NP bit of the
PSW is 1.
<2> Transfers control back to the address of the restored PC and PSW.
Figure 5-4 illustrates how the RETI instruction is processed.
RETI instruction
1
PSW.EP
0
PSW.NP
0
PC EIPC
PSW EIPSW
Original processing restored
Figure 5-4 RETI instruction processing
Caution When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction
during non-maskable interrupt processing, in order to restore the PC and PSW
correctly during recovery by the RETI instruction, it is necessary to set
PSW.EP back to 0 and PSW.NP back to 1 using the LDSR instruction
immediately before the RETI instruction.
Note The solid line indicates the CPU processing flow.
(2) NMIWDT
Restoring by RETI instruction is not possible. Perform a system reset after
interrupt servicing.
Preliminary User's Manual U17566EE1V2UM00
1
PC FEPC
PSW FEPSW
Chapter 5
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