NEC V850E/Dx3 Preliminary User's Manual page 25

Introduction
Internal data RAM
Size
Clock Generator
Internal spread-spectrum PLL
Internal PLL (peripheral clock supply)
CPU frequency range
Peripheral frequency range
Main crystal frequency range (main oscillator)
Sub oscillator
Ring oscillator
Clock supervision
Auxiliary frequency output
Built-in power saving modes
HALT / IDLE / WATCH / Sub-WATCH / STOP
External memory bus interface (µPD70F3427 only)
Address/data separated busses
Chip select signals
DMA Controller
Number of channels
I/O ports
Input/output ports
Input ports
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Table 1-1 V850E/Dx3 features summary (2/4)
Preliminary User's Manual U17566EE1V2UM00
• 84 KB (µPD70F3426)
• 60 KB (µPD70F3427)
• 32KB (µPD70F3425)
• 24 KB (µPD70F3424)
• 20 KB (µPD70F3423)
• 16 KB (µPD70(F)3422)
• 12 KB (µPD70(F)3421)
• 6 KB (µPD70(F)3420)
• 48 MHz ± 5 % (µPD70F3424, µPD70F3425,
µPD70F3426, µPD70F3427)
• 24 MHz ± 5 % (µPD70(F)3420, µPD70(F)3421,
µPD70(F)3422, µPD70F3423)
8-fold PLL
• up to 50.4 MHz (µPD70F3424, µPD70F3425,
µPD70F3426, µPD70F3427)
• up to 25.2 MHz (µPD70(F)3420, µPD70(F)3421,
µPD70(F)3422, µPD70F3423)
up to 16 MHz
4 MHz
32 KHz (typ.)
240 KHz (typ.)
2 channels:
• main oscillator monitor
• sub oscillator monitor
24/32-bit
4
4
• µPD70F3427: 101
• all others: 98
16
Chapter 1
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