NEC V850E/Dx3 Preliminary User's Manual page 399

16-bit Timer/Event Counter P (TMP)
<1> Count operation start flow
<2> TPnCCR0, TPnCCR1 register
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START
Initial setting of these
Register initial setting
registers is performed
TPnCTL0
before setting the
(TPnCKS0 to TPnCKS2 bits)
TPnCE bit to 1.
TPnCTL1,
TPnIOC0,
TPnIOC2,
TPnCCR0,
TPnCCR1
The TPnCKS0 to
TPnCKS2 bits can be
set at the same time
TPnCE bit = 1
when counting is
enabled (TPnCE bit = 1).
setting change flow
TPnCCR1 write
Setting of TPnCCR0 register
processing is necessary
only when the set cycle
is changed.
When the counter is
Setting of TPnCCR1 register
cleared after setting,
the value of the TPnCCRm
register is transferred to the
CCRm buffer register.
Figure 11-24 Software processing flow in PWM output mode (1/2)
Preliminary User's Manual U17566EE1V2UM00
<3> TPnCCR0, TPnCCR1 register
setting change flow
Setting of TPnCCR1 register
<4> TPnCCR0, TPnCCR1 register
setting change flow
Setting of TPnCCR0 register
Setting of TPnCCR1 register
<5> Count operation stop flow
TPnCE bit = 0
STOP
Chapter 11
Only writing of the TPnCCR1
register must be performed
when the set duty factor is
changed. When the counter is
cleared after setting, the
value of compare register m
is transferred to the CCRm
buffer register.
When the counter is
cleared after setting,
the value of the TPnCCRm
register is transferred to the
CCRm buffer register.
Counting is stopped.
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