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Chapter 8
DRST
Bit position
3 to 0
320
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8.3.6 DRST - DMA restart register
The ENn bit of this register and the ENn bit of the DCHCn register are linked to
each other. This provides a fast way to check the status of all DMA channels.
This register can be read/written in 8-bit or 1-bit units.
7
6
5
4
0
0
0
0
Bit name
Function
EN3 to EN0 Specifies whether DMA transfer through DMA channel n is to be enabled or
disabled. This bit is cleared to 0 when DMA transfer is completed in accordance
with the terminal count output.
It is also cleared to 0 when DMA transfer is forcibly terminated by setting the
INITn bit to 1 or by NMI input.
0: DMA transfer disabled
1: DMA transfer enabled
Preliminary User's Manual U17566EE1V2UM00
3
2
1
0
EN3
EN2
EN1
EN0
DMA Controller (DMAC)
Initial
Address
value
FFFFF0F2H
00H
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