In-Service Priority Register (Ispr) - NEC V850E/RS1 User Manual

17.3.6 In-service priority register (ISPR)

This register holds the priority level of the maskable interrupt currently acknowledged. When an inter-
rupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt
request is set to 1 and remains set while the interrupt is serviced.
When the RETI instruction is executed, the bit corresponding to the interrupt request having the highest
priority is automatically reset to 0 by hardware. However, it is not reset to 0 when execution is returned
from non-maskable interrupt servicing or exception processing.
This register is read-only in 8-bit or 1-bit units.
Remark:
Caution:
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Chapter 17 Interrupt/Exception Processing Function
Figure 17-12: In-Service Priority Register (ISPR) Format
After reset: 00H
<7> <6>
ISPR ISPR7 ISPR6
ISPRn
0 Interrupt request signal with priority n not acknowledged
1 Interrupt request signal with priority n acknowledged
n = 0 to 7 (priority level)
If an interrupt is acknowledged while the ISPR register is being read in the interrupt
enabled (EI) status, the value of the ISPR register after the bits of the register have
been set by acknowledging the interrupt may be read. To accurately read the value of
the ISPR register before an interrupt is acknowledged, read the register while inter-
rupts are disable (DI).
User's Manual U16702EE3V2UD00
R Address:
<5> <4> <3>
ISPR5 ISPR4 ISPR3
Priority of interrupt currently acknowledged
FFFFF1FAH
<2> <1> <0>
ISPR2 ISPR1 ISPR0
705