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DBCn 316
DBPC 108
DBPSW 111
DCHCn 319
DDAHn 314
DDALn 315
Debug Function (on-chip)
Restrictions and
Debug function (on-chip) 877
Code protection 339
Debug Trap 224
DFEN0 94
DFEN1 96
Digital filter enable register
(DFEN0) 94
Digital filter enable register
(DFEN1) 96
Digitally filtered inputs 93
DMA (direct memory
access) 309
DMA Addressing Control Regis-
ters n (DADCn) 317
DMA Channel Control Regis-
ters n (DCHCn) 319
DMA Controller 309
Automatic restart
Channel priorities 325
Control registers 312
Forcible interruption 325
Forcible termination 326
Transfer completion 327
Transfer mode 328
Transfer object 324
Transfer start factors 325
Transfer type 324
DMA destination address regis-
ters Hn (DDAHn) 314
DMA destination address regis-
ters Ln (DDALn) 315
DMA Functions 309
DMA Restart Register
(DRST) 320
DMA source address registers
Hn (DSAHn) 312
DMA source address registers
Ln (DSALn) 313
DMA Transfer Count Registers
n (DBCn) 316
DMA Trigger Source Select
Register n (DTFRn) 321
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DMAnIC 210
DRST 320
DSAHn 312
DSALn 313
DTFRn 321
Duty factor (pulse width
DWCn 274
Cautions 890
E
ECR 112
EIPC 108
EIPSW 111
Element pointer 106
Endian configuration register
Endian format 282
Exception status flag (EP) 222
Exception trap 222
External bus properties 257
External devices
function 323
External interrupt configuration
External memory area 122
External reset 866
F
FCC 155
FEPC 108
FEPSW 111
Fixed peripheral I/O area 255
Flash area 119, 121
Flash memory 229
Flash programmer 238
Flash programming
Preliminary User's Manual U17566EE1V2UM00
modulation) 804
(BEC) 269
Bus access 258
Bus priority order 257
Bus width 257
Initialization for
access 259
Interface timing 284
registers (INTMn) 218
Address assignment 230
protection 339
Self-programming 234
Communication
mode 239
Pin connection 242
Programming
method 244
Mode 115
via N-Wire 237
Index
with flash
programmer 238
FOUTCLK control register
(FCC) 155
G
GCCn0 447
GCCn5 447
GCCnm 448
General purpose registers (r0 to
r31) 106
Global pointer 106
H
HALT Mode 169
I
2
I
C bus 573
Acknowledge signal 596
Address match detection
method 620
Arbitration 622
Cautions 624
Communication
operations 624
Control registers 578
Definitions and control
methods 594
Error detection 620
Extension code 621
Interrupt request signal
(INTIICn) generation
timing and wait
control 619
Interrupt request signals
(INTIICn) 601
Pin configuration 593
Stop condition 598
Timing of data
communication 631
Transfer direction
specification 596
Wait signal 599
Wakeup function 623
ICC 156
ID code 879
IDLE mode 170
Idle pins
Recommended
connection 98
Idle state insertion (access to
external devices) 284
IIC clock control register
925
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