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16-bit Timer/Event Counter P (TMP)
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(c) Notes on rewriting TPnCCR0 register
To change the value of the TPnCCR0 register to a smaller value, stop
counting once and then change the set value.
If the value of the TPnCCR0 register is rewritten to a smaller value during
counting, the 16-bit counter may overflow.
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
TPnOL0 bit
L
TOPn0 pin output
INTTPnCC0 signal
Interval time (1)
Note
1.
Interval time (1): (D
2.
Interval time (NG): (10000H + D
3.
Interval time (2): (D
If the value of the TPnCCR0 register is changed from D
count value is greater than D
transferred to the CCR0 buffer register as soon as the TPnCCR0 register
has been rewritten. Consequently, the value of the 16-bit counter that is
compared is D
Because the count value has already exceeded D
counter counts up to FFFFH, overflows, and then counts up again from
0000H. When the count value matches D
generated and the output of the TOPn0 pin is inverted.
Therefore, the INTTPnCC0 signal may not be generated at the interval
+ 1) × Count clock cycle" or "(D
time "(D
1
originally expected, but may be generated at an interval of
"(10000H + D
Preliminary User's Manual U17566EE1V2UM00
D
D
1
1
D
2
D
1
Interval time (NG)
+ 1) × Count clock cycle
1
+ 1) × Count clock cycle
2
+ 1) × Count clock cycle
2
but less than D
2
.
2
2
2
+ 1) × Count clock period".
2
Chapter 11
D
D
2
2
D
2
Interval
time (2)
to D
while the
1
2
, the count value is
1
, however, the 16-bit
2
, the INTTPnCC0 signal is
+ 1) × Count clock cycle"
363
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