NEC V850E/Dx3 Preliminary User's Manual page 288

Chapter 7
288
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(2) Read with address setup wait and idle state insertion
BCLK
A[23:0] (output)
CSk (output)
RD (output)
WR (output)
D[31:0] (I/O)
WAIT (input)
Figure 7-14 Timing: read data with address setup wait and idle state insertion
Register settings:
• BCTm.BTk0 = 0 (connected external device is SRAM or external I/O)
• ASC.ACk[1:0] = 01
• DWCm.DWk[2:0] = 000
• BCC.BCk[1:0] = 01
Note 1. The circles indicate the sampling timing.
2. The broken line indicates the high-impedance state (bus is not driven).
Preliminary User's Manual U17566EE1V2UM00
Bus and Memory Control (BCU, MEMC)
TASW T1 T2
Address
Data
(one address setup wait state inserted)
B
(no programmable data wait states inserted)
B
(one idle state inserted)
B
TI