Table of Contents
Advertisement
Chapter 17
542
Downloaded from
Elcodis.com
electronic components distributor
17.2 Configuration
The following shows the block diagram of CSIBn.
CBnCTL1
SPCLK1 (8 MHz)
BRGn
Note
PCLK1 (8 MHz)
PCLK2 (4 MHz)
PCLK3 (2 MHz)
PCLK4 (1 MHz)
PCLK5 (500 KHz)
PCLK6 (250 KHz)
SCKBn
SIBn
Figure 17-1
Block diagram of CSIBn
Note
The clock is generated by the dedicated baud rate generator BRGn.
Preliminary User's Manual U17566EE1V2UM00
Clocked Serial Interface (CSIB)
Internal bus
CBnCTL0
CBnCTL2
CBnSTR
Controller
Phase control
CBnTX
SO latch
Shift register
CBnRX
INTCBnT
INTCBnR
INTCBnRE
Phase
SOBn
control
Advertisement
Table of Contents
