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NEC V850ES/KF1 User Manual

32-bit single-chip microcontrollers

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User's Manual

V850ES/KF1

32-Bit Single-Chip Microcontrollers

Hardware

V850ES/KF1:

µ µ µ µ PD703208

µ µ µ µ PD703208(A)

µ µ µ µ PD703208Y

µ µ µ µ PD703208Y(A)

µ µ µ µ PD703209

µ µ µ µ PD703209(A)

µ µ µ µ PD703209Y

µ µ µ µ PD703209Y(A)

µ µ µ µ PD703210

µ µ µ µ PD703210(A)

µ µ µ µ PD703210Y

µ µ µ µ PD703210Y(A)

µ µ µ µ PD70F3210

µ µ µ µ PD70F3210(A)

µ µ µ µ PD70F3210Y

µ µ µ µ PD70F3210Y(A)

Document No. U15862EJ3V0UD00 (3rd edition)

Date Published January 2003 N CP(K)

Printed in Japan

www.DataSheet.in

TM

, V850ES/KG1

V850ES/KG1:

µ µ µ µ PD703212

µ µ µ µ PD703212(A)

µ µ µ µ PD703212Y

µ µ µ µ PD703212Y(A)

µ µ µ µ PD703213

µ µ µ µ PD703213(A)

µ µ µ µ PD703213Y

µ µ µ µ PD703213Y(A)

µ µ µ µ PD703214

µ µ µ µ PD703214(A)

µ µ µ µ PD703214Y

µ µ µ µ PD703214Y(A)

µ µ µ µ PD70F3214

µ µ µ µ PD70F3214(A)

µ µ µ µ PD70F3214Y

µ µ µ µ PD70F3214Y(A)

2002

TM

, V850ES/KJ1

V850ES/KJ1:

µ µ µ µ PD703216

µ µ µ µ PD703216(A)

µ µ µ µ PD703216Y

µ µ µ µ PD703216Y(A)

µ µ µ µ PD703217

µ µ µ µ PD703217(A)

µ µ µ µ PD703217Y

µ µ µ µ PD703217Y(A)

µ µ µ µ PD70F3217

µ µ µ µ PD70F3217(A)

µ µ µ µ PD70F3217Y

µ µ µ µ PD70F3217Y(A)

TM

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Summary of Contents for NEC V850ES/KF1

Page 1 User’s Manual V850ES/KF1 , V850ES/KG1 , V850ES/KJ1 32-Bit Single-Chip Microcontrollers Hardware V850ES/KF1: V850ES/KG1: V850ES/KJ1: µ µ µ µ PD703208 µ µ µ µ PD703212 µ µ µ µ PD703216 µ µ µ µ PD703208(A) µ µ µ µ PD703212(A) µ µ µ µ PD703216(A) µ...
Page 2 [MEMO] User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 3: Notes For Cmos Devices
C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. V850 Series, V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are trademarks of NEC Electronics Corporation. User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5: Regional Information
Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 703213(A), 703213Y(A), 703214(A), 703214Y(A), 703216(A), 703216Y(A), 703217(A), 703217Y(A), 70F3210(A), 70F3210Y(A), 70F3214(A), 70F3214Y(A), 70F3217(A), 70F3217Y(A) p. 33 Addition of Caution in 1.2.4 Pin configuration (top view) (V850ES/KF1) p. 41 Addition of Caution in 1.3.4 Pin configuration (top view) (V850ES/KG1) p. 49 Addition of Caution in 1.4.4 Pin configuration (top view) (V850ES/KJ1)
Page 7 544 Addition of description in CHAPTER 18 I C BUS Addition of Cautions in Table 25-1 Wiring Between µ PD70F3210 and 70F3210Y (V850ES/KF1), and PG-FP3 p. 682 p. 683 Addition of Figure 25-1 Wiring Example of V850ES/KF1 Flash Writing Adapter (FA-80GC-8BT, FA-80GK-9EU) Addition of Cautions in Table 25-2 Wiring Between µ...
Page 8 PREFACE Readers This manual is intended for users who wish to understand the functions of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 and design application systems using these products. The target products are as follows. • Standard products: µ PD703208, 703208Y, 703209, 703209Y, 703210, 703210Y,...
Page 9 → The name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. To understand the overall functions of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 → Read this manual according to the CONTENTS.
Page 10 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/KF1, V850ES/KG1, and V850ES/KJ1 Document Name Document No. V850ES Architecture User’s Manual U15943E V850ES/KF1, V850ES/KG1, V850ES/KJ1 Hardware User’s Manual This manual Documents related to development tools (user’s manuals)
Page 11: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION .........................29 V850ES/KF1, V850ES/KG1, and V850ES/KJ1 Product Lineup ..........29 V850ES/KF1 ..........................31 1.2.1 Features (V850ES/KF1) .........................31 1.2.2 Applications (V850ES/KF1) ......................32 1.2.3 Ordering information (V850ES/KF1)....................32 1.2.4 Pin configuration (top view) (V850ES/KF1) ..................33 1.2.5 Function block configuration (V850ES/KF1)...................35 V850ES/KG1..........................39 1.3.1 Features (V850ES/KG1).........................39...
Page 12 CHAPTER 4 PORT FUNCTIONS ......................137 Features ............................ 137 4.1.1 V850ES/KF1 ..........................137 4.1.2 V850ES/KG1 ..........................137 4.1.3 V850ES/KJ1 ..........................137 Basic Port Configuration......................138 4.2.1 V850ES/KF1 ..........................138 4.2.2 V850ES/KG1 ..........................139 4.2.3 V850ES/KJ1 ..........................140 Port Configuration........................141 4.3.1 Port 0 ............................
Page 13 Bus Hold Function ........................282 5.8.1 Functional outline .........................282 5.8.2 Bus hold procedure ........................283 5.8.3 Operation in power save mode.....................283 Bus Priority..........................284 5.10 Boundary Operation Conditions .....................284 5.10.1 Program space ..........................284 5.10.2 Data space ...........................284 5.11 Bus Timing..........................285 5.12 Cautions.............................291 CHAPTER 6 CLOCK GENERATION FUNCTION ................292 Overview ............................292 Configuration..........................293 Control Registers ........................295...
Page 14 8.4.8 Cautions ............................368 CHAPTER 9 8-BIT TIMERS H0 AND H1....................369 Functions ..........................369 Configuration..........................369 Control Registers ........................372 Operation ..........................376 9.4.1 Operation as interval timer......................376 9.4.2 PWM pulse generator mode operation ..................379 9.4.3 Carrier generator mode operation....................385 CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) ..............392 10.1 Function ............................
Page 15 13.5 Operation ...........................428 13.5.1 Basic operation..........................428 13.5.2 Conversion operation (software trigger mode) ................429 13.5.3 Power fail monitoring function ......................429 13.6 Cautions.............................430 13.7 How to Read A/D Converter Characteristics Table ...............432 CHAPTER 14 D/A CONVERTER ......................436 14.1 Functions ...........................436 14.2 Configuration..........................437 14.3 D/A Converter Control Register....................437 14.4...
Page 16 17.1 Functions ..........................501 17.2 Configuration..........................502 17.3 Control Registers ........................504 17.4 Operation ..........................513 17.4.1 Operation stop mode ........................513 17.4.2 3-wire serial I/O mode........................513 17.4.3 3-wire serial I/O mode with automatic transmit/receive function ..........521 CHAPTER 18 I C BUS ...........................544 18.1 Selecting UART2 or I...
Page 17 19.2.4 Noise elimination for NMI pin......................619 19.2.5 Edge detection function for NMI pin....................620 19.3 Maskable Interrupts ........................622 19.3.1 Operation............................622 19.3.2 Restore............................624 19.3.3 Priorities of maskable interrupts ....................625 19.3.4 Interrupt control register (xxlCn) ....................629 19.3.5 Interrupt mask registers 0 to 2 (IMR0 to IMR2)................634 19.3.6 In-service priority register (ISPR)....................637 19.3.7 Maskable interrupt status flag.......................638 19.3.8 Watchdog timer mode register 1 (WDTM1) ..................639...
Page 18 22.1 Overview ........................... 671 22.2 Configuration..........................671 22.3 Operation ..........................672 CHAPTER 23 REGULATOR ........................675 23.1 Overview ........................... 675 23.2 Operation ..........................675 CHAPTER 24 ROM CORRECTION FUNCTION..................677 24.1 Overview ........................... 677 24.2 Control Registers ........................678 24.2.1 Correction address registers 0 to 3 (CORAD0 to CORAD3)............678 24.2.2 Correction control register (CORCN) ...................
Page 19 LIST OF FIGURES (1/6) Figure No. Title Page CPU Address Space ..........................108 Address Space Image..........................109 Data Memory Map (Physical Addresses) ....................111 Program Memory Map ..........................112 Internal ROM/Internal Flash Memory Area (128 KB) ................. 113 Internal ROM Area (96 KB) ........................114 Internal ROM Area (64 KB) ........................
Page 20 4-39 Block Diagram of PDH0 to PDH7.......................250 4-40 Block Diagram of PDL0 to PDL15 ......................254 Data Memory Map (V850ES/KF1)......................266 Data Memory Map (V850ES/KG1) ......................267 Data Memory Map (V850ES/KJ1) ......................268 Little Endian Address in Word ........................271 Example of Inserting Wait States .......................279 Multiplex Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) ..............285...
Page 21 LIST OF FIGURES (3/6) Figure No. Title Page 7-15 Timing of Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) ........................332 7-16 Control Register Settings for Pulse Width Measurement by Restarting ............. 333 7-17 Timing of Pulse Width Measurement by Restarting (with Rising Edge Specified)........
Page 22 LIST OF FIGURES (4/6) Figure No. Title Page 12-1 Block Diagram of Watchdog Timer 1......................409 12-2 Block Diagram of Watchdog Timer 2......................416 13-1 Block Diagram of A/D Converter ........................420 13-2 Operation Sequence ..........................424 13-3 Relationship Between Analog Input Voltages and A/D Conversion Results..........427 13-4 Power Fail Monitoring Function (PFCM = 0) ....................429 13-5...
Page 23: List Of Figures
LIST OF FIGURES (5/6) Figure No. Title Page 17-1 Block Diagram of CSIAn ..........................503 17-2 3-Wire Serial I/O Mode Timing........................518 17-3 Format of Transmit/Receive Data ......................519 17-4 Transfer Bit Order Switching Circuit......................520 17-5 Automatic Transmission/Reception Mode Operation Timings..............529 17-6 Automatic Transmission/Reception Mode Flowchart .................
Page 24 Block Diagram of ROM Correction ......................677 24-2 ROM Correction Operation and Program Flow ..................680 25-1 Wiring Example of V850ES/KF1 Flash Writing Adapter (FA-80GC-8BT, FA-80GK-9EU) ......683 25-2 Wiring Example of V850ES/KG1 Flash Writing Adapter (FA-100GC-8EU) ..........685 25-3 Wiring Example of V850ES/KJ1 Flash Writing Adapter (FA-144GJ-UEN) ..........687 25-4 Environment for Writing Program to Flash Memory ...................688...
Page 25 Title Page Pin I/O Buffer Power Supplies........................55 Pin Operation Status in Operation Modes of V850ES/KF1 ................64 Pin Operation Status in Operation Modes of V850ES/KG1 ................. 65 Pin Operation Status in Operation Modes of V850ES/KJ1 ................65 Program Registers ............................. 100 System Register Numbers .........................
Page 26 LIST OF TABLES (2/4) Table No. Title Page Bus Priority..............................284 Operation Status of Each Clock .........................299 Configuration of 16-Bit Timer/Event Counters 00 to 05 ................303 Valid Edge of TI0n0 Pin and Capture Trigger of CR0n0 Register ..............305 Valid Edge of TI0n1 Pin and Capture Trigger of CR0n0 Register ..............305 Valid Edge of TI0n0 Pin and Capture Trigger of CR0n1 Register ..............307 Configuration of 8-Bit Timer/Event Counters 50 and 51 ................351 Configuration of 8-Bit Timers H0 and H1....................369...
Page 27 Hardware Status on Occurrence of WDTRES1 ..................673 24-1 Correspondence Between CORCN Register Bits and CORADn Registers ..........679 Wiring Between µ PD70F3210 and 70F3210Y (V850ES/KF1), and PG-FP3 ..........682 25-1 Wiring Between µ PD70F3214 and 70F3214Y (V850ES/KG1), and PG-FP3..........684 25-2 Wiring Between µ...
Page 28: List Of Tables
LIST OF TABLES (4/4) Table No. Title Page 25-4 Signals Generated by Dedicated Flash Programmer (PG-FP3)..............690 25-5 Pins Used by Each Serial Interface......................692 25-6 Communication Modes..........................696 25-7 Flash Memory Control Commands......................697 25-8 Response Commands..........................698 28-1 Surface Mounting Type Soldering Conditions ....................745 User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 29: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION 1.1 V850ES/KF1, V850ES/KG1, and V850ES/KJ1 Product Lineup 144-pin plastic LQFP (fine pitch) (20 × 20) V850ES/KJ1 µ PD70F3217 Flash memory: 128 KB, RAM: 6 KB µ C bus version PD70F3217Y µ PD703217 Mask ROM: 128 KB, RAM: 6 KB µ...
Page 30 – µ PD70F3217Y 2 ch Remark In this manual, the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 product names are used as follows. • Mask ROM versions V850ES/KF1: µ PD703208, 703208Y, 703209, 703209Y, 703210, 703210Y V850ES/KG1: µ PD703212, 703212Y, 703213, 703213Y, 703214, 703214Y V850ES/KJ1: µ...
Page 31: V850Es/Kf1
CHAPTER 1 INTRODUCTION 1.2 V850ES/KF1 1.2.1 Features (V850ES/KF1) Number of instructions: 83 Minimum instruction execution time: 50 ns (operation at main clock (f ) = 20 MHz) General-purpose registers: 32 bits × 32 registers Instruction set: Signed multiplication (16 × 16 → 32): 1 to 2 clocks...
Page 32: Applications (V850Es/Kf1)
P l e a s e r e f e r t o " Q u a l i t y G r a d e s o n N E C S e m i c o n d u c t o r D e v i c e s " ( D o c u m e n t N o . C 1 1 5 3 1 E ) p u b l i s h e d b y NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Page 33: Pin Configuration (Top View) (V850Es/Kf1)
CHAPTER 1 INTRODUCTION 1.2.4 Pin configuration (top view) (V850ES/KF1) 80-pin plastic QFP (14 × 14) 80-pin plastic TQFP (fine pitch) (12 × 12) µ PD703208GC-×××-8BT µ PD703209GK-×××-9EU µ PD70F3210GC-8BT µ PD703208YGC-×××-8BT µ PD703209YGK-×××-9EU µ PD70F3210YGC-8BT µ PD703208GK-×××-9EU µ PD703210GC-×××-8BT µ PD70F3210GK-9EU µ...
Page 34 CHAPTER 1 INTRODUCTION Pin Identification (V850ES/KF1) AD0 to AD15: Address/data bus Read strobe ANI0 to ANI7: Analog input REGC: Regulator control ASCK0: Asynchronous serial clock RESET: Reset ASTB: Address strobe RTP00 to RTP05: Real-time output port Analog reference voltage RXD0, RXD1:...
Page 35: Function Block Configuration (V850Es/Kf1)
CHAPTER 1 INTRODUCTION 1.2.5 Function block configuration (V850ES/KF1) (1) Internal block diagram INTC Instruction INTP0 to INTP6 Note 1 queue HLDRQ 16-bit 32-bit barrel Multiplier HLDAK TI000, TI001,TI010, TI011 timer/event 16 × 16→32 shifter ASTB TO00, TO01 counter: 2 ch...
Page 36 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) help accelerate processing of complex instructions.
Page 37 Serial interface (SIO) The V850ES/KF1 includes four kinds of serial interfaces: an asynchronous serial interface (UARTn), a clocked serial interface (CSI0n), a clocked serial interface (with an automatic transmit/receive function) C0). The µ PD703208, 703209, 703210, and 70F3210 can...
Page 38 CHAPTER 1 INTRODUCTION (o) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port Port Function Control Function 7-bit I/O General-purpose port NMI, external interrupt, timer output 8-bit I/O Serial interface, timer I/O 3-bit I/O Serial interface 6-bit I/O Serial interface, timer I/O, key interrupt function, real-time output function...
Page 39: V850Es/Kg1
CHAPTER 1 INTRODUCTION 1.3 V850ES/KG1 1.3.1 Features (V850ES/KG1) Number of instructions: 83 Minimum instruction execution time: 50 ns (operation at main clock (f ) = 20 MHz) General-purpose registers: 32 bits × 32 registers Instruction set: Signed multiplication (16 × 16 → 32): 1 to 2 clocks (Instructions without creating register hazards can be continuously executed in parallel) Saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock...
Page 40: Applications (V850Es/Kg1)
P l e a s e r e f e r t o " Q u a l i t y G r a d e s o n N E C S e m i c o n d u c t o r D e v i c e s " ( D o c u m e n t N o . C 1 1 5 3 1 E ) p u b l i s h e d b y NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Page 41: Pin Configuration (Top View) (V850Es/Kg1)
CHAPTER 1 INTRODUCTION 1.3.4 Pin configuration (top view) (V850ES/KG1) 100-pin plastic LQFP (fine pitch) (14 × 14) µ PD703212GC-×××-8EU µ PD703214GC-×××-8EU µ PD703212YGC-×××-8EU µ PD703214YGC-×××-8EU µ PD703213GC-×××-8EU µ PD70F3214GC-8EU µ PD703213YGC-×××-8EU µ PD70F3214YGC-8EU µ PD703212GC(A)-×××-8EU µ PD703214GC(A)-×××-8EU µ PD703212YGC(A)-×××-8EU µ PD703214YGC(A)-×××-8EU µ...
Page 42 CHAPTER 1 INTRODUCTION Pin Identification (V850ES/KG1) A0 to A21: Address bus Read strobe AD0 to AD15: Address/data bus REGC: Regulator control ANI0 to ANI7: Analog input RESET: Reset ANO0, ANO1: Analog output RTP00 to RTP05: Real-time output port ASCK0: Asynchronous serial clock RXD0, RXD1: Receive data ASTB:...
Page 43: Function Block Configuration (V850Es/Kg1)
CHAPTER 1 INTRODUCTION 1.3.5 Function block configuration (V850ES/KG1) (1) Internal block diagram INTC Instruction INTP0 to INTP6 Note 1 queue HLDRQ TI000, TI001, TI010, TI011, 16-bit 32-bit barrel Multiplier HLDAK TI020, TI021, TI030, TI031 16 × 16→32 timer/event ASTB shifter TO00 to TO03 counter: 4 ch WAIT...
Page 44 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) help accelerate processing of complex instructions.
Page 45 CHAPTER 1 INTRODUCTION Watchdog timer Two watchdog timer channels are provided on chip to detect program loops and system abnormalities. Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a non- maskable interrupt request signal (INTWDT1) or system reset (WDTRES1) after an overflow occurs.
Page 46 CHAPTER 1 INTRODUCTION (p) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port Port Function Control Function 7-bit I/O General-purpose port NMI, external interrupt, timer output 2-bit I/O D/A converter analog output 10-bit I/O Serial interface, timer I/O 3-bit I/O Serial interface...
Page 47: V850Es/Kj1
CHAPTER 1 INTRODUCTION 1.4 V850ES/KJ1 1.4.1 Features (V850ES/KJ1) Number of instructions: 83 Minimum instruction execution time: 50 ns (operation at main clock (f ) = 20 MHz) General-purpose registers: 32 bits × 32 registers Instruction set: Signed multiplication (16 × 16 → 32): 1 to 2 clocks (Instructions without creating register hazards can be continuously executed in parallel) Saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock...
Page 48: Applications (V850Es/Kj1)
P l e a s e r e f e r t o " Q u a l i t y G r a d e s o n N E C S e m i c o n d u c t o r D e v i c e s " ( D o c u m e n t N o . C 1 1 5 3 1 E ) p u b l i s h e d b y NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Page 49: Pin Configuration (Top View) (V850Es/Kj1)
CHAPTER 1 INTRODUCTION 1.4.4 Pin configuration (top view) (V850ES/KJ1) 144-pin plastic LQFP (fine pitch) (20 × 20) µ PD703216GJ-×××-UEN µ PD70F3217GJ-UEN µ PD703217GJ(A)-×××-UEN µ PD703216YGJ-×××-UEN µ PD70F3217YGJ-UEN µ PD703217YGJ(A)-×××-UEN µ PD703217GJ-×××-UEN µ PD703216GJ(A)-×××-UEN µ PD70F3217GJ(A)-UEN µ PD703217YGJ-×××-UEN µ PD703216YGJ(A)-×××-UEN µ PD70F3217YGJ(A)-UEN PDL3/AD3 REF0 PDL2/AD2...
Page 50 CHAPTER 1 INTRODUCTION Pin Identification (V850ES/KJ1) A0 to A23: Address bus PDL0 to PDL15: Port DL AD0 to AD15: Address/data bus Read strobe ANI0 to ANI15: Analog input REGC: Regulator control ANO0, ANO1: Analog output RESET: Reset ASCK0: Asynchronous serial clock RTP00 to RTP05, ASTB: Address strobe...
Page 51: Function Block Configuration (V850Es/Kj1)
CHAPTER 1 INTRODUCTION 1.4.5 Function block configuration (V850ES/KJ1) (1) Internal block diagram INTC Instruction INTP0 to INTP6 Note 1 queue TI000, TI001, TI010, TI011, HLDRQ TI020, TI021, TI030, TI031, 16-bit 32-bit barrel Multiplier HLDAK TI040, TI041, TI050, TI051 timer/event 16 × 16→32 ASTB shifter TO00 to TO05...
Page 52 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) help accelerate processing of complex instructions.
Page 53 CHAPTER 1 INTRODUCTION Watchdog timer Two watchdog timer channels are provided on chip to detect program loops and system abnormalities. Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a non- maskable interrupt request signal (INTWDT1) or system reset signal (WDTRES1) after an overflow occurs.
Page 54 CHAPTER 1 INTRODUCTION (p) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port Port Function Control Function 7-bit I/O General-purpose port NMI, external interrupt, timer output 2-bit I/O D/A converter analog output 10-bit I/O Serial interface, timer I/O 3-bit I/O Serial interface...
Page 55: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS The names and functions of the pins of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are described below, divided into port pins and non-port pins. The pin I/O buffer power supplies are divided into three systems; AV , BV , and EV .
Page 56 CHAPTER 2 PIN FUNCTIONS (2/4) Pin Name Pull-up Resistor Function Alternate Function Products Port 4 SI00 All products I/O port SO00 Input/output can be specified in 1-bit units. SCK00 Port 5 TI011/RTP00/KR0 All products I/O port TI50/RTP01/KR1 Input/output can be specified in 1-bit units. TO50/RTP02/KR2 SIA0/RTP03/KR3 SOA0/RTP04/KR4...
Page 57 PCS3 PCS4 – PCS5 – PCS6 – PCS7 – Note Only for the µ PD703216Y, 703217Y, and 70F3217Y Remarks 1. KG1: V850ES/KG1, KJ1: V850ES/KJ1 2. The A0 to A15 pins are not provided in the V850ES/KF1. User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 58 CHAPTER 2 PIN FUNCTIONS (4/4) Pin Name Pull-up Resistor Function Alternate Function Products PCT0 Port CT All products I/O port PCT1 Input/output can be specified in 1-bit units. PCT2 – PCT3 – PCT4 All products PCT5 – PCT6 ASTB All products PCT7 –...
Page 59 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/5) Pin Name Pull-up Resistor Function Alternate Function Products KG1, KJ1 Output Address bus for external memory P90/TDX1/KR6 (when using a separate bus) P91/RXD1/KR7 P92/TI020/TO2 P93/TI021 P94/TI030/TO3 P95/TI031 P96/TI51/TO51 P97/SI01 P98/SO01 P99/SCK01 P910/SIA1 P911/SOA1 P912/SCKA1 P913/INTP4...
Page 60 CHAPTER 2 PIN FUNCTIONS (2/5) Pin Name Pull-up Resistor Function Alternate Function Products ANI0 Input Analog voltage input for A/D converter All products ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 P710 ANI11 P711 ANI12 P712 ANI13 P713 ANI14 P714 ANI15...
Page 61 CHAPTER 2 PIN FUNCTIONS (3/5) Pin Name Pull-up Resistor Function Alternate Function Products Input Key return input P50/TI011/RTP00 All products P51/TI50/RTP01 P52/TO50/RTP02 P53/SIA0/RTP03 P54/SOA0/RTP04 P55/SCKA0/RTP05 P90/A0/TXD1 P91/A1/RXD1 Input External interrupt input All products (non-maskable, analog noise elimination) Output Read strobe signal output for external memory PCT4 All products Connecting capacitor for regulator output stabilization...
Page 62 CHAPTER 2 PIN FUNCTIONS (4/5) Pin Name Pull-up Resistor Function Alternate Function Products SI00 Input Serial receive data input for CSI00 All products SI01 Serial receive data input for CSI01 P97/A7 SI02 Serial receive data input for CSI02 SIA0 Serial receive data input for CSIA0 P53/RTP03/KR3 All products KG1, KJ1...
Page 63 CHAPTER 2 PIN FUNCTIONS (5/5) Pin Name Pull-up Resistor Function Alternate Function Products WAIT Input External wait input PCM0 All products Output Write strobe for external memory (lower 8 bits) PCT0 All products Write strobe for external memory (higher 8 bits) PCT1 All products Input...
Page 64: Pin Status
During peripheral I/O access, the address bus outputs the addresses of the on-chip peripheral I/Os that are accessed. The data bus goes into the high-impedance state without data output. The external bus control signal becomes inactive. Table 2-2. Pin Operation Status in Operation Modes of V850ES/KF1 Note 1 Note 2...
Page 65 CHAPTER 2 PIN FUNCTIONS Table 2-3. Pin Operation Status in Operation Modes of V850ES/KG1 Note 1 Note 2 Operating Status Reset HALT Mode IDLE Mode/ Idle State Bus Hold STOP Mode AD0 to AD15 (PDL0 to PDL15) Hi-Z Operating Hi-Z Held Hi-Z A0 to A15 (P90 to P915)
Page 66: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.3 Description of Pin Functions 2.3.1 V850ES/KF1 (1) P00 to P06 (Port 0) ... I/O Port 0 is a 7-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P00 to P06 can also be used for NMI input, external interrupt request input, and timer H output in the control mode.
Page 67 CHAPTER 2 PIN FUNCTIONS (ii) RXD0 (receive data) ... Input This is the serial receive data input pin for UART0. (iii) ASCK0 (asynchronous serial clock) ... Input This is the serial baud rate clock input pin for UART0. (iv) TI000, TI001, TI010 (timer input) ... Input These are the external count clock input pins for the 16-bit timer.
Page 68 CHAPTER 2 PIN FUNCTIONS (4) P50 to P55 (port 5) ... I/O Port 5 is a 6-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P50 to P55 can also be used as 16-bit timer input, 8-bit timer I/O, and serial interface (CSIA0) I/O pins in control mode 1, and as real-time output port pins in control mode 2.
Page 69 CHAPTER 2 PIN FUNCTIONS (6) P70 to P77 (port 7) ... Input Port 7 is an 8-bit input-only port in which all the pins are fixed to input. In addition to functioning as input ports pins, P70 to P77 can also be used for A/D converter (ADC) analog input in the control mode.
Page 70 CM mode control register (PMCCM). (iii) HLDAK (hold acknowledge) ... Output This is the output pin for the acknowledge signal that indicates that the V850ES/KF1 has received a bus hold request and set the external address/data bus and the strobe pins to high impedance.
Page 71 CHAPTER 2 PIN FUNCTIONS (iv) HLDRQ (hold request) ... Input This is the input pin by which an external device requests the V850ES/KF1 to release the external address/data bus and strobe pins. This pin supports asynchronous input for CLKOUT. When this pin...
Page 72 CHAPTER 2 PIN FUNCTIONS (ii) WR1 (upper byte write strobe) ... Output This is the write strobe signal output pin for the higher data of the external 16-bit data bus. (iii) RD (read strobe) ... Output This is the strobe signal that indicates that the bus cycle currently being executed is a read cycle for the external memory or external peripheral I/O.
Page 73 CHAPTER 2 PIN FUNCTIONS (16) AV (ground for analog) This is the ground pin for the A/D converter. (17) AV (analog reference voltage) ... Input REF0 This is the pin for supplying the reference voltage for the A/D converter. (18) EV (power supply for ports) These are the positive power supply pins for the peripheral interface.
Page 74: V850Es/Kg1
CHAPTER 2 PIN FUNCTIONS 2.3.2 V850ES/KG1 (1) P00 to P06 (port 0) ... I/O Port 0 is a 7-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P00 to P06 can also be used for NMI input, external interrupt request input, and timer H output in the control mode.
Page 75 CHAPTER 2 PIN FUNCTIONS (b) Control mode P30 to P39 can be set to the port mode or control mode in 1-bit units by the port 3 mode control register (PMC3). P33 and P35 can be set to control mode 1 or control mode 2 in 1-bit units by the port 3 function control register (PFC3).
Page 76 CHAPTER 2 PIN FUNCTIONS (iii) SCK00 (serial clock) ... I/O This is the serial clock I/O pin for CSI00. (5) P50 to P55 (port 5) ... I/O Port 5 is a 6-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P50 to P55 can also be used as 16-bit timer input, 8-bit timer I/O, and serial interface (CSIA0) I/O pins in control mode 1, and as real-time output port pins in control mode 2.
Page 77 CHAPTER 2 PIN FUNCTIONS (6) P70 to P77 (port 7) ... Input Port 7 is an 8-bit input-only port in which all the pins are fixed to input. In addition to functioning as input ports pins, P70 to P77 can also be used for A/D converter (ADC) analog input in the control mode.
Page 78 CHAPTER 2 PIN FUNCTIONS (iv) TI020, TI021, TI030, TI031 (timer input) ... Input These are the external count clock input pins for the 16-bit timer. (v) TO02, TO03 (timer output) ... Output These are the pulse signal output pins for the 16-bit timer. (vi) TI51 (timer input) ...
Page 79 CHAPTER 2 PIN FUNCTIONS (ii) CLKOUT (clock output) ... Output This is the internal system clock output pin. Since it is in the port mode during the reset period, output is not performed from the CLKOUT pin. To perform CLKOUT output, set this pin to the control mode with the port CM mode control register (PMCCM).
Page 80 CHAPTER 2 PIN FUNCTIONS (a) Port mode PCT0, PCT1, PCT4, and PCT6 can be set to input or output in 1-bit units by the port CT mode register (PMCT). (b) Control mode PCT0, PCT1, PCT4, and PCT6 can be set to the port mode or control mode in 1-bit units by the PMCCT register.
Page 81 CHAPTER 2 PIN FUNCTIONS In addition to functioning as a port, PDL0 to PDL15 can also be used as an address/data bus in the multiplex mode and as a data bus in the separate mode when the memory is expanded externally in the control mode (external expansion mode).
Page 82 CHAPTER 2 PIN FUNCTIONS (21) BV (ground for bus interface) This is the ground pin for the bus interface. (22) EV (power supply for ports) This is the power supply pin for the peripheral interface. (23) EV (ground for ports) This is the ground pin for the peripheral interface.
Page 83: V850Es/Kj1
CHAPTER 2 PIN FUNCTIONS 2.3.3 V850ES/KJ1 (1) P00 to P06 (port 0) ... I/O Port 0 is a 7-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P00 to P06 can also be used for NMI input, external interrupt request input, and timer H output in the control mode.
Page 84 CHAPTER 2 PIN FUNCTIONS (b) Control mode P30 to P39 can be set to the port mode or control mode in 1-bit units by the port 3 mode control register (PMC3). P33 and P35 can be set to control mode 1 or control mode 2 in 1-bit units by the port 3 function control register (PFC3).
Page 85 CHAPTER 2 PIN FUNCTIONS (iii) SCK00 (serial clock) ... I/O This is the serial clock I/O pin for CSI00. (5) P50 to P55 (port 5) ... I/O Port 5 is a 6-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P50 to P55 can also be used as 16-bit timer input, 8-bit timer I/O, and serial interface (CSIA0) I/O pins in control mode 1, and as real-time output port pins in control mode 2.
Page 86 CHAPTER 2 PIN FUNCTIONS (6) P60 to P615 (port 6) ... I/O Port 6 is a 16-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as an I/O port, P60 to P615 can also be used for real-time output port function, serial interface (CSI02) I/O, and 16-bit timer I/O in control mode 1, and for 16-bit timer output in control mode 2.
Page 87 CHAPTER 2 PIN FUNCTIONS (b) Control mode (alternate function) P70 to P715 are shared with ANI0 to ANI15, but switching is not possible. ANI0 to ANI15 (analog input) ... Input These are the analog input pins to the A/D converter (ADC). (8) P80, P81 (port 8) ...
Page 88 CHAPTER 2 PIN FUNCTIONS (a) Port mode P90 to P915 can be set to input or output in 1-bit units by the port 9 mode register (PM9). (b) Control mode (alternate function) P90 to P915 can be set to the port mode or control mode in 1-bit units by the port 9 mode control register (PMC9) (when used as the A0 to A15 pins, mode switching in 16-bit units is necessary).
Page 89 CHAPTER 2 PIN FUNCTIONS (10) PCD0 to PCD3 (port CD) ... I/O Port CD is a 4-bit I/O port for which input and output can be set in 1-bit units. PCD0 to PCD3 operate as an I/O port. (a) Port mode PCD0 to PCD3 can be set to input or output in 1-bit units by the port CD mode register (PMCD).
Page 90 CHAPTER 2 PIN FUNCTIONS (12) PCS0 to PCS7 (port CS) ... I/O Port CS is an 8-bit I/O port for which input and output can be set in 1-bit units. In addition to functioning as a port, PCS0 to PCS7 can also be used for chip select signal output when the memory is expanded externally in the control mode.
Page 91 CHAPTER 2 PIN FUNCTIONS (14) PDH0 to PDH7 (port DH) ... I/O Port DH is an 8-bit I/O port that can be set to input or output in 1-bit units. In addition to functioning as a port, PDH0 to PDH7 can also be used as an address bus (A16 to A23) when the memory is expanded externally in the control mode (external expansion mode).
Page 92 CHAPTER 2 PIN FUNCTIONS (17) REGC (regulator control) ... Input This is the pin for connecting a capacitor for the regulator. (18) X1, X2 (crystal for main clock) These pins are used to connect the resonator that generates the main clock. An external clock can also be input.
Page 93: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins (1/3) Alternate Function I/O Circuit Type Recommended Connection Product TOH0 Input: Independently connect to EV or EV via a All products resistor. TOH1 Output: Leave open. P03 to P06 INTP0 to INTP3 KG1, KJ1...
Page 94 All products P914, P915 A14/INTP5, A15/INTP6 PCD0 to PCD3 – Input: Independently connect to BV or BV via a resistor. (For the V850ES/KF1, independently PCM0 WAIT All products connect to EV or EV via a resistor.) PCM1 CLKOUT Output: Leave open...
Page 95 CHAPTER 2 PIN FUNCTIONS (3/3) Alternate Function I/O Circuit Type Recommended Connection Target Product KG1, KJ1 – – – KG1, KJ1 – – – – – – All products – – – All products Note 1 – – Directly connect to EV or V or pull down with a All products...
Page 96: Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS 2.5 Pin I/O Circuits (1/2) Type 2 Type 8-A Pullup P-ch enable Data P-ch IN/OUT Output N-ch Schmitt-triggered input with hysteresis characteristics disable Type 5 Type 9-C P-ch Data P-ch Comparator – IN/OUT N-ch Output N-ch (threshold voltage) disable REF0...
Page 97 CHAPTER 2 PIN FUNCTIONS (2/2) Type 10-F Type 13-B Mask Pullup option P-ch enable IN/OUT Data N-ch Output disable Data P-ch IN/OUT Open drain N-ch Output disable P-ch Input Medium-voltage input buffer enable Type 12-B Type 16 REF1 Pullup P-ch enable Feedback cut-off REF1...
Page 98: Chapter 3 Cpu Functions
CHAPTER 3 CPU FUNCTIONS The CPU of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 is based on the RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline control. 3.1 Features Number of instructions: Minimum instruction execution time: 50.0 ns (@ 20 MHz operation, 4.5 to 5.5 V, not using regulator) 62.5 ns (@ 16 MHz operation, 4.0 to 5.5 V, using regulator)
Page 99: Cpu Register Set
CHAPTER 3 CPU FUNCTIONS 3.2 CPU Register Set The CPU registers of the V850ES/KF1, V850ES/KG1 and V850ES/KJ1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers have 32-bit width.
Page 100: Program Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. All of these registers can be used as a data variable or address variable.
Page 101: System Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (LDSR, STSR instructions). Table 3-2.
Page 102 CHAPTER 3 CPU FUNCTIONS (1) Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the contents of the program status word (PSW) are saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)).
Page 103 CHAPTER 3 CPU FUNCTIONS (2) NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the program status word (PSW) are saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to FEPC, except for some instructions.
Page 104 CHAPTER 3 CPU FUNCTIONS (4) Program status word (PSW) A program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of the LDSR instruction execution.
Page 105 CHAPTER 3 CPU FUNCTIONS (2/2) Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set to 1 only when the OV flag is set to 1 during saturated operation. Operation result status Flag status Saturated...
Page 106 CHAPTER 3 CPU FUNCTIONS (6) Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW.
Page 107: Operation Modes
CHAPTER 3 CPU FUNCTIONS 3.3 Operation Modes The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have the following operating modes. (1) Normal operating mode After the system has been released from the reset state, the pins related to the bus interface are set to the port mode, execution branches to the reset entry address of the internal ROM, and instruction processing is started.
Page 108: Address Space
3.4 Address Space 3.4.1 CPU address space The CPU of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 uses a 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). When addressing instruction addresses, a linear address space (program space) of up to 64 MB is supported. However, both the program and data spaces include areas whose use is prohibited.
Page 109: Image
CHAPTER 3 CPU FUNCTIONS 3.4.2 Image Up to 16 MB of external memory area in a linear address space (program area) of up to 16 MB, internal ROM area, and internal RAM area are supported for instruction address addressing. During operand addressing (data access), up to 4 GB of linear address space (data space) is supported.
Page 110: Wraparound Of Cpu Address Space
CHAPTER 3 CPU FUNCTIONS 3.4.3 Wraparound of CPU address space (1) Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calculation, the higher 6 bits ignore this and remain 0.
Page 111: Memory Map
(1 MB) 0000000H 0000000H Notes 1. Only for the V850ES/KJ1. Access-prohibited area for the V850ES/KF1 and V850ES/KG1. 2. 64 KB for the V850ES/KF1 3. Fetch access and read access to addresses 0000000H to 00FFFFFH is performed for the internal ROM area, but in the case of data write access, it is performed for an external memory area.
Page 112 Internal ROM area (1 MB) 00000000H Notes 1. Only for the V850ES/KJ1. Access-prohibited area for the V850ES/KF1 and V850ES/KG1. 2. 64 KB for the V850ES/KF1 Remark Instruction execution for external memory areas without branching from the internal ROM area to an external memory area can be performed.
Page 113: Areas
A 128 KB area from 0000000H to 001FFFFH is provided in the following products. Addresses 0020000H to 00FFFFFH are an access-prohibited area. • V850ES/KF1 ( µ PD703210, 703210Y, 70F3210, 70F3210Y) • V850ES/KG1 ( µ PD703214, 703214Y, 70F3214, 70F3214Y) • V850ES/KJ1 ( µ PD703217, 703217Y, 70F3217, 70F3217Y) Figure 3-5.
Page 114 A 96 KB area from 0000000H to 0017FFFH is provided in the following products. Addresses 0018000H to 00FFFFFH are an access-prohibited area. • V850ES/KF1 ( µ PD703209, 703209Y) • V850ES/KG1 ( µ PD703213, 703213Y) • V850ES/KJ1 ( µ PD703216, 703216Y) Figure 3-6.
Page 115 CHAPTER 3 CPU FUNCTIONS • Interrupt/exception table The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 increase the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. This group of handler addresses is called an interrupt/exception table. This table is located in the internal ROM area.
Page 116 A 6 KB area from 3FFD800H to 3FFEFFFH is provided as physical internal RAM. Addresses 3FF0000H to 3FFD7FFH are an access-prohibited area. • V850ES/KF1 ( µ PD703210, 703210Y, 70F3210, 70F3210Y) • V850ES/KG1 ( µ PD703214, 703214Y, 70F3214, 70F3214Y) • V850ES/KJ1 ( µ PD703216, 703216Y, 703217, 703217Y, 70F3217, 70F3217Y) Figure 3-8.
Page 117 A 4 KB area from 3FFE000H to 3FFEFFFH is provided as physical internal RAM in the following products. Addresses 3FF0000H to 3FFDFFFH are an access-prohibited area. • V850ES/KF1 ( µ PD703218, 703218Y, 703219, 703219Y) • V850ES/KG1 ( µ PD703212, 703212Y, 703213, 70F3213Y) Figure 3-9.
Page 118 CHAPTER 3 CPU FUNCTIONS (3) On-chip peripheral I/O area A 4 KB area from 3FFF000H to 3FFFFFFH is reserved as the on-chip peripheral I/O area. Figure 3-10. On-Chip Peripheral I/O Area 3FFFFFFH On-chip peripheral I/O area (4 KB) 3FFF000H Peripheral I/O registers assigned with functions such as on-chip peripheral I/O operation mode specification and state monitoring are mapped to the on-chip peripheral I/O area.
Page 119: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTIONS 3.4.6 Peripheral I/O registers (1/12) Operable Bit Address Function Register Name Symbol After Reset √ FFFFF004H Port DL register Undefined √ √ FFFFF004H Port DL register L PDLL Undefined √ √ FFFFF005H Port DL register H PDLH Undefined √...
Page 120 CHAPTER 3 CPU FUNCTIONS (2/12) Operable Bit Address Function Register Name Symbol After Reset √ √ FFFFF118H Interrupt control register PIC3 √ √ FFFFF11AH Interrupt control register PIC4 √ √ FFFFF11CH Interrupt control register PIC5 √ √ FFFFF11EH Interrupt control register PIC6 √...
Page 121 FFFFF427H Port 3 mode register H PM3H Notes 1. Only for the V850ES/KJ1 2. Only for the µ PD703216Y, 703217Y, and 70F3217Y 3. Only for the V850ES/KG1 and V850ES/KJ1 4. Only for the V850ES/KF1 and V850ES/KG1 User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 122 CHAPTER 3 CPU FUNCTIONS (4/12) Operable Bit Address Function Register Name Symbol After Reset √ √ FFFFF428H Port 4 mode register √ √ FFFFF42AH Port 5 mode register √ Note FFFF42CH Port 6 mode register FFFFH √ √ Note FFFFF42CH Port 6 mode register L PM6L √...
Page 123 CHAPTER 3 CPU FUNCTIONS (5/12) Operable Bit Address Function Register Name Symbol After Reset √ FFFFF5C0H 16-bit timer counter 5 0000H √ FFFFF5C0H 8-bit timer counter 50 TM50 √ FFFFF5C1H 8-bit timer counter 51 TM51 √ FFFFF5C2H 16-bit timer compare register 5 0000H √...
Page 124 CHAPTER 3 CPU FUNCTIONS (6/12) Operable Bit Address Function Register Name Symbol After Reset √ Note FFFFF640H 16-bit timer counter 04 TM04 0000H √ Note FFFFF642H 16-bit timer capture/compare register 040 CR040 0000H √ Note FFFFF644H 16-bit timer capture/compare register 041 CR041 0000H √...
Page 125 CHAPTER 3 CPU FUNCTIONS (7/12) Operable Bit Address Function Register Name Symbol After Reset √ FFFFF84CH Correction address register 3 CORAD3 00000000H √ FFFFF84CH Correction address register 3L CORAD3L 0000H √ FFFFF84EH Correction address register 3H CORAD3H 0000H √ √ FFFFF880H Correction control register CORCN...
Page 126 CHAPTER 3 CPU FUNCTIONS (8/12) Operable Bit Address Function Register Name Symbol After Reset √ Note FFFFFC4CH Pull-up resistor option register 6 0000H √ √ Note FFFFFC4CH Pull-up resistor option register 6L PU6L √ √ Note FFFFFC4DH Pull-up resistor option register 6H PU6H √...
Page 127 CHAPTER 3 CPU FUNCTIONS (9/12) Operable Bit Address Function Register Name Symbol After Reset √ Note 1 FFFFFD22H Clocked serial interface receive buffer register 2 SIRB2 0000H √ Note 1 FFFFFD22H Clocked serial interface receive buffer register 2L SIRB2L √ Note 1 FFFFFD24H Clocked serial interface transmit buffer register 2...
Page 128 CHAPTER 3 CPU FUNCTIONS (10/12) Operable Bit Address Function Register Name Symbol After Reset √ √ Note FFFFFD96H IIC status register 1 IICS01 √ √ Note FFFFFD9AH IIC flag register 1 IICF1 √ FFFFFE00H CSIA0 buffer RAM 0 CSIA0B0 Undefined √...
Page 129 CHAPTER 3 CPU FUNCTIONS (11/12) Operable Bit Address Function Register Name Symbol After Reset √ FFFFFE1AH CSIA0 buffer RAM D CSIA0BD Undefined √ FFFFFE1AH CSIA0 buffer RAM DL CSIA0BDL Undefined √ FFFFFE1BH CSIA0 buffer RAM DH CSIA0BDH Undefined √ FFFFFE1CH CSIA0 buffer RAM E CSIA0BE Undefined...
Page 130 CHAPTER 3 CPU FUNCTIONS (12/12) Operable Bit Address Function Register Name Symbol After Reset √ Note FFFFFE36H CSIA1 buffer RAM B CSIA1BB Undefined √ Note FFFFFE36H CSIA1 buffer RAM BL CSIA1BBL Undefined √ Note FFFFFE37H CSIA1 buffer RAM BH CSIA1BBH Undefined √...
Page 131: Special Registers
Special registers are registers that prevent invalid data from being written when an inadvertent program loop occurs. The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have the following three special registers. • Power save control register (PSC) • Processor clock control register (PCC) •...
Page 132 CHAPTER 3 CPU FUNCTIONS Cautions 1. Interrupts are not acknowledged for the store instruction for the PRCMD register. This is because continuous execution of store instructions by the program in steps <3> and <4> above is assumed. If another instruction is placed between step <3> and <4>, the above sequence may not be realized when an interrupt is acknowledged for that instruction, which may cause malfunction.
Page 133 CHAPTER 3 CPU FUNCTIONS The operation conditions of the PRERR flag are described below. (a) Set conditions (PRERR = 1) When a write operation to the special register takes place without write operation being performed to the PRCMD register (when step <4> is performed without performing step <3> as described in 3.4.7 (1) Setting data to special registers).
Page 134: Cautions
The system wait control register (VSWC) controls the bus access wait time for the on-chip peripheral I/O registers. Access to the on-chip peripheral I/O register lasts 3 clocks (during no wait), but in the V850ES/KF1, V850ES/KG1 and V850ES/KJ1, waits are required according to the operation frequency. Set the values shown below to the VSWC register according to the operation frequency that is used.
Page 135 CHAPTER 3 CPU FUNCTIONS Peripheral Function Register Name Access Watchdog timer 1 (WDT1) WDTM1 Write 2 to 4 <Calculation of number of waits> {(1/fx) × 2/((2 + m)/f )} + 1 fx: Oscillation frequency Watchdog timer 2 (WDT2) WDTM2 Write 3 (fixed) 16-bit timer/event counters 00 to 05 TMC00 to TMC05...
Page 136 CHAPTER 3 CPU FUNCTIONS Remark In the calculation for the number of waits: : CPU clock frequency Set value of bits 2 to 0 of the VSWC register : Internal system clock When f < 16.6 MHz: 0 ≥ 16.6 MHz: 1 When f The digits below the decimal point are truncated if less than (1/ )/(2 + m) or rounded up if larger...
Page 137: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Features 4.1.1 V850ES/KF1 Input-only ports: 8 pins I/O ports: 59 pins Shared with I/O pins of other peripheral functions Input/output can be specified in 1-bit units 4.1.2 V850ES/KG1 Input-only ports: 8 pins I/O ports: 76 pins...
Page 138: Basic Port Configuration
4.2 Basic Port Configuration 4.2.1 V850ES/KF1 The V850ES/KF1 incorporates a total of 67 I/O port pins consisting of ports 0, 3 to 5, 7, 9, CM, CS, CT, and DL (including 8 input-only port pins). The port configuration is shown below.
Page 139: V850Es/Kg1
CHAPTER 4 PORT FUNCTIONS 4.2.2 V850ES/KG1 The V850ES/KG1 incorporates a total of 84 I/O port pins consisting of ports 0, 1, 3 to 5, 7, 9, CM, CS, CT, DH, and DL (including 8 input-only port pins). The port configuration is shown below. Port 0 Port 9 P915...
Page 140: V850Es/Kj1
CHAPTER 4 PORT FUNCTIONS 4.2.3 V850ES/KJ1 The V850ES/KJ1 incorporates a total of 128 I/O port pins consisting of ports 0, 1, 3 to 9, CD, CM, CS, CT, DH, and DL (including 16 input-only port pins). The port configuration is shown below. Port 0 Port 9 P915...
Page 141: Port Configuration
CHAPTER 4 PORT FUNCTIONS 4.3 Port Configuration Table 4-1. Port Configuration (V850ES/KF1) Item Configuration Control register Port mode registers PMn (n = 0, 3 to 5, 7, 9, CM, CS, CT, DL) Pull-up resistor option registers PUn (n = 0, 3 to 5, 9)
Page 142: Port 0
CHAPTER 4 PORT FUNCTIONS 4.3.1 Port 0 Input/output for port 0 can be controlled in 1-bit units. The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have the same number of I/O port pins for port 0. Product I/O Port Pin Count V850ES/KF1 7-bit I/O port...
Page 143 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port 0 register (P0) The port 0 register (P0) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units. After Reset: Undefined Address: FFFFF400H Control of output data (in output mode) (n = 0 to 6) Output 0...
Page 144 CHAPTER 4 PORT FUNCTIONS (c) Port 0 mode control register (PMC0) This is an 8-bit register that specifies the port mode or control mode. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H Address: FFFFF440H PMC0 PMC06 PMC05 PMC04...
Page 145 CHAPTER 4 PORT FUNCTIONS (d) Pull-up resistor option register 0 (PU0) This is an 8-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H Address: FFFFFC40H PU06 PU05 PU04...
Page 146 CHAPTER 4 PORT FUNCTIONS (f) External interrupt rising edge specification register 0 (INTR0) This is an 8-bit register that specifies the rising edge as the detection edge for the external interrupt pin. This register can be read/written in 8-bit or 1-bit units. Caution When switching from the external interrupt function (alternate function) to the port function, edge detection may be performed.
Page 147 CHAPTER 4 PORT FUNCTIONS (3) Block diagram (port 0) Figure 4-1. Block Diagram of P00 and P01 PU0n P-ch PMC0 PMC0n PM0n TOHn output PORT P00/TOH0, P01/TOH1 Output latch (P0n) Address Remarks 1. PU0: Pull-up resistor option register 0 PM0: Port 0 mode register PMC0: Port 0 mode control register Port 0 read signal...
Page 148 CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P02 to P06 PU0n P-ch INTR INTR0 INTR0n INTF INTF0 INTF0n PMC0 PMC0n PM0n PORT P02/NMI, P03/INTP0, Output latch P04/INTP1, (P0n) P05/INTP2, P06/INTP3 Address Noise eliminator NMI, INTP0 to INTP3 input Edge detector Remarks 1.
Page 149: Port 1
4.3.2 Port 1 Port 1 can control input/output in 1-bit units. The number of I/O port pins for port 1 differs according to the product. Product I/O Port Pin Count V850ES/KF1 – V850ES/KG1 2-bit I/O port V850ES/KJ1 2-bit I/O port (1) Port 1 functions (V850ES/KG1, V850ES/KJ1) Port input/output data can be specified in 1-bit units.
Page 150 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port 1 register (P1) Port 1 register (P1) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KG1, V850ES/KJ1 After Reset: Undefined Address: FFFFF402H Control of output data (in output mode) (n = 0, 1)
Page 151 CHAPTER 4 PORT FUNCTIONS (c) Pull-up resistor option register 1 (PU1) This is an 8-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 8-bit or 1-bit units. (i) 850ES/KG1, V850ES/KJ1 After Reset: 00H Address: FFFFFC42H PU11 PU10...
Page 152 CHAPTER 4 PORT FUNCTIONS (3) Block diagram (port 1) Figure 4-3. Block Diagram of P10 and P11 PU1n P-ch PM1n PORT Output latch P10/ANO0, (P1n) P11/ANO1 Address P-ch ANOn output N-ch Remarks 1. PM1: Port 1 mode register RD: Port 1 read signal WR: Port 1 write register 2.
Page 153: Port 3
10-bit I/O port V850ES/KJ1 10-bit I/O port (1) Port 3 functions (V850ES/KF1, V850ES/KG1, V850ES/KJ1) Port input/output data can be specified in 1-bit units. Specification is made by the port 3 register (P3). Port input/output can be specified in 1-bit units.
Page 154 CHAPTER 4 PORT FUNCTIONS Port 3 includes the following alternate functions. Table 4-7. Alternate-Function Pins of Port 3 (V850ES/KF1) Note 1 Pin Name Alternate Function PULL Remark Port 3 TXD0 – RXD0 ASCK0 TI000/TO00 TI001 TI010/TO01 Note 2 Note 3...
Page 155 However, when the higher 8 bits and the lower 8 bits of the P3 register are used as the P3H register and as the P3L register, respectively, this register can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1 After Reset: Undefined...
Page 156 However, when the higher 8 bits and the lower 8 bits of the PM3 register are used as the PM3H register and as the PM3L register, respectively, this register can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1 After Reset: FFFFH...
Page 157 However, when the higher 8 bits and the lower 8 bits of the PMC3 register are used as the PMC3H register and as the PMC3L register, respectively, this register can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1, V850ES/KG1, V850ES/KJ1 After Reset: 0000H...
Page 158 P3n bit = 1 → → → → PF3n bit = 1 → → → → PMC3n bit = 1 (e) Port 3 function control register (PFC3) This is an 8-bit register that specifies control mode 1/control mode 2. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1, V850ES/KG1, V850ES/KJ1 After Reset: 00H Address: FFFFF466H PFC3...
Page 159 Caution An on-chip pull-up resistor can be provided for P3n by a mask option. n = 8, 9: For the mask ROM version of the V850ES/KF1 n = 6 to 9: For the mask ROM versions of the V850ES/KG1 and V850ES/KJ1 User’s Manual U15862EJ3V0UD...
Page 160 CHAPTER 4 PORT FUNCTIONS (3) Block diagram (port 3) Figure 4-4. Block Diagram of P30 P-ch PU30 PMC3 PMC30 PM30 PORT TXD0 output P30/TXD0 Output latch (P30) Address Remark PU3: Pull-up resistor option register 3 PM3: Port 3 mode register PMC3: Port 3 mode control register Port 3 read signal Port 3 write signal...
Page 161 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P31, P32, and P34 PU3n P-ch PMC3 PMC3n PM3n PORT Output latch P31/RXD0, P32/ASCK0, (P3n) P34/TI001 Address RXD0, ASCK0, TI001 input Remarks 1. PU3: Pull-up resistor option register 3 PM3: Port 3 mode register PMC3: Port 3 mode control register Port 3 read signal Port 3 write signal...
Page 162 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P33 and P35 P-ch PU3n PFC3 PFC3n PMC3 PMC3n PM3n PORT TO00, TO01 output P33/TI000/TO00 P35/TI010/TO01 Output latch (P3n) Address TI000, TI010 input Remarks 1. PU3: Pull-up resistor option register 3 PFC3: Port 3 function control register PM3: Port 3 mode register...
Page 163 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P36 and P37 Mask PM3n option P36, P37 PORT Output latch N-ch (P3n) P-ch Medium-voltage Address input buffer Remarks 1. PM3: Port 3 mode register RD: Port 3 read signal WR: Port 3 write signal 2.
Page 164 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P38 and P39 PF3H PF3n PMC3 PMC3n PM3n Mask option P38/SDA0, P39/SCL0 SDA0, SCL0 output PORT N-ch Output latch (P3n) Address SDA0, SCL0 input Remarks 1. PF3H: Port 3 function register H PM3: Port 3 mode register PMC3: Port 3 mode control register...
Page 165: Port 4
CHAPTER 4 PORT FUNCTIONS 4.3.4 Port 4 Port 4 can control input/output in 1-bit units. The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have the same number of I/O port pins for port 4. Product I/O Port Pin Count V850ES/KF1 3-bit I/O port...
Page 166 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port 4 register (P4) The port 4 register (P4) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units. After Reset: Undefined Address: FFFFF408H Control of output data (in output mode) (n = 0 to 2) Output 0...
Page 167 CHAPTER 4 PORT FUNCTIONS (c) Port 4 mode control register (PMC4) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H Address: FFFFF448H PMC4 PMC42 PMC41 PMC40 PMC42 Specification of P42 pin operation mode...
Page 168 CHAPTER 4 PORT FUNCTIONS (e) Pull-up resistor option register 4 (PU4) This is an 8-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H Address: FFFFFC48H PU42 PU41 PU40...
Page 169 CHAPTER 4 PORT FUNCTIONS (3) Block diagram (port 4) Figure 4-9. Block Diagram of P40 P-ch PU40 PMC4 PMC40 PM40 PORT Output latch P40/SI00 (P40) Address SI00 input Remark PU4: Pull-up resistor option register 4 PM4: Port 4 mode register PMC4: Port 4 mode control register Port 4 read signal Port 4 write signal...
Page 170 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P41 P-ch PU41 PF41 PMC4 PMC41 PM41 PORT SO00 output P-ch Output latch P41/SO00 (P41) N-ch Address Remark PU4: Pull-up resistor option register 4 PF4: Port 4 function register PM4: Port 4 mode register PMC4: Port 4 mode control register Port 4 read signal Port 4 write signal...
Page 171 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P42 P-ch PU42 PF42 CSI00 output PMC4 enable signal PMC42 PM42 PORT SCK00 output P-ch Output latch P42/SCK00 (P42) N-ch Address CSI00 input enable signal SCK00 input Remark PU4: Pull-up resistor option register 0 PF4: Port 4 function register PM4: Port 4 mode register...
Page 172: Port 5
CHAPTER 4 PORT FUNCTIONS 4.3.5 Port 5 Port 5 can control input/output in 1-bit units. The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have the same number of I/O port pins for port 5. Product I/O Port Pin Count V850ES/KF1 6-bit I/O port...
Page 173 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port 5 register (P5) The port 5 register (P5) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units. After Reset: Undefined Address: FFFFF40AH Control of output data (in output mode) (n = 0 to 5) Output 0...
Page 174 CHAPTER 4 PORT FUNCTIONS (c) Port 5 mode control register (PMC5) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H Address: FFFFF44AH PMC5 PMC55 PMC54 PMC53 PMC52 PMC51...
Page 175 CHAPTER 4 PORT FUNCTIONS (d) Port 5 function register 5 (PF5) This is an 8-bit register that specifies normal output/N-ch open-drain output. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H Address: FFFFFC6AH PF55 PF54 PF5n Control of normal output/N-ch open-drain output (n = 4, 5) Normal output N-ch open-drain output...
Page 176 CHAPTER 4 PORT FUNCTIONS (e) Port 5 function control register (PFC5) This is an 8-bit register that specifies control mode 1/control mode 2. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H Address: FFFFF46AH PFC5 PFC55 PFC54 PFC53 PFC52...
Page 177 CHAPTER 4 PORT FUNCTIONS (f) Pull-up resistor option register 5 (PU5) This is an 8-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 8-bit or 1-bit units. After Reset: 00H Address: FFFFFC4AH PU55 PU54 PU53...
Page 178 CHAPTER 4 PORT FUNCTIONS (3) Block diagram (port 5) Figure 4-12. Block Diagram of P50, P51, and P53 PU5n P-ch PFC5 PFC5n PMC5 PMC5n PM5n PORT RTP0n output Output latch P50/TI011/RTP00/KR0, (P5n) P51/TI50/RTP01/KR1, P53/SIA0/RTP03/KR3 Address TI011, TI50, SIA0 input KRn input Remarks 1.
Page 179 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P52 P-ch PU52 PFC5 PFC52 PMC5 PMC52 PM52 TO50 output RTP02 output PORT Output latch P52/TO50/RTP02/KR2 (P52) Address KR2 input Remark PU5: Pull-up resistor option register 5 PFC5: Port 5 function control register PM5: Port 5 mode register PMC5: Port 5 mode control register Port 5 read signal...
Page 180 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P54 P-ch PU54 PF54 PFC5 PFC54 PMC5 PMC54 PM54 SOA0 output RTP04 output PORT P-ch Output latch P54/SOA0/RTP04/KR4 (P54) N-ch Address KR4 input Remark PU5: Pull-up resistor option register 5 PF5: Port 5 function register PFC5: Port 5 function control register PM5: Port 5 mode register...
Page 181 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P55 P-ch PU55 PF55 CSIA0 output enable signal PFC5 PFC55 PMC5 PMC55 PM55 SCKA0 output RTP05 output PORT P-ch Output latch (P55) P55/SCKA0/RTP05/KR5 N-ch Address SCKA0 input KR5 input Remark PU5: Pull-up resistor option register 5 PF5: Port 5 function register...
Page 182: Port 6
CHAPTER 4 PORT FUNCTIONS 4.3.6 Port 6 Port 6 can control input/output in 1-bit units. The number of I/O port pins for port 6 differs according to the product. Product I/O Port Pin Count V850ES/KF1 – V850ES/KG1 – V850ES/KJ1 16-bit I/O port (1) Port 6 functions (V850ES/KJ1) Port input/output data can be specified in 1-bit units.
Page 183 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port 6 register (P6) The port 6 register (P6) is a 16-bit register that controls pin level read and output level write. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the P6 register are used as the P6H register and as the P6L register, respectively, this register can be read/written in 8-bit or 1-bit units.
Page 184 CHAPTER 4 PORT FUNCTIONS (b) Port 6 mode register (PM6) This is a 16-bit register that specifies the input mode/output mode. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PM6 register are used as the PM6H register and as the PM6L register, respectively, this register can be read/written in 8-bit or 1-bit units.
Page 185 CHAPTER 4 PORT FUNCTIONS (c) Port 6 mode control register (PMC6) This is a 16-bit register that specifies the port mode/control mode. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PMC6 register are used as the PMC6H register and as the PMC6L register, respectively, this register can be read/written in 8-bit or 1-bit units.
Page 186 CHAPTER 4 PORT FUNCTIONS (d) Port 6 function register (PF6) This is a 16-bit register that specifies normal output/N-ch open-drain output. The PF6 register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PF6 register are used as the PF6H register and as the PF6L register, respectively, this register can be read/written in 8-bit or 1-bit units.
Page 187 CHAPTER 4 PORT FUNCTIONS (f) Pull-up resistor option register 6 (PU6) This is a 16-bit register that specifies the connection of an on-chip pull-up resistor. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PU6 register are used as the PU6H register and as the PU6L register, respectively, this register can be read/written in 8-bit or 1-bit units.
Page 188 CHAPTER 4 PORT FUNCTIONS (3) Block diagram (Port 6) Figure 4-16. Block Diagram of P60 to P65, and P611 P-ch PU6n, PU611 PMC6 PMC6n, PMC611 PM6n, PM611 P60/RTP10, P61/RTP11, RTP1n, TO04 output PORT P62/RTP12, P63/RTP13, Output latch P64/RTP14, P65/RTP15, (P6n, P611) P611/TO04 Address Remarks 1.
Page 189 CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P66, P69, P610, and P612 P-ch PU6n PMC6 PMC6n PM6n PORT P66/SI02, Output latch P69/TI040, P610/TI041, (P6n) P612/TI050 Address SI02, TI040, TI041, TI050 input Remarks 1. PU6: Pull-up resistor option register 6 PM6: Port 6 mode register PMC6: Port 6 mode control register Port 6 read signal...
Page 190 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of P67 P-ch PU67 PF67 PMC6 PMC67 PM67 PORT SO02 output P-ch Output latch P67/SO02 (P67) N-ch Address Remark PU6: Pull-up resistor option register 6 PF6: Port 6 function register PM6: Port 6 mode register PMC6: Port 6 mode control register Port 6 read signal Port 6 write signal...
Page 191 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of P68 P-ch PU68 PF68 CSI02 output PMC6 enable signal PMC68 PM68 PORT SCK02 output P-ch Output latch P68/SCK02 (P68) N-ch Address CSI02 input enable signal SCK02 input Remark PU6: Pull-up resistor option register 6 PF6: Port 6 function register PM6: Port 6 mode register...
Page 192 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of P613 P-ch PU613 PFC6 PFC613 PMC6 PMC613 PM613 PORT TO05 output P613/TI051/TO05 Output latch (P613) Address TI051 input Remark PU6: Pull-up resistor option register 6 PFC6: Port 6 function control register PM6: Port 6 mode register PMC6: Port 6 mode control register Port 6 read signal...
Page 193 CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of P614 and P615 Mask PM61n option P614, P615 PORT N-ch Output latch (P61n) P-ch Medium-voltage Address input buffer Remarks 1. PM6: Port 6 mode register RD: Port 6 read signal WR: Port 6 write signal 2.
Page 194: Port 7
(1) Port 7 functions Port input data read is possible in 1-bit units. Specification is made by the port 7 register (P7). Port 7 includes the following alternate functions. Table 4-12. Alternate-Function Pins of Port 7 (V850ES/KF1, V850ES/KG1) Note Pin Name Alternate Function...
Page 195 CHAPTER 4 PORT FUNCTIONS Table 4-13. Alternate-Function Pins of Port 7 (V850ES/KJ1) Note Pin Name Alternate Function PULL Remark Port 7 ANI0 Input – ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 P710 ANI10 P711 ANI11 P712 ANI12 P713 ANI13 P714 ANI14...
Page 196 (2) Registers (a) Port 7 register (P7) The port 7 register (P7) of the V850ES/KF1 and V850ES/KG1 is an 8-bit register that reads the pin level. This register can be read in 8-bit units. The port 7 register (P7) of the V850ES/KJ1 is a 16-bit register that reads the pin level. This register can be read only in 16-bit units.
Page 197 CHAPTER 4 PORT FUNCTIONS (3) Block diagram (Port 7) Figure 4-22. Block Diagram of P70 to P715 P7n/ANIn ANIn input Remark n = 0 to 15 RD: Port 7 read signal User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 198: Port 8
CHAPTER 4 PORT FUNCTIONS 4.3.8 Port 8 Port 8 controls input/output in 1-bit units. The number of I/O port pins differs according to the product. Product I/O Port Pin Count V850ES/KF1 – V850ES/KG1 – V850ES/KJ1 2-bit I/O port (1) Port 8 function (V850ES/KJ1) Port input/output data can be specified in 1-bit units.
Page 199 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port 8 register (P8) The port 8 register (PM8) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KJ1 After Reset: Undefined Address: FFFFF410H Control of output data (in output mode) (n = 0, 1)
Page 200 CHAPTER 4 PORT FUNCTIONS (c) Port 8 mode control register (PMC8) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KJ1 After Reset: 00H Address: FFFFF450H PMC8 PMC81 PMC80 PMC81...
Page 201 CHAPTER 4 PORT FUNCTIONS (e) Port 8 function control register (PFC8) This is an 8-bit register that specifies control mode 1/control mode 2. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KJ1 After Reset: 00H Address: FFFFF470H PFC8 PFC81 PFC80...
Page 202 CHAPTER 4 PORT FUNCTIONS (3) Block diagram (Port 8) Figure 4-23. Block Diagram of P80 PU80 P-ch PF80 PFC8 PFC80 PMC8 PMC80 PM80 SDA1 output PORT P-ch Output latch (P80) P80/RXD2/SDA1 N-ch Address RXD2 input SDA1 input Remark PU8: Pull-up resistor option register 8 PF8: Port 8 function register PFC8: Port 8 function control register...
Page 203 CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of P81 PU81 P-ch PF81 PFC8 PFC81 PMC8 PMC81 PM81 TXD2 output SCL1 output PORT P-ch Output latch (P81) P81/TXD2/SCL1 N-ch Address SCL1 input Remark PU8: Pull-up resistor option register 8 PF8: Port 8 function register PFC8: Port 8 function control register PM8: Port 8 mode register...
Page 204: Port 9
4.3.9 Port 9 Port 9 controls input/output in 1-bit units. The number of I/O port pins for port 9 differs according to the product. Product I/O Port Pin Count V850ES/KF1 9-bit I/O port V850ES/KG1 16-bit I/O port V850ES/KJ1 16-bit I/O port (1) Port 9 functions Port input/output data can be specified in 1-bit units.
Page 205 CHAPTER 4 PORT FUNCTIONS Port 9 includes the following alternate functions. Table 4-15. Alternate-Function Pins of Port 9 (V850ES/KF1) Note Pin Name Alternate Function PULL Remark Port 9 TXD1/KR6 – RXD1/KR7 TI51/TO51 SI01 SO01 N-ch open-drain output can be specified.
Page 206 However, when the higher 8 bits and the lower 8 bits of the P9 register are used as the P9H register and as the P9L register, respectively, these registers can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1 After Reset: Undefined...
Page 207 However, when the higher 8 bits and the lower 8 bits of the PM9 register are used as the PM9H register and as the PM9L register, respectively, this register can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1 After Reset: FFFFH...
Page 208 CHAPTER 4 PORT FUNCTIONS (i) V850ES/KJ1 After Reset: 0000H Address: FFFFF452H (PMC9, PMC9L), FFFFF453H (PML9H) Note PMC9 (PMC9H PMC915 PMC914 PMC913 PMC99 PMC98 PMC97 PMC96 PMC91 PMC90 (PMC9L) PMC915 Specification of P915 pin operation mode I/O port INTP6 input PMC914 Specification of P914 pin operation mode I/O port INTP5 input...
Page 209 CHAPTER 4 PORT FUNCTIONS (1/2) (ii) V850ES/KG1, V850ES/KJ1 After Reset: 0000H Address: FFFFFF452H (PMC9, PMC9L), FFFFF453H (PMC9H) Note PMC9 (PMC9H PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 PMC99 PMC98 PMC97 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91 PMC90 (PMC9L) PMC915 Specification of P915 pin operation mode I/O port A15/INTP6 I/O PMC914...
Page 210 CHAPTER 4 PORT FUNCTIONS (2/2) PMC97 Specification of P97 pin operation mode I/O port A7/SI01 I/O PMC96 Specification of P96 pin operation mode I/O port/TI51 A6/TO51 output PMC95 Specification of P95 pin operation mode I/O port A5/TI031 I/O PMC94 Specification of P94 pin operation mode I/O port/TI030 input A4/TO03 output PMC93...
Page 211 PFC9 register maintaining the initial value (0), output becomes undefined. Therefore, to set control mode 2 of port 9, set the PFC9n bit to 1 first and then set the PMC9n bit to 1 (n = 0, 1, 6 to 9, 13 to 15) (V850ES/KF1 only). User’s Manual U15862EJ3V0UD...
Page 212 CHAPTER 4 PORT FUNCTIONS (i) V850ES/KF1 After Reset: 0000H Address: FFFFF472H (PFC9, PFC9L), FFFFF473H (PFC9H) Note PFC9 (PFC9H PFC910 PFC910 PFC910 PFC99 PFC98 PFC97 PFC96 PFC91 PFC90 (PFC9L) PFC915 Specification of P915 pin operation mode in control mode INTP6 input...
Page 213 CHAPTER 4 PORT FUNCTIONS (1/2) (ii) V850ES/KG1, V850ES/KJ1 After Reset: 0000H Address: FFFFF472H (PFC9, PFC9L), FFFFF473H (PFC9H) Note PFC9 (PFC9H PFC915 PFC914 PFC913 PFC912 PFC911 PFC910 PFC99 PFC98 (PFC9L) PFC97 PFC96 PFC95 PFC94 PFC93 PFC92 PFC91 PFC90 PFC915 Specification of P915 pin operation mode in control mode A15 output INTP6 input PFC914...
Page 214 CHAPTER 4 PORT FUNCTIONS (2/2) PFC97 Specification of P97 pin operation mode in control mode A7 output SI01 input PFC96 Specification of P96 pin operation mode in control mode A6 output TO51 output PFC95 Specification of P95 pin operation mode in control mode A5 output TI031 input PFC94...
Page 215 However, when the higher 8 bits and the lower 8 bits of the PU9 register are used as the PU9H register and as the PU9L register, respectively, these registers can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1, V850ES/KG1 After Reset: 0000H...
Page 216 Caution When switching from the external interrupt function (alternate function) to the port function, edge detection may be performed. Therefore, set the port mode after setting INTF9n bit = INTR9n bit = 0. (i) V850ES/KF1, V850ES/KG1, V850ES/KJ1 After Reset: 00H Address: FFFFFC13H...
Page 217 CHAPTER 4 PORT FUNCTIONS (3) Block diagram (port 9) Figure 4-25. Block Diagram of P90, P92, P94, and P96 PU9n P-ch PFC9 PFC9n PMC9 PMC9n Output buffer OFF signal PM9n An output TXD1, TO02,TO03, TO51 input PORT Output latch P90/A0/TXD1/KR6, P92/A2/TI020/TO02, (P9n) P94/A4/TI030/TO03,...
Page 218 CHAPTER 4 PORT FUNCTIONS Figure 4-26. Block Diagram of P91 P-ch PU91 PFC9 PFC91 PMC9 PMC91 Output buffer OFF signal PM91 A1 output PORT P91/A1/RXD1/KR7 Output latch (P91) Address RXD1 input KR7 input Remark PU9: Pull-up resistor option register 9 PFC9: Port 9 function control register PM9: Port 9 mode register PMC9: Port 9 mode control register...
Page 219 CHAPTER 4 PORT FUNCTIONS Figure 4-27. Block Diagram of P93, P95, P97, and P910 P-ch PU9n PFC9 PFC9n PMC9 PMC9n Output buffer OFF signal PM9n An output PORT P93/A3/TI021, P95/A5/TI031, P97/A7/SI01, Output latch P910/A10/SIA1 (P9n) Address TI021, TI031, SI01, SIA1 input Remarks 1.
Page 220 CHAPTER 4 PORT FUNCTIONS Figure 4-28. Block Diagram of P98 and P911 P-ch PU9n PF9H PF9n PFC9 PFC9n PMC9 PMC9n Output buffer OFF signal PM9n An output SO01, SOA1 output PORT P-ch Output latch P98/A8/SO01, (P9n) N-ch P911/A11/SOA1 Address Remarks 1. PU9: Pull-up resistor option register 9 PF9H: Port 9 function register H PFC9: Port 9 function control register...
Page 221 CHAPTER 4 PORT FUNCTIONS Figure 4-29. Block Diagram of P99 and P912 P-ch PU9n PF9H PF9n PFC9 PFC9n PMC9 PMC9n A9 output CSI01, CSIA1 output enable signal PM9n An output SCK01, SCKA1 output PORT P-ch Output latch P99/A9/SCK01, (P9n) P912/A12/SCKA1 N-ch Address SCK01, SCKA1 input...
Page 222 CHAPTER 4 PORT FUNCTIONS Figure 4-30. Block Diagram of P913 to P915 P-ch PU9n INTR INTR9H INTR9n INTF INTF9H INTF9n PFC9 PFC9n PMC9 PMC9n Output buffer OFF signal PM9n An output PORT P913/A13/INTP4, P914/A14/INTP5, P915/A15/INTP6 Output latch (P9n) Address Noise eliminator INTP4 to INTP6 input Noise detector Remarks 1.
Page 223: Port Cd
CHAPTER 4 PORT FUNCTIONS 4.3.10 Port CD Port CD can control input/output in 1-bit units. The number of I/O port pins for port CD differs according to the product. Product I/O Port Pin Count V850ES/KF1 – V850ES/KG1 – V850ES/KJ1 4-bit I/O port (1) Port CD functions (V850ES/KJ1) Port input/output data can be specified in 1-bit units.
Page 224 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port CD register (PCD) The port CD register (PCD) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KJ1 After Reset: Undefined Address: FFFFF00EH PCD3...
Page 225 CHAPTER 4 PORT FUNCTIONS (b) Port CD mode register (PMCD) This is an 8-bit register that specifies the input mode/output mode. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KJ1 After Reset: FFH Address: FFFFF02EH PMCD PMCD3 PMCD2 PMCD1 PMCD0...
Page 226 CHAPTER 4 PORT FUNCTIONS (3) Block diagram (Port CD) Figure 4-31. Block Diagram of PCD0 to PCD3 PMCD PMCDn PORT PCD0, Output latch PCD1, (PCDn) PCD2, PCD3 Address Remarks 1. PMCD: Port CD mode register Port CD read signal Port CD write signal 2.
Page 227: Port Cm
Port mode/control mode (alternate functions) can be specified 1-bit units. Specification is made by the port CM mode control register (PMCCM). Port CM includes the following alternate functions. Table 4-19. Alternate-Function Pins of Port CM (V850ES/KF1, V850ES/KG1) Note Pin Name...
Page 228 (a) Port CM register (PCM) The port CM register (PCM) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1, v850ES/KG1 After Reset: Undefined Address: FFFFF00CH...
Page 229 CHAPTER 4 PORT FUNCTIONS (b) Port CM mode register (PMCM) This is an 8-bit register that specifies the input mode/output mode. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1, V850ES/KG1 After Reset: FFH Address: FFFFF02CH PMCM...
Page 230 CHAPTER 4 PORT FUNCTIONS (c) Port CM mode control register (PMCCM) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1, V850ES/KG1, V850ES/KJ1 After Reset: 00H Address: FFFFF04CH PMCCM...
Page 231 CHAPTER 4 PORT FUNCTIONS (3) Block diagram (Port CM) Figure 4-32. Block Diagram of PCM0 and PCM3 PMCCM PMCCMn PMCM PMCMn PORT Output latch PCM0/WAIT, PCM3/HLDRQ (PCMn) Address WAIT, HLDRQ input Remarks 1. PMCM: Port CM mode register PMCCM: Port CM mode control register Port CM read signal Port CM write signal 2.
Page 232 CHAPTER 4 PORT FUNCTIONS Figure 4-33. Block Diagram of PCM1 and PCM2 PMCCM PMCCMn PMCM PMCMn CLKOUT, HLDAK output signal PORT PCM1/CLKOUT, PCM2/HLDAK Output latch (PCMn) Address Remarks 1. PMCM: Port CM mode register PMCCM: Port CM mode control register Port CM read signal Port CM write signal 2.
Page 233 CHAPTER 4 PORT FUNCTIONS Figure 4-34. Block Diagram of PCM4 and PCM5 PMCM PMCMn PORT Output latch PCM4, PCM5 (PCMn) Address Remarks 1. PMCM: Port CM mode register Port CM read signal Port CM write signal 2. n = 4, 5 User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 234: Port Cs
Port mode/control mode (alternate functions) can be specified 1-bit units. Specification is made by the port CS mode control register (PMCCS). Port CS includes the following alternate functions. Table 4-21. Alternate-Function Pins of Port CS (V850ES/KF1, V850ES/KG1) Note Pin Name...
Page 235 (a) Port CS register (PCS) The port CS register (PCS) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1, V850ES/KG1 After Reset: Undefined Address: FFFFF008H...
Page 236 CHAPTER 4 PORT FUNCTIONS (b) Port CS mode register (PMCS) This is an 8-bit register that specifies the input mode/output mode. This register can be written in 8-bit or 1-bit units. (i) V850ES/KF1, V850ES/KG1 After Reset: FFH Address: FFFFF028H PMCS...
Page 237 CHAPTER 4 PORT FUNCTIONS (c) Port CS mode control register (PMCCS) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1, V850ES/KG1 After Reset: 00H Address: FFFFF048H PMCCS...
Page 238 CHAPTER 4 PORT FUNCTIONS (3) Block diagram (port CS) Figure 4-35. Block Diagram of PCS0 to PCS3 PMCCS PMCCSn Output buffer OFF signal PMCS PMCSn CSn output PORT PCS0/CS0, PCS1/CS1, PCS2/CS2, Output latch PCS3/CS3 (PCSn) Address Remarks 1. PMCS: Port CS mode register PMCCS: Port CS mode control register Port CS read signal Port CS write signal...
Page 239 CHAPTER 4 PORT FUNCTIONS Figure 4-36. Block Diagram of PCS4 to PCS7 PMCS PMCSn PORT PCS4, PCS5, Output latch PCS6, (PCSn) PCS7 Address Remarks 1. PMCS: Port CS mode register 2. n = 4 to 7 User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 240: Port Ct
Port mode/control mode (alternate functions) can be specified 1-bit units. Specification is made by the port CT mode control register (PMCCT). Port CT includes the following alternate functions. Table 4-23. Alternate-Function Pins of Port CT (V850ES/KF1, V850ES/KG1) Note Pin Name...
Page 241 (a) Port CT register (PCT) The port CT register (PCT) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1, V850ES/KG1 After Reset: Undefined Address: FFFFF00AH...
Page 242 CHAPTER 4 PORT FUNCTIONS (b) Port CT mode register (PMCT) This is an 8-bit register that specifies the input mode/output mode. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1, V850ES/KG1 After Reset: FFH Address: FFFFF02AH PMCT...
Page 243 CHAPTER 4 PORT FUNCTIONS (c) Port CT mode control register (PMCCT) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KF1, V850ES/KG1, V850ES/KJ1 After Reset: 00H Address: FFFFF04AH PMCCT...
Page 244 CHAPTER 4 PORT FUNCTIONS (3) Block diagram (port CT) Figure 4-37. Block Diagram of PCT0, PCT1, PCT4, and PCT6 PMCCT PMCCTn Output buffer OFF signal PMCT PMCTn WR0, WR1, RD, PORT PCT0/WR0, ASTB output PCT1/WR1, PCT4/RD, Output latch PCT6/ASTB (PCTn) Address Remarks 1.
Page 245 CHAPTER 4 PORT FUNCTIONS Figure 4-38. Block Diagram of PCT2, PCT3, PCT5, and PCT7 PMCT PMCTn PORT PCT2, Output latch PCT3, (PCTn) PCT5, PCT7 Address Remarks 1. PMCT: Port CT mode register Port CM read signal Port CM write signal 2.
Page 246: Port Dh
4.3.14 Port DH Port DH can control input/output in 1-bit units. The number of I/O port pins for port DH differs according to the product. Product I/O Port Pin Count V850ES/KF1 – V850ES/KG1 6-bit I/O port V850ES/KJ1 8-bit I/O port (1) Port DH functions (V850ES/KG1, V850ES/KJ1) Port input/output data can be specified in 1-bit units.
Page 247 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port DH register (PDH) The port DH register (PDH) is an 8-bit register that controls pin level read and output level write. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KG1 After Reset: Undefined Address: FFFFF006H PDH5...
Page 248 CHAPTER 4 PORT FUNCTIONS (b) Port DH mode register (PMDH) This is an 8-bit register that specifies the input mode/output mode. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KG1 After Reset: FFH Address: FFFFF026H PMDH PMDH5 PMDH4 PMDH3 PMDH2...
Page 249 CHAPTER 4 PORT FUNCTIONS (c) Port DH mode control register (PMCDH) This is an 8-bit register that specifies the port mode/control mode. This register can be read/written in 8-bit or 1-bit units. (i) V850ES/KG1 After Reset: 00H Address: FFFFF046H PMCDH PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 PMCDHn Specification of PDHn pin operation mode (n = 0 to 5)
Page 250 CHAPTER 4 PORT FUNCTIONS (3) Block diagram (Port DH) Figure 4-39. Block Diagram of PDH0 to PDH7 PMCDH PMCDHn Output buffer OFF signal PMDH PMDHn PDH0/A16, PDH1/A17, Am output PDH2/A18, PORT PDH3/A19, PDH4/A20, PDH5/A21, Output latch PDH6/A22, (PCHn) PDH7/A23 Address Remarks 1.
Page 251: Port Dl
4.3.15 Port DL Port DL can control input/output in 1-bit units. The number of I/O port pins for port 1 differs according to the product. Product I/O Port Pin Count V850ES/KF1 16-bit I/O port V850ES/KG1 16-bit I/O port V850ES/KJ1 16-bit I/O port (1) Port DL functions Port input/output data can be specified in 1-bit units.
Page 252 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port DL register (PDL) The port DL register (PDL) is an 16-bit register that controls pin level read and output level write. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PDL register are used as the PDLH register and as the PDLL register, respectively, these registers can be read/written in 8-bit or 1-bit units.
Page 253 CHAPTER 4 PORT FUNCTIONS (b) Port DL mode register (PMDL) This is a 16-bit register that specifies the input mode/output mode. This register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the PMDL register are used as the PMDLH register and as the PMDLL register, respectively, these registers can be read/written in 8-bit or 1-bit units.
Page 254 CHAPTER 4 PORT FUNCTIONS (3) Block diagram (Port DL) Figure 4-40. Block Diagram of PDL0 to PDL15 PMCDL PMCDLn Output enable signal for address/data bus Output buffer OFF signal PMDL PDL0/AD0, PDL1/AD1, PMDLn PDL2/AD2, PDL3/AD3, PDL4/AD4, PDL5/AD5, ADn output PDL6/AD6, PORT PDL7/AD7, PDL8/AD8,...
Page 255 Table 4-28. Settings When Port Pins Are Used for Alternate Functions (1/7) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) PMCn Register PFCn Register Function Name TOH0 Output P00 = Setting not required...
Page 256 Table 4-28. Settings When Port Pins Are Used for Alternate Functions (2/7) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) Function Name PMCn Register PFCn Register TI011 Input P50 = Setting not required...
Page 257 Table 4-28. Settings When Port Pins Are Used for Alternate Functions (3/7) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) Function Name PMCn Register PFCn Register RTP10 Output P60 = Setting not required...
Page 258 Table 4-28. Settings When Port Pins Are Used for Alternate Functions (4/7) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) Function Name PMCn Register PFCn Register ANI0 Input P70 = Setting not required...
Page 259 Table 4-28. Settings When Port Pins Are Used for Alternate Functions (5/7) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) Function Name PMCn Register PFCn Register Output P90 = Setting not required PM90 = Setting not required...
Page 260 Table 4-28. Settings When Port Pins Are Used for Alternate Functions (6/7) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) Function Name PMCn Register PFCn Register P910 Output P910 = Setting not required...
Page 261 Table 4-28. Settings When Port Pins Are Used for Alternate Functions (7/7) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) Function Name PMCn Register PFCn Register PDH0 Output PDH0 = Setting not required...
Page 262: Port Function Operation
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operation Port operation differs according to the input/output mode setting, as follows. 4.4.1 Write operation to I/O port (1) In output mode A value is written to the output latch using the transfer instruction, and the contents of the output latch are output from the pin.
Page 263: Chapter 5 Bus Control Function
CHAPTER 5 BUS CONTROL FUNCTION The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 5.1 Features Output is selectable from a multiplex bus with a minimum of 3 bus cycles and a separate bus with a minimum of...
Page 264 Input Bus hold control HLDAK PCM2 Output (2) Separate bus mode Note that the separate bus mode is not available in the V850ES/KF1. Table 5-4. V850ES/KG1 Bus Control Pins Bus Control Pin Alternate-Function Pin Function AD0 to AD15 PDL0 to PDL15...
Page 265: Pin Status When Internal Rom, Internal Ram, Or On-Chip Peripheral I/O Is Accessed
Note When an on-chip peripheral I/O is accessed, the address bus outputs the address of the on-chip peripheral I/O that is accessed. 5.2.2 Pin status in each operation mode For the pin status of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 in each operation mode, refer to 2.2 Pin Status. User’s Manual U15862EJ3V0UD...
Page 266: Memory Block Function
The 64 MB memory space is divided into memory blocks of (lower) 2 MB and 64 KB. The programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units. Figure 5-1. Data Memory Map (V850ES/KF1) 3FFFFFFH 3FFFFFFH...
Page 267 CHAPTER 5 BUS CONTROL FUNCTION (2) V850ES/KG1 The 64 MB memory space is divided into memory blocks of (lower) 2 MB and 2 MB. The programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units.
Page 268 CHAPTER 5 BUS CONTROL FUNCTION (3) V850ES/KJ1 The 64 MB memory space is divided into memory blocks of (lower) 2 MB, 2 MB, 4 MB, and 8 MB. The programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units.
Page 269: Chip Select Control Function
• Separate bus mode These two modes can be selected by using the external bus interface mode control register (EXIMC). Remark Only the multiplex bus mode is available in the V850ES/KF1. (1) External bus interface mode control register (EXIMC) This register can be read or written in 8-bit or 1-bit units.
Page 270: Bus Access
The external memory area of the V850ES/KJ1 (0100000H to 0FFFFFFH) is selected by CS0 to CS3. The external memory area of the V850ES/KG1 (0100000H to 03FFFFFH) is selected by CS0 and CS1. The external memory area of the V850ES/KF1 (0100000H to 010FFFFH and 0200000H to 020FFFFH) is selected by CS0 and CS1.
Page 271: Access By Bus Size
CHAPTER 5 BUS CONTROL FUNCTION 5.5.3 Access by bus size The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 access the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to 16 bits.
Page 272 CHAPTER 5 BUS CONTROL FUNCTION (2) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) First access Second access Address Address Address 2n + 1 2n + 1 2n + 2 Halfword...
Page 273 CHAPTER 5 BUS CONTROL FUNCTION (3) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Second access Address Address 4n + 1 4n + 3 4n + 2 Word data External Word data External data bus data bus...
Page 274 CHAPTER 5 BUS CONTROL FUNCTION (a) 16-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External Word data External data bus data bus...
Page 275 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Second access Third access Fourth access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External Word data External Word data...
Page 276 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Third access Fourth access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External Word data...
Page 277: Wait Function
Note The DW32 to DW30 and DW22 to DW20 bits are only valid in the V850ES/KJ1. Changing these bits has no effect on the operation in the V850ES/KF1 and V850ES/KG1. Caution Be sure to clear bits 15, 11, 7, and 3 to 0.
Page 278: External Wait Function
CHAPTER 5 BUS CONTROL FUNCTION 5.6.2 External wait function To synchronize an extremely slow external device, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). Access to each area of the internal ROM, internal RAM, and on-chip peripheral I/O is not subject to control by the external wait function, in the same manner as the programmable wait function.
Page 279: Relationship Between Programmable Wait And External Wait
CHAPTER 5 BUS CONTROL FUNCTION 5.6.3 Relationship between programmable wait and external wait Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WAIT pin. The number of wait cycles is determined by the side with the greatest number of cycles.
Page 280: Programmable Address Wait Function
Note The AHW3, AHW2, ASW3, and ASW2 bits are only valid in the V850ES/KJ1. Changing these bits has no effect on the operation in the V850ES/KF1 and V850ES/KG1. Caution Be sure to set bits 15 to 8 to 1. User’s Manual U15862EJ3V0UD...
Page 281: Idle State Insertion Function
Note The BC31 and BC21 bits are only valid in the V850ES/KJ1. Changing these bits has no effect on the operation in the V850ES/KF1 and V850ES/KG1. Caution Be sure to set bits 15, 13, 11, and 9 to 1, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to 0.
Page 282: Bus Hold Function
CHAPTER 5 BUS CONTROL FUNCTION 5.8 Bus Hold Function 5.8.1 Functional outline The HLDAK and HLDRQ functions are valid if the PCM2 and PCM3 pins are set in the control mode. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status).
Page 283: Bus Hold Procedure
CHAPTER 5 BUS CONTROL FUNCTION 5.8.2 Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited Normal status <3> End of current bus cycle <4> Shift to bus idle status. <5>...
Page 284: Bus Priority
ROM area to the external memory area. 5.10.2 Data space The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have an address misalign function. With this function, data can be placed at all addresses, regardless of the format of the data (word data or halfword data).
Page 285: Bus Timing
CHAPTER 5 BUS CONTROL FUNCTION 5.11 Bus Timing Figure 5-6. Multiplex Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT A23 to A16 ASTB CS3 to CS0 WAIT AD15 to AD0 Idle state Programmable External wait wait 8-bit access Odd address Even address AD15 to AD8...
Page 286 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-8. Multiplex Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT A23 to A16 ASTB CS3 to CS0 WAIT AD15 to AD0 WR1, WR0 Programmable External wait wait 8-bit access Odd address Even address AD15 to AD8 Active Undefined...
Page 287 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-10. Multiplex Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access) Note Note CLKOUT HLDRQ HLDAK A23 to A16 Undefined Undefined Undefined Undefined AD15 to AD0 ASTB CS3 to CS0 1111 1111 Note This idle state (TI) does not depend on the BCC register settings. Remarks 1.
Page 288 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-11. Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT CS3 to CS0 WAIT A23 to A0 AD15 to AD0 External Programmable Idle state wait wait 8-bit access Odd address Even address AD15 to AD8 Active –...
Page 289 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-13. Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT CS3 to CS0 WAIT A23 to A0 WR1, WR0 AD15 to AD0 Programmable External wait wait 8-bit access Odd address Even address AD15 to AD8 Active Undefined...
Page 290 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-15. Separate Bus Hold Timing (Bus Size: 8 Bits, Write) íç íç CLKOUT HLDRQ HLDAK A23 to A0 Undefined Undefined AD7 to AD0 WR1, WR0 CS3 to CS0 1111 1111 Note This idle state (TI) does not depend on the BCC register settings. Remark The broken lines indicate high impedance.
Page 291: Cautions
CHAPTER 5 BUS CONTROL FUNCTION 5.12 Cautions With the external bus function, signals may not be output at the correct timing under the following conditions. <Operating conditions> Multiplex bus mode <1> CLKOUT asynchronous (2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ BV ≤...
Page 292: Chapter 6 Clock Generation Function
CHAPTER 6 CLOCK GENERATION FUNCTION 6.1 Overview The following clock generation functions are available. Main clock oscillator • f = 2 to 2.5 MHz (REGC = V = 2.7 to 5.5 V, in PLL mode) • f = 2 to 5 MHz (REGC = V = 4.5 to 5.5 V, in PLL mode) •...
Page 293: Configuration
CHAPTER 6 CLOCK GENERATION FUNCTION 6.2 Configuration Figure 6-1. Clock Generator FRC bit Watch timer clock, Subclock watchdog timer clock oscillator /2 to f Watch timer clock Prescaler 3 IDLE mode IDLE control IDLE mode PLLON bit MFRC bit CK2 to CK0 bits CLS bit, CK3 bit IDLE Main clock...
Page 294 CHAPTER 6 CLOCK GENERATION FUNCTION (4) Prescaler 1 This prescaler generates the clock (f to f /1024) to be supplied to the following on-chip peripheral functions: TM00 to TM05, TM50, TM51, TMH0, TMH1, CSI00 to CSI02, CSIA0, CSIA1, UART0 to UART2, I C0, I ADC, DAC, and WDT2 (5) Prescaler 2...
Page 295: Control Registers
CHAPTER 6 CLOCK GENERATION FUNCTION 6.3 Control Registers (1) Processor clock control register (PCC) The processor clock control register (PCC) is a special register. Data can be written to this register only in combination of specific sequences (refer to 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units.
Page 296 CHAPTER 6 CLOCK GENERATION FUNCTION (2/2) Clock selection (f /8 (default value) × Setting prohibited × × × Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits of the PCC register) while CLKOUT is being output. 2.
Page 297 CHAPTER 6 CLOCK GENERATION FUNCTION (b) Example of setting subclock operation → → → → main clock operation <1> MCK ← 0: Main clock oscillation starts. <2> Insert wait cycles by program and wait until the oscillation of the main clock has been stabilized. <3>...
Page 298 CHAPTER 6 CLOCK GENERATION FUNCTION (3) Power save mode register (PSMR) This is an 8-bit register that controls the operation status in the power save mode and the clock operation. This register can be read or written in 8-bit or 1-bit units. RESET input clears this register to 00H.
Page 299: Operation
CHAPTER 6 CLOCK GENERATION FUNCTION 6.4 Operation 6.4.1 Operation of each clock The following table shows the operation status of each clock. Table 6-1. Operation Status of Each Clock CLK bit = 0, MCK bit = 0 CLS bit = 1, CLS bit = 1, MCK bit = 0 MCK bit = 1...
Page 300: Pll Function
CHAPTER 6 CLOCK GENERATION FUNCTION 6.5 PLL Function 6.5.1 Overview The PLL function is used to output the operating clock of the CPU and peripheral macro at a frequency 4 times higher than the oscillation frequency, and select the clock-through mode. When PLL function is used: Input clock = 2 to 5 MHz (f : 8 to 20 MHz) (usable voltage: V...
Page 301: Usage
CHAPTER 6 CLOCK GENERATION FUNCTION 6.5.3 Usage (1) To use PLL • After the RESET has been released, the PLL operates (PLLON = 1), but because the default mode is the clock-through mode (SELPLL = 0), select the PLL mode (SELPLL = 1). •...
Page 302: Chapter 7 16-Bit Timer/Event Counters 00 To 05
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 The number of 16-bit timer/event counter 00 to 05 channels incorporated differs as follows depending on the product. Product Name V850ES/KF1 V850ES/KG1 V850ES/KJ1 Number of channels 2 channels 4 channels 6 channels...
Page 303: Configuration
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 7.2 Configuration 16-bit timer/event counters 00 to 05 consist of the following hardware. Table 7-1. Configuration of 16-Bit Timer/Event Counters 00 to 05 Item Configuration 16 bits × 1 × 6 channels (TM0n) Timer/counters 16-bit timer capture/compare register: 16 bits ×...
Page 304 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-1. Block Diagram of 16-Bit Timer/Event Counter 0n Internal bus Capture/compare control CRC0n2CRC0n1 CRC0n0 register 0n (CRC0n) INTTM0n0 16-bit timer capture/compare Tl0n1 register 0n0 (CR0n0) Match Note Count clock 16-bit timer counter 0n Clear (TM0n) Output...
Page 305 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (2) 16-bit timer capture/compare register 0n0 (CR0n0) The CR0n0 register is a 16-bit register that combines capture register and compare register functions. Bit 0 (CRC0n0) of the capture/compare control register (CRC0n) is used to set whether to use the CR0n0 register as a capture register or as a compare register.
Page 306 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Cautions 1. Set a value other than 0000H to the CR0n0 register in the mode in which clear & start occurs upon a match of the values of the TM0n register and CR0n0 register. However, if 0000H is set to the CR0n0 register in the free-running mode or the TI0n0 valid edge clear mode, an interrupt request (INTTM0n0) is generated after an overflow (FFFFH).
Page 307 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (3) 16-bit timer capture/compare register 0n1 (CR0n1) The CR0n1 register is a 16-bit register that combines capture register and compare register functions. Bit 2 (CRC0n2) of the CRC0n register is used to set whether to use the CR0n1 register as a capture register or as a compare register.
Page 308: Control Registers
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 7.3 Control Registers The registers that control 16-bit timer/event counters 00 to 05 are as follows. • 16-bit timer mode control register 0n (TMC0n) • Capture/compare control register 0n (CRC0n) • 16-bit timer output control register 0n (TOC0n) •...
Page 309 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 After reset: 00H Address: FFFFF606H, FFFFF616H, FFFFF626H FFFFF636H, FFFFF646H, FFFFF656H <0> TMC0n TMC0n3 TMC0n2 TMC0n1 OVF0n (n = 0 to 5 Selection of Selection of TO0n Generation of TMC0n3 TMC0n2 TMC0n1 m = 4, 5) operation mode output timing interrupt...
Page 310 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (2) Capture/compare control register 0n (CRC0n) CRC0n controls the operation of 16-bit timer capture/compare registers 0n0 and 0n1 (CR0n0 and CRC0n1). The CRC0n register is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears CRC0n to 00H.
Page 311 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 After reset: 00H Address: FFFFF609H, FFFFF619H, FFFFF629H FFFFF639H, FFFFF649H, FFFFF659H Note 1 Note 1 TOC0n OSPT0m OSPE0m TOC0n4 LVS0n LVR0n TOC0n1 TOE0n (n = 0 to 5 m = 0, 1, 4, 5 Note 1 OSPT0m Control of output trigger for one-shot pulse by software...
Page 312 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (4) Prescaler mode register 0n (PRM0n) This register sets the count clock of 16-bit timer counter 0n (TM0n) and the valid edge of the TI0n0 and TI0n1 pin inputs. The PRM0n register is set by an 8-bit memory manipulation instruction. RESET input clears PRM0n to 00H.
Page 313 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (a) Prescaler mode register 00 (PRM00) After reset: 00H Address: FFFFF607H PRM00 ES011 ES010 ES001 ES000 PRM001 PRM000 ES011 ES010 Selection of valid edge of TI001 Falling edge Rising edge Setting prohibited Both rising and falling edges ES001 ES000...
Page 314 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (b) Prescaler mode register 01 (PRM01) After reset: 00H Address: FFFFF617H PRM01 ES111 ES110 ES101 ES100 PRM011 PRM010 ES111 ES110 Selection of valid edge of TI0n1 Falling edge Rising edge Setting prohibited Both rising and falling edges ES101 ES100...
Page 315 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (c) Prescaler mode register 02 (PRM02) After reset: 00H Address: FFFFF627H PRM02 ES211 ES210 ES201 ES200 PRM021 PRM020 ES211 ES210 Selection of valid edge of TI021 Falling edge Rising edge Setting prohibited Both rising and falling edges ES201 ES200...
Page 316 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (d) Prescaler mode register 03 (PRM03) After reset: 00H Address: FFFFF637H PRM03 ES311 ES310 ES301 ES300 PRM031 PRM030 ES311 ES310 Selection of valid edge of TI031 Falling edge Rising edge Setting prohibited Both rising and falling edges ES301 ES300...
Page 317 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (e) Prescaler mode register 04 (PRM04) After reset: 00H Address: FFFFF647H PRM04 ES411 ES410 ES401 ES400 PRM041 PRM040 ES411 ES410 Selection of valid edge of TI041 Falling edge Rising edge Setting prohibited Both rising and falling edges ES401 ES400...
Page 318 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (f) Prescaler mode register 05 (PRM05) After reset: 00H Address: FFFFF657H PRM05 ES511 ES510 ES501 ES500 PRM051 PRM050 ES511 ES510 Selection of valid edge of TI051 Falling edge Rising edge Setting prohibited Both rising and falling edges ES501 ES500...
Page 319: Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 7.4 Operation 7.4.1 Operation as interval timer (16 bits) 16-bit timer/event counter 0n can be made to operate as an interval timer by setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-2 (n = 0 to 5). Setting procedure The basic operation setting procedure is as follows.
Page 320 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-2. Control Register Setting Contents During Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears & starts upon match between TM0n and CR0n0 (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CRC0n...
Page 321 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-4. Timing of Interval Timer Operation Count clock TM0n count value 0000H 0001H 0000H 0001H 0000H 0001H Count start Clear Clear CR0n0 INTTM0n0 Interrupt acknowledgment Interrupt acknowledgment Interval time Interval time Interval time Remarks 1.
Page 322: Ppg Output Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 7.4.2 PPG output operation 16-bit timer/event counter 0n can be used for PPG (Programmable Pulse Generator) output by setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 7-5. Setting procedure The basic operation setting procedure is as follows.
Page 323 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-5. Control Register Settings in PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts upon match between TM0n and CR0n0 (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 ×...
Page 324 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-6. Configuration of PPG Output 16-bit capture/compare register 0n0 (CR0n0) Clear Note Count clock 16-bit timer counter 0n (TM0n) circuit Noise TI0k0 eliminator TO0n 16-bit capture/compare register 0n1 (CR0n1) Note The count clock is set by the PRM0n register. Remarks 1.
Page 325 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-7. PPG Output Operation Timing Count clock 0000H 0001H 0000H 0001H TM0n count value Count starts Clear Value loaded to CR0n0 Value loaded to CR0n1 TO0n Pulse width: (M + 1) × t 1 cycle: (N + 1) ×...
Page 326: Pulse Width Measurement
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 7.4.3 Pulse width measurement The 16-bit timer counter (TM0n) can be used to measure the pulse widths of the signals input to the TI0n0 and TI0n1 pins. Measurement can be carried out with the TM0n register used as a free-running counter or by restarting the timer in synchronization with the edge of the signal input to the TI0n0 pin.
Page 327 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-8. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Free-running mode (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CRC0n CR0n0 used as compare register...
Page 328 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-10. Timing of Pulse Width Measurement with Free-Running Counter and One Capture Register (with Both Edges Specified) Count clock TM0n count value 0000H 0001H D0 D0 + 1 D1 + 1 FFFFH 0000H TI0n0 pin input...
Page 329 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (2) Measurement of two pulse widths with free-running counter The pulse widths of two signals respectively input to the TI0n0 pin and the TI0n1 pin can be simultaneously measured when 16-bit timer counter 0n (TM0n) is used as a free-running counter (refer to Figure 7-11). When the edge specified by bits 4 and 5 (ESn00, ESn01) of prescaler mode register 0n (PRM0n) is input to the TI0n0 pin, the value of the TM0n register is loaded to 16-bit timer capture/compare register 0n1 (CR0n1) and an external interrupt request signal (INTTM0n1) is set.
Page 330 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 • Capture operation (free-running mode) The following figure illustrates the operation of the capture register when the capture trigger is input. Figure 7-12. CR0n1 Capture Operation with Rising Edge Specified Count clock TM0n n –...
Page 331 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0n (TM0n) is used as a free-running counter (refer to Figure 7-14), the pulse width of the signal input to the TI0n0 pin can be measured. When the edge specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register 0n (PRM0n) is input to the TI0n0 pin, the value of the TM0n register is loaded to 16-bit timer capture/compare register 0n1 (CR0n1) and an external interrupt request signal (INTTM0n1) is set.
Page 332 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-15. Timing of Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock 0000H 0001H D0 + 1 D1 D1 + 1 FFFFH 0000H D2 + 1 TM0n count value TI0n0 pin input Value loaded to CR0n1...
Page 333 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-16. Control Register Settings for Pulse Width Measurement by Restarting (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts at valid edge of TI0n0 pin (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CRC0n...
Page 334: Operation As External Event Counter
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 7.4.4 Operation as external event counter Setting procedure The basic operation setting procedure is as follows. <1> Set the pins to the TI0n0 pin mode (see CHAPTER 4 PORT FUNCTIONS). <2> Set the CRC0n register (see Figure 7-18 for the setting value). <3>...
Page 335 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-18. Control Register Settings in External Event Counter Mode (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts on match between TM0n and CR0n0 (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CRC0n...
Page 336 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-19. Configuration of External Event Counter 16-bit timer capture/compare register 0n0 (CR0n0) Match INTTM0n0 Clear Note Count clock 16-bit timer counter 0n OVF0n (TM0n) Noise fxx/4 eliminator 16-bit timer capture/compare TI0n0 valid edge register 0n1 (CR0n1) Internal bus Note Set with the PRM0n register.
Page 337: Square-Wave Output Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 7.4.5 Square-wave output operation Setting procedure The basic operation setting procedure is as follows. <1> Set the count clock using the PRM0n register. <2> Set the CRC0n register (see Figure 7-21 for the setting value). <3>...
Page 338 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-21. Control Register Settings in Square-Wave Output Mode (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts upon match between TM0n and CR0n0 (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CRC0n CR0n0 used as compare register...
Page 339 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-22. Timing of Square-Wave Output Operation Count clock TM0n count value 0000H 0001H 0002H N – 1 0000H 0001H 0002H N – 1 0000H CR0n0 INTTM0n0 TO0n pin output Remark n = 0 to 5 User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 340: One-Shot Pulse Output Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 7.4.6 One-shot pulse output operation The one-shot pulse output is valid only for 16-bit timer/event counters 00, 01, 04, and 05. 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI0k0 pin input).
Page 341 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-23. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 0m (TMC0m) TMC0m3 TMC0m2 TMC0m1 OVF0m TMC0m Free-running mode (b) Capture/compare control register 0m (CRC0m) CRC0m2 CRC0m1 CRC0m0 CRC0m CR0m0 used as compare register...
Page 342 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-24. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC0m to 0CH (TM0m count starts) Count clock TM0m count 0000H 0001H N + 1 0000H N – 1 M – 1 M + 1 M + 2 CR0m1 set value CR0m0 set value...
Page 343 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-25. Control Register Settings for One-Shot Pulse Output with External Trigger (a) 16-bit timer mode control register 0k (TMC0k) TMC0k3 TMC0k2 TMC0k1 OVF0k TMC0k Clears and starts at valid edge of TI0k0 pin (b) Capture/compare control register 0k (CRC0k) CRC0k2 CRC0k1 CRC0k0...
Page 344 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 Figure 7-26. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) Set TMC0k to 08H (TM0k count starts) Count clock TM0k count value 0000H 0001H 0000H N + 1 N + 2 M –...
Page 345: Cautions
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 7.4.7 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because 16-bit timer counter 0n (TM0n) is started asynchronously to the count pulse. Figure 7-27.
Page 346 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (4) Setting valid edge Before setting the valid edge of the TI0n0 pin, stop the timer operation by setting bits 2 and 3 (TMC0n2 and TMC0n3) of 16-bit timer mode control register 0n to 0, 0. Set the valid edge by using bits 4 and 5 (ESn00 and ESn01) of prescaler mode register 0n (PRM0n).
Page 347 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (6) Operation of OVF0n flag (a) Setting of OVF0n flag The OVF0n flag is set to 1 in the following case in addition to when the TM0n register overflows. Select the mode in which clear & start occurs upon match between the TM0n register and the CR0n0 register.
Page 348 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (8) Timer operation (a) CR0n1 register capture Even if 16-bit timer counter 0n (TM0n) is read, the read data cannot be captured into 16-bit timer capture/compare register 0n1 (CR0n1). (b) TI0n0, TI0n1 pin acknowledgement Regardless of the CPU’s operation mode, if the timer is stopped, signals input to the TI0n0 and TI0n1 pins are not acknowledged.
Page 349 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05 (10) Compare operation (a) When overwriting CR0n1 register during timer operation in PPG output mode When overwriting 16-bit timer capture/compare register 0n1 (CR0n1) while the timer is operating, if the new value is close to and larger than the timer value, match interrupt request generation may not be performed normally.
Page 350: Chapter 8 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Two 8-bit timer/event counter 50 and 51 channels are incorporated in each product. Product Name V850ES/KF1 V850ES/KG1 V850ES/KJ1 Number of channels 2 channels (TM50, TM51) 8.1 Functions 8-bit timer/event counter 5n has the following two modes (n = 0, 1).
Page 351: Configuration
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-1. Block Diagram of 8-Bit Timer/Event Counters 50 and 51 Internal bus 8-bit timer compare Selector INTTM5n register 5n (CR5n) Match 8-bit timer TI5n TO5n counter 5n Note Count clock (TM5n) Clear Invert level...
Page 352 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) 8-bit timer counters 50 and 51 (TM50, TM51) The TM5n register is an 8-bit read-only register that counts the count pulses. The counter is incremented in synchronization with the rising edge of the count clock. Through cascade connection, the TM5n registers can be used as a 16-bit timer.
Page 353: Control Registers
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.3 Control Registers The following two registers are used to control 8-bit timer/event counter 5n. • Timer clock selection register 5n (TCL5n) • 8-bit timer mode control register 5n (TMC5n) Remark To use the functions of the TI5n and TO5n pins, refer to Table 4-28 Settings When Port Pins Are Used for Alternate Functions.
Page 354 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control registers 50 and 51 (TMC50, TMC51) The TMC5n register performs the following six settings. • Controls counting by 8-bit timer counters 50 and 51 (TM50, TM51) • Selects the operation mode of the TM50 and TM51 registers •...
Page 355 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 After reset: 00H Address: TMC50 FFFFF5C6H TMC51 FFFFF5C7H <7> <0> Note TMC5n TCE5n TMC5n6 TMC514 LVS5n LVR5n TMC5n1 TOE5n (n = 0, 1) TCE5n Control of count operation of 8-bit timer/event counter 5n Counting is disabled after the counter is cleared to 0 (counter disabled) Start count operation TMC5n6...
Page 356: Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4 Operation 8.4.1 Operation as interval timer (8 bits) 8-bit timer/event counter 5n operates as an interval timer that repeatedly generates interrupts at the interval of the count value preset in 8-bit timer compare register 5n (CR5n). If the count value in 8-bit timer counter 5n (TM5n) matches the value set in the CR5n register, the value of the TM5n register is cleared to 0 and counting is continued, and at the same time, an interrupt request signal (INTTM5n) is generated.
Page 357 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-2. Timing of Interval Timer Operation (2/2) When CR5n register = 00H Count clock TM5n count value CR5n TCE5n INTTM5n Interval time Remark n = 0, 1 When CR5n register = FFH Count clock TM5n count value FEH FFH...
Page 358: Operation As External Event Counter (8 Bits)
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.2 Operation as external event counter (8 bits) The external event counter counts the number of clock pulses input to the TI5n pin from an external source by using 8-bit timer counter 5n (TM5n). Each time the valid edge specified by timer clock selection register 5n (TCL5n) is input to the TI5n pin, the TM5n register is incremented.
Page 359: Square-Wave Output Operation (8-Bit Resolution)
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.3 Square-wave output operation (8-bit resolution) A square wave with any frequency can be output at an interval specified by the value preset in 8-bit timer compare register 5n (CR5n). By setting the TOE5n bit of 8-bit timer mode control register 5n (TMC5n) to 1, the output status of the TO5n pin is inverted at an interval specified by the count value preset in the CR5n register.
Page 360 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-4. Timing of Square-Wave Output Operation Count clock TM5n count value Count start Clear Clear CR5n TCE5n INTTM5n Interrupt Interrupt acknowledgement acknowledgement TO5n Interval time Interval time Note The initial value of the TO5n output can be set using the LVS5n and LVR5n bits of the TMC5n register.
Page 361: 8-Bit Pwm Output Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.4 8-bit PWM output operation By setting the TMC5n6 bit of 8-bit timer mode control register 5n (TMC5n) to 1, 8-bit timer/event counter 5n performs PWM output. Pulses with a duty factor determined by the value set in 8-bit timer compare register 5n (CR5n) are output from the TO5n pin.
Page 362 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (a) Basic operation of PWM output Figure 8-5. Timing of PWM Output Operation Basic operation (active level = H) Count clock TM5n count value N + 1 CR5n TCE5n INTTM5n TO5n Active level Inactive level Active level When CR5n register = 00H...
Page 363 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (b) Operation based on CR5n register transitions Figure 8-6. Timing of Operation Based on CR5n Register Transitions When the value of the CR5n register changes from N to M before the rising edge of the FFH clock →...
Page 364: Operation As Interval Timer (16 Bits)
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.5 Operation as interval timer (16 bits) The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are provided with a 16-bit register that can be used only during cascade connection. The 16-bit resolution timer/event counter mode is selected by setting the TMC514 bit of 8-bit timer mode control register 51 (TMC51) to 1.
Page 365 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-35 shows a timing example of the cascade connection mode with 16-bit resolution. Figure 8-7. Cascade Connection Mode with 16-Bit Resolution Count clock TM50 count value N– 1 TM51 count value M –...
Page 366: Operation As External Event Counter (16 Bits)
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.6 Operation as external event counter (16 bits) The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are provided with a 16-bit register that can be used only during cascade connection. The 16-bit resolution timer/event counter mode is selected by setting the TMC514 bit of 8-bit timer mode control register 51 (TMC51) to 1.
Page 367: Square-Wave Output Operation (16-Bit Resolution)
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.7 Square-wave output operation (16-bit resolution) The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are provided with a 16-bit register that can be used only during cascade connection. The 16-bit resolution timer/event counter mode is selected by setting the TMC514 bit of 8-bit timer mode control register 51 (TMC51) to 1.
Page 368 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.8 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because 8-bit timer counter 5n (TM5n) is started asynchronously to the count pulse. Figure 8-8.
Page 369: Chapter 9 8-Bit Timers H0 And H1
CHAPTER 9 8-BIT TIMERS H0 AND H1 Two 8-bit timer H0 and H1 channels are incorporated in each product. Product Name V850ES/KF1 V850ES/KG1 V850ES/KJ1 Number of channels 2 channels (TMH0, TMH1) 9.1 Functions 8-bit timers H0 and H1 have the following functions.
Page 370 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-1 shows the block diagram. Figure 9-1. Block Diagram of 8-Bit Timers H0 and H1 Internal bus 8-bit timer H mode 8-bit timer H carrier control register n (TMHMDn) register n (TMCYCn) 8-bit timer H compare 8-bit timer H compare RMCn NRZBn...
Page 371 CHAPTER 9 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register n0 (CMPn0) The CMPn0 register can be read and written by an 8-bit memory manipulation instruction. RESET input clears CMPn0 to 00H. After reset: 00H Address: FFFFF582H, FFFFF592H CMPn0 Caution Rewriting the CMPn0 register during timer count operation is prohibited.
Page 372: Control Registers
CHAPTER 9 8-BIT TIMERS H0 AND H1 9.3 Control Registers The registers that control 8-bit timers H0 and H1 are as follows. • 8-bit timer H mode register n (TMHMDn) • 8-bit timer H carrier control register n (TMCYCn) Remarks 1. To use the TOHn pin function, refer to Table 4-28 Settings When Port Pins Are Used for Alternate Functions.
Page 373 CHAPTER 9 8-BIT TIMERS H0 AND H1 (a) 8-bit timer H mode register 0 (TMHMD0) After reset: 00H Address: FFFFF580H <7> <0> TMHMD0 TMHE0 CKSH02 CKSH01 CKSH00 TMMD01 TMMD00 TOLEV0 TOEN0 TMHE0 8-bit timer H0 operation enable Stop timer count operation (8-bit timer counter H0 = 00H) Enable timer count operation (Counting starts when clock is input) CKSH02 CKSH01...
Page 374 CHAPTER 9 8-BIT TIMERS H0 AND H1 (b) 8-bit timer H mode register 1 (TMHMD1) After reset: 00H Address: FFFFF590H <7> <0> TMHMD1 TMHE1 CKSH12 CKSH11 CKSH10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 8-bit timer H1 operation enable Stop timer count operation (8-bit timer counter H1 = 00H) Enable timer count operation (Counting starts when clock is input) CKSH12 CKSH11...
Page 375 CHAPTER 9 8-BIT TIMERS H0 AND H1 (2) 8-bit timer H carrier control register n (TMCYCn) This register controls the 8-bit timer Hn remote control output and carrier pulse output status. TMCYCn register is set by an 8- bit or 1-bit memory manipulation instruction. The NRZn bit is a read-only bit.
Page 376: Operation
CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4 Operation 8-bit timers H0 and H1 can operate in the following three modes. • Interval timer mode • Carrier generator mode • PWM pulse generator mode Caution Rewriting the values of 8-bit timer H compare registers 00 and 10 (CMP00 and CMP10) while 8-bit timers H0 and H1 are operating is prohibited.
Page 377 CHAPTER 9 8-BIT TIMERS H0 AND H1 <3> When the count value of 8-bit timer counter Hn and the value of the CMPn0 register match, the INTTMHn signal is generated and 8-bit timer counter Hn is cleared to 00H. Interval time = (N + 1)/f <4>...
Page 378 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-3. Timing of Interval Timer Operation (2/2) Operation when CMPn0 = FFH Count clock Count start 8-bit timer counter Hn count value Clear Clear CMPn0 TMHEn INTTMHn TOHn Interval time Operation when CMPn0 = 00H Count clock Count start 8-bit timer counter...
Page 379 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.2 PWM pulse generator mode operation In the PWM mode, a pulse of any duty and cycle can be output. 8-bit timer H compare register n0 (CMPn0) controls the timer output (TOHn) cycle. Rewriting the CMPn0 register during timer operation is prohibited.
Page 380 CHAPTER 9 8-BIT TIMERS H0 AND H1 <3> After the count operation is enabled, the first compare register to be compared is the CMPn0 register. When the count value of 8-bit timer counter Hn and the value of the CMPn0 register match, 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and the TOHn output becomes active.
Page 381 CHAPTER 9 8-BIT TIMERS H0 AND H1 (2) Timing chart The operation timing in the PWM mode is as follows. Caution The setting value (M) of the CMPn1 register and the setting value (N) of the CMPn0 register must always be set within the following range. 00H ≤...
Page 382 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-5. Operation Timing in PWM Pulse Generator Mode (2/4) Operation when CMPn0 = FFH, CMPn1 = 00H Count clock 8-bit timer counter 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H Hn count value CMPn0...
Page 383 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-5. Operation Timing in PWM Pulse Generator Mode (3/4) Operation when CMPn0 = 01H, CMPn1 = 00H Count clock 8-bit timer counter 01H 00H 01H 00H 00H 01H 00H 01H Hn count value CMPn0 CMPn1 TMHEn...
Page 384 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-5. Operation Timing in PWM Pulse Generator Mode (4/4) Operation based on CMPn1 transitions (CMPn1 = 01H → 03H, CMPn0 = A5H) Count clock 8-bit timer counter 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H Hn count value...
Page 385 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.3 Carrier generator mode operation The carrier clock generated by 8-bit timer Hn is output using the cycle set with 8-bit timer/event counter 5n. In the carrier generator mode, 8-bit timer/event counter 5n is used to control the extent to which the carrier pulse of 8-bit timer Hn is output, and the carrier pulse is output from the TOHn output.
Page 386 CHAPTER 9 8-BIT TIMERS H0 AND H1 To control carrier pulse output during count operation, the NRZn and NRZBn bits of the TMCYCn register have a master and slave bit configuration. The NRZn bit is read-only while the NRZBn bit can be read and written. The INTTM5n signal is synchronized with the 8-bit timer Hn clock and output as the INTTM5Hn signal.
Page 387 CHAPTER 9 8-BIT TIMERS H0 AND H1 (3) Usage method Any carrier clock can be output from the TOHn pin. <1> Set each register. Figure 9-8. Register Settings in Carrier Generator Mode • 8-bit timer H mode register n (TMHMDn) TMHEn CKSHn2 CKSHn1...
Page 388 CHAPTER 9 8-BIT TIMERS H0 AND H1 Designating the setting value of the CMPn0 register as (N), the setting value of the CMPn1 register as (M), and the count clock frequency as f , the carrier clock output cycle and duty ratio are as follows. Carrier clock output cycle = (N + M + 2)/f Duty ratio = High level width: Low level width = (M + 1) : (N + 1) Caution Be sure to set the CMPn1 register when starting the timer count operation (TMHEn = 1) after...
Page 389 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-9. Carrier Generator Mode (1/3) Operation when CMPn0 = N, CMPn1 = N is set 8-bit timer Hn count clock 8-bit timer counter N 00H N 00H N 00H N 00H N 00H Hn count value CMPn0 CMPn1...
Page 390 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-9. Carrier Generator Mode (2/3) Operation when CMPn0 = N, CMPn1 = M is set (operation with carrier clock phase asynchronous to NRZn phase) 8-bit timer Hn count clock 8-bit timer counter N 00H 01H M 00H N 00H 01H...
Page 391 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-9. Carrier Generator Mode (3/3) Operation based on CMPn1 transitions 8-bit timer Hn count clock 8-bit timer counter 00H 01H 00H 01H Hn count value CMPn0 <3> <3>' CMPn1 M (L) TMHEn INTTMHn <4>...
Page 392: Chapter 10 Real-Time Output Function (Rto)
Because RTO can output signal without jitter, it is suitable for controlling a stepping motor. In the V850ES/KF1 and V850ES/KG1, one 6-bit real-time output port channel is provided. In the V850ES/KJ1, two 6-bit real-time output port channels are provided.
Page 393 CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) 10.2 Configuration RTO consists of the following hardware. Table 10-1. Configuration of RTO Item Configuration Registers Real-time output buffer register n (RTBLn, RTBHn) Control registers Real-time output port mode register n (RTPMn) Real-time output port control register n (RTPCn) (1) Real-time output buffer register n (RTBLn, RTBHn) RTBLn and RTBHn are 4-bit registers that hold output data in advance.
Page 394: Rto Control Registers
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) 10.3 RTO Control Registers RTO is controlled using the following two types of registers. • Real-time output port mode register n (RTPMn) • Real-time output port control register n (RTPCn) (1) Real-time output port mode register n (RTPMn) This register selects the real-time output port mode or port mode in 1-bit units.
Page 395 CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register n (RTPCn) RTPCn are registers used to set the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Tables 10-3 and 10-4.
Page 396: Operation
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) 10.4 Operation If the real-time output operation is enabled by setting bit 7 (RTPOEn) of real-time output port control register n (RTPCn) to 1, the data of real-time output buffer register n (RTBHn, RTBLn) is transferred to the real-time output latch Note in synchronization with the generation of the selected transfer trigger (set by EXTRn and BYTEn ).
Page 397 CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) 10.5 Usage (1) Disable real-time output. Clear bit 7 (RTPOEn) of real-time output port control register n (RTPCn) to 0. (2) Perform initialization as follows. • Specify the real-time output port mode or port mode in 1-bit units. Set real-time output port mode register n (RTPMn).
Page 398: Security Function
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO) 10.7 Security Function A circuit that sets the pin outputs to high impedance as a security function for when malfunctions of a stepping motor controlled by RTO occur is provided on chip. It forcibly resets the pins allocated to RTP00 to RTP05 via external Note 1 interrupt INTP0 edge detection, and the pins allocated to RTP10 to RTP15 via INTP1 edge detection , placing them...
Page 399 INTPn is used as trigger for security function Notes 1. The RTOST1 bit is valid only for the V850ES/KJ1. In the V850ES/KG1 and V850ES/KF1, this bit is fixed to 0. Changing the value of this bit does not affect the operation.
Page 400: Chapter 11 Watch Timer Functions
CHAPTER 11 WATCH TIMER FUNCTIONS 11.1 Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and interval timer functions can be used at the same time. Figure 11-1. Block Diagram of Watch Timer Clear 5-bit counter INTWT...
Page 401 CHAPTER 11 WATCH TIMER FUNCTIONS Figure 11-2. Block Diagram of Prescaler 3 3-bit prescaler BGCS INTBRG 8-bit counter Clear Match Output control Prescaler compare register (PRSCM) Prescaler mode register (PRSM) BGCE TODIS BGCS1 BGCS0 Remark f Prescaler 3 clock frequency Oscillation frequency INTBRG: Prescaler 3 interval timer interrupt (1) Watch timer...
Page 402: Watch Timer Control Registers
CHAPTER 11 WATCH TIMER FUNCTIONS 11.2 Configuration The watch timer consists of the following hardware. Table 11-2. Configuration of Watch Timer Item Configuration 5 bits × 1 Counter 11 bits × 1 Prescaler Control register Watch timer operation mode register (WTM) 11.3 Watch Timer Control Registers Two registers control the watch timer, the watch timer operation mode register (WTM).
Page 403 CHAPTER 11 WATCH TIMER FUNCTIONS After reset: 00H Address: FFFFF680H < > < > WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 WTM7 WTM6 WTM5 WTM4 Selection of interval time of prescaler µ (488 s: f µ (977 s: f (1.95 ms: f (3.91 ms: f (7.81 ms: f...
Page 404 CHAPTER 11 WATCH TIMER FUNCTIONS 11.4 Operation 11.4.1 Operation as watch timer The watch timer generates an interrupt request at fixed time intervals. The watch timer operates using time intervals of 0.5 seconds with the subclock (32.768 kHz). The count operation starts when bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1.
Page 405 CHAPTER 11 WATCH TIMER FUNCTIONS Figure 11-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock or f Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T)
Page 406 CHAPTER 11 WATCH TIMER FUNCTIONS 11.5 Prescaler 3 The prescaler 3 has the following functions. • Generation of watch timer count clock (source clock: main oscillation clock) • Interval timer (INTBRG) 11.5.1 Control registers (1) Prescaler mode register (PRSM) The PRSM register controls the generation of the count clock for the watch timer. PRSM can be read and written in 8-bit units.
Page 407 CHAPTER 11 WATCH TIMER FUNCTIONS (2) Prescaler compare register (PRSCM) This is an 8-bit compare register. PRSCM can be read and written in 8-bit units. After reset: 00H Address: FFFFF8B1H PRSCM PRSCM7 PRSCM6 PRSCM5 PRSCM4 PRSCM3 PRSCM2 PRSCM1 PRSCM0 Cautions 1. Do not rewrite the PRSCM register during prescaler operation. 2.
Page 408: Chapter 12 Watchdog Timer Functions
CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.1 Watchdog Timer 1 12.1.1 Functions Watchdog timer 1 has the following operation modes. • Watchdog timer 1 • Interval timer • Selecting the oscillation stabilization time The following functions are realized from the above-listed operation modes. •...
Page 409 CHAPTER 12 WATCHDOG TIMER FUNCTIONS Figure 12-1. Block Diagram of Watchdog Timer 1 Internal bus Watchdog timer clock Oscillation stabilization time Watchdog timer mode selection register (WDCS) selection register (OSTS) register 1 (WDTM1) RUN1 WDTM14 WDTM13 WDCS2 WDCS1 WDCS0 OSTS2 OSTS1 OSTS0 Clear...
Page 410 CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.1.2 Configuration Watchdog timer 1 consists of the following hardware. Table 12-1. Configuration of Watchdog Timer 1 Item Configuration Control register Oscillation stabilization time selection register (OSTS) Watchdog timer clock selection register (WDCS) Watchdog timer mode register 1 (WDTM1) 12.1.3 Watchdog timer 1 control register The registers that control watchdog timer 1 are as follows.
Page 411 CHAPTER 12 WATCHDOG TIMER FUNCTIONS (2) Watchdog timer clock selection register (WDCS) This register sets the overflow time of watchdog timer 1 and the interval timer. The WDCS register is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears WDCS to 00H. After reset: 00H Address: FFFFF6C1H WDCS...
Page 412 CHAPTER 12 WATCHDOG TIMER FUNCTIONS (3) Watchdog timer mode register 1 (WDTM1) This register sets the watchdog timer 1 operation mode and enables/disables count operations. This register is a special register that can be written only in a special sequence (refer to 3.4.7 Special registers).
Page 413 CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.1.4 Operation (1) Oscillation stabilization time selection function The wait time until the oscillation stabilizes after the STOP mode is released is controlled by the oscillation stabilization time register (OSTS). The OSTS register is set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 01H.
Page 414 CHAPTER 12 WATCHDOG TIMER FUNCTIONS (2) Operation as watchdog timer 1 Watchdog timer 1 operation to detect a program loop is selected by setting bit 4 (WDTM14) of watchdog timer mode register 1 (WDTM1) to 1. The count clock (program loop detection time interval) of watchdog timer 1 can be selected using bits WDCS0 to WDCS2 of the watchdog timer clock selection register (WDCS).
Page 415 CHAPTER 12 WATCHDOG TIMER FUNCTIONS (3) Operation as interval timer Watchdog timer 1 can be made to operate as an interval timer that repeatedly generates interrupts using the count value set in advance as the interval, by setting bit 4 (WDTM14) of watchdog timer mode register 1 (WDTM1) to 0.
Page 416 CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.2 Watchdog Timer 2 12.2.1 Functions Watchdog timer 2 has the following functions. • Default start watchdog timer Note 1 → Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDTRES2) → Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 (generation of Note 2 INTWDT2) •...
Page 417 CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.2.2 Configuration Watchdog timer 2 consists of the following hardware. Table 12-4. Configuration of Watchdog Timer 2 Item Configuration Control register Watchdog timer mode register 2 (WDTM2) Watchdog timer enable register (WDTE) 12.2.3 Watchdog timer 2 control register (1) Watchdog timer mode register 2 (WDTM2) This register sets the overflow time and operation clock of watchdog timer 2.
Page 418 CHAPTER 12 WATCHDOG TIMER FUNCTIONS Table 12-5. Watchdog Timer 2 Clock Selection WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Selected Clock = 20 MHz = 16 MHz = 10 MHz 13.1 ms 16.4 ms 26.2 ms 26.2 ms 32.8 ms 52.4 ms 52.4 ms 65.5 ms 104.9 ms...
Page 419 CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.2.4 Operation Watchdog timer 2 automatically starts in the reset mode following reset release. The WDTM2 register can be written to only once following reset through byte access. To use watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using 8-bit memory manipulation instructions. After this is done, the operation of watchdog timer 2 cannot be stopped.
Page 420: Chapter 13 A/D Converter
CHAPTER 13 A/D CONVERTER 13.1 Function The A/D converter converts analog input signals into digital values with a resolution of 10 bits. In the V850ES/KF1 and V850ES/KG1, it has an 8-channel (ANI0 to ANI7) configuration, and in the V850ES/KJ1, it has a 16-channel (ANI0 to ANI15) configuration.
Page 421 The A/D converter consists of the following hardware. Table 13-1. Configuration of A/D Converter Item Configuration Analog input V850ES/KF1, V850ES/KG1: 8 channels (ANI0 to ANI7) V850ES/KJ1: 16 channels (ANI0 to ANI15) Registers Successive approximation register (SAR) A/D conversion result register (ADCR)
Page 422 (ADS) can be used as input ports. Note The V850ES/KF1 and V850ES/KG1 provide only 8 channels, ANI0 to ANI7. Caution Make sure that the voltage input to ANI0 to ANI15 does not exceed the rated values. If a...
Page 423: Control Registers
CHAPTER 13 A/D CONVERTER 13.3 Control Registers The A/D converter is controlled by the following registers. • A/D converter mode register (ADM) • Analog input channel specification register (ADS) • Power fail comparison mode register (PFM) (1) A/D converter mode register (ADM) This register sets the conversion time of the analog input signal to be converted into a digital signal as well as conversion start and stop.
Page 424 CHAPTER 13 A/D CONVERTER Table 13-2. Operation Mode Control ADCS ADCS2 Stopped status DC power consumption path does not exist. Conversion standby mode Only the comparator consumes power. Note Conversion mode Note Conversion mode Note When A/D conversion is started as follows, the first conversion result is invalid. <1>...
Page 425 Note 2 ANI15 Notes 1. Because V850ES/KF1 and V850ES/KG1 have 8 channels (ANI0 to ANI7), be sure to set the ADS3 bit to 0. 2. The ANI8 to ANI15 channels are available only in the V850ES/KJ1. In the V850ES/KF1 and V850ES/KG1, setting these channels is prohibited.
Page 426 CHAPTER 13 A/D CONVERTER (3) Power fail comparison mode register (PFM) This register sets the power fail monitoring mode. It compares the value of the power fail comparison threshold register (PFT) and the value of the A/D conversion result register (ADCRH). The PFM register is set by an 8-bit or 1-bit memory manipulation instruction.
Page 427: Relationship Between Analog Input Voltage And A/D Conversion Result
CHAPTER 13 A/D CONVERTER 13.4 Relationship Between Analog Input Voltage and A/D Conversion Result The relationship between the analog voltage input to an analog input pin (ANI0 to ANI15) and the value of the A/D conversion result register (ADCR) is as follows: ADCR = INT ( ×1,024 + 0.5) REF0...
Page 428: Operation
CHAPTER 13 A/D CONVERTER 13.5 Operation 13.5.1 Basic operation <1> Select one channel whose analog signal is to be converted into a digital signal using the analog input channel specification register (ADS). <2> The sample & hold circuit samples the voltage input to the selected analog input channel. <3>...
Page 429 CHAPTER 13 A/D CONVERTER 13.5.2 Conversion operation (software trigger mode) • Setting ADCS of the A/D converter mode register (ADM) to 1 starts conversion of the signal input to the channel specified with the analog input channel specification register (ADS). Upon completion of the conversion, the conversion result is stored to the ADCR register and a new conversion starts.
Page 430 CHAPTER 13 A/D CONVERTER 13.6 Cautions (1) Power consumption in standby mode The operation of the A/D converter stops in the STOP and IDLE modes (operation of the A/D converter is possible in the HALT mode). At this time, the power consumption can be reduced by stopping the conversion operation (bit 7 (ADCS) and bit 0 (ADCS2) of the A/D converter mode register (ADM) = 0).
Page 431 CHAPTER 13 A/D CONVERTER Table 13-3. A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value) Note Conversion Time Sampling Time A/D Conversion Start Delay Time MIN. MAX. 288/f 40/f 32/f 36/f 240/f 32/f 28/f 32/f 192/f 24/f 24/f 28/f...
Page 432: How To Read A/D Converter Characteristics Table
CHAPTER 13 A/D CONVERTER 13.7 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 433 CHAPTER 13 A/D CONVERTER (3) Quantization error When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of ±1/2LSB is converted to the same digital code, so a quantization error cannot be avoided.
Page 434 CHAPTER 13 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 1……110 to 1……111. Figure 13-9. Full-Scale Error Full-scale error –3 –2 –1...
Page 435 CHAPTER 13 A/D CONVERTER (7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0.
Page 436: Chapter 14 D/A Converter
Analog output voltage: AV REF1 Operation modes: Normal mode, real-time output mode Caution The V850ES/KF1 does not have a D/A converter. Remark n = 0, 1 The D/A converter configuration is shown below. Figure 14-1. Block Diagram of D/A Converter...
Page 437 CHAPTER 14 D/A CONVERTER 14.2 Configuration The D/A converter consists of the following hardware. Table 14-1. Configuration of D/A Converter Item Configuration Control register D/A converter mode register (DAM) D/A conversion value setting registers 0 and 1 (DACS0, DACS1) 14.3 D/A Converter Control Register The registers that control the D/A converter are as follows.
Page 438 CHAPTER 14 D/A CONVERTER (2) D/A conversion value setting registers 0 and 1 (DACS0, DACS1) These registers set the analog voltage value output to the ANO0 and ANO1 pins. These register are set by an 8-bit memory manipulation instruction. RESET input clears DACS0 and DACS1 to 00H. After reset: 00H Address: FFFFF280H DACS0...
Page 439 CHAPTER 14 D/A CONVERTER 14.4 Operation 14.4.1 Operation in normal mode D/A conversion is performed using a write operation to the D/A conversion value setting register (DACSn) as the trigger. The setting method is described below. <1> Set the DAMDn bit of the D/A converter mode register (DAM) to 0 (normal mode). <2>...
Page 440 CHAPTER 14 D/A CONVERTER 14.4.3 Cautions Observe the following cautions when using the D/A converter of the V850ES/KG1 and V850ES/KJ1. • When using the D/A converter, set the port pins to the input mode (PM1n bit = 1; n = 0, 1) •...
Page 441: Chapter 15 Asynchronous Serial Interface (Uart)
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) The number of asynchronous serial interface (UART) channels incorporated differs as follows depending on the product. Product Name V850ES/KF1 V850ES/KG1 V850ES/KJ1 Number of channels 2 channels (UART0, UART1) 3 channels (UART0 to UART2) 15.1 Selecting UART2 or I...
Page 442 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) 15.2 Features • Full-duplex communications On-chip reception buffer register n (RXBn) On-chip transmission buffer register n (TXBn) • Two-pin configuration Note TXDn: Transmit data output pin RXDn: Receive data input pin • Reception error detection functions •...
Page 443 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) 15.3 Configuration UARTn is controlled by asynchronous serial interface mode register n (ASIMn), asynchronous serial interface status register n (ASISn), and asynchronous serial interface transmission status register n (ASIFn). Receive data is maintained in reception buffer register n (RXBn), and transmit data is written to transmission buffer register n (TXBn). Figure 15-2 shows the configuration of asynchronous serial interface n (UARTn).
Page 444 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) (8) Transmission buffer register n (TXBn) TXBn is an 8-bit buffer for transmit data. A transmit operation is started by writing transmit data to TXBn. The transmission completion interrupt request (INTSTn) is generated synchronized with the completion of transmission of one frame.
Page 445: Control Registers
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) 15.4 Control Registers (1) Asynchronous serial interface mode register n (ASIMn) The ASIMn register is an 8-bit register that controls the UARTn transfer operation. This register can be read/written in 8-bit or 1-bit units. Caution When using UARTn, be sure to set the external pins related to UARTn functions to the control made before setting clock select register n (CKSRn) and the baud rate generator control register n (BRGCn), and then set the UARTEn bit to 1.
Page 446 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) (2/3) RXEn Enables/disables reception Note Disables reception Enables reception • Set the RXEn bit to 1 after setting the UARTEn bit to 1 at startup. Set the UARTEn bit to 0 after setting the RXEn bit to 0 to stop.
Page 447 In this case, no reception error interrupt request (INTSREn) is generated. • To overwrite the ISRMn bit, first clear (0) the RXEn bit. Remark n = 0, 1 (V850ES/KF1, V850ES/KG1) n = 0 to 2 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 448 • When an overrun error occurs, the next receive data value is not written to the RXBn register and the data is discarded. Remark n = 0, 1 (V850ES/KF1, V850ES/KG1) n = 0 to 2 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 449 • When the transmission unit is initialized, initialization should be executed after confirming that this flag is 0 following the occurrence of a transmission completion interrupt. If initialization is performed when this flag is 1, transmit data cannot be guaranteed. Remark n = 0, 1 (V850ES/KF1, V850ES/KG1) n = 0 to 2 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 450 This register is read-only in 8-bit units. After reset: FFH Address: FFFFFA02H, FFFFFA12H, FFFFFA22H RXBn RXBn7 RXBn6 RXBn5 RXBn4 RXBn3 RXBn2 RXBn1 RXBn0 Remark n = 0, 1 (V850ES/KF1, V850ES/KG1) n = 0 to 2 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 451 This register can be read or written in 8-bit units. After reset: FFH Address: FFFFFA04H, FFFFFA14H, FFFFFA24H TXBn TXBn7 TXBn6 TXBn5 TXBn4 TXBn3 TXBn2 TXBn1 TXBn0 Remark n = 0, 1 (V850ES/KF1, V850ES/KG1) n = 0 to 2 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 452: Interrupt Requests
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) 15.5 Interrupt Requests The following three types of interrupt requests are generated from UARTn. • Reception error interrupt (INTSREn) • Reception completion interrupt (INTSRn) • Transmission completion interrupt (INTSTn) The default priorities among these three types of interrupt requests is, from high to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt.
Page 453: Operation
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) 15.6 Operation 15.6.1 Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 15-3. The character bit length within one data frame, the type of parity, and the stop bit length are specified according to asynchronous serial interface mode register n (ASIMn).
Page 454 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) 15.6.2 Transmit operation When the UARTEn bit is set to 1 in the ASIMn register, a high level is output from the TXDn pin. Then, when the TXEn bit is set to 1 in the ASIMn register, transmission is enabled, and the transmit operation is started by writing transmit data to transmission buffer register n (TXBn).
Page 455 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) Figure 15-4. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) Stop bit length: 1 Start TXDn (output) Parity Stop INTSTn (output) (b) Stop bit length: 2 Stop Parity TXDn (output) Start INTSTn (output) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 456 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) 15.6.3 Continuous transmission operation UARTn can write the next transmit data to the TXBn register at the timing that the transmission shift register starts the shift operation. This enables an efficient transmission rate to be realized by continuously transmitting data even during the INTSTn interrupt service after the transmission of one data frame.
Page 457 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) Figure 15-5. Continuous Transmission Processing Flow Set registers Write transmit data to TXBn register When reading ASIFn register, TXBFn = 0? Interrupt occurrence Required number of transfers performed? When reading When reading ASIFn register, ASIFn register, TXSFn = 0? TXSFn = 1?
Page 458 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) (1) Starting procedure The procedure to start continuous transmission is shown below. Figure 15-6. Continuous Transmission Starting Procedure Start Start Stop Stop TXDn (output) Data (1) Data (2) <1> <2> <3> <4> <5> INTSTn (output) TXBn register Data (1) Data (2)
Page 459 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) (2) Ending procedure The procedure for ending continuous transmission is shown below. Figure 15-7. Continuous Transmission End Procedure Start Start Stop Stop TXDn (output) Data (m − 1) Data (m) <6> <7> <8> <9> <10>...
Page 460 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) 15.6.4 Receive operation The awaiting reception state is set by setting the UARTEn bit to 1 in the ASIMn register and then setting the RXEn bit to 1 in the ASIMn register. To start the receive operation, first perform start bit detection. The start bit is detected by sampling the RXDn pin.
Page 461 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) Figure 15-8. Asynchronous Serial Interface Reception Completion Interrupt Timing RXDn (input) Start Parity Stop INTSRn (output) RXBn register Cautions 1. Be sure to read reception buffer register n (RXBn) even when a reception error occurs. If RXBn is not read, an overrun error will occur at the next data reception and the reception error status will continue infinitely.
Page 462 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) (1) Separation of reception error interrupt A reception error interrupt can be separated from the INTSRn interrupt and generated as the INTSREn interrupt by clearing the ISRMn bit of the ASIMn register to 0. Figure 15-9.
Page 463 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) 15.6.6 Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used on the transmission and reception sides. (1) Even parity (i) During transmission The parity bit is controlled so that the number of bits with the value “1”...
Page 464 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) 15.6.7 Receive data noise filter The RXDn signal is sampled at the rising edge of the prescaler output base clock (Clock). If the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see Figure 15-12).
Page 465: Dedicated Baud Rate Generator N (Brgn)
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) 15.7 Dedicated Baud Rate Generator n (BRGn) A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by UARTn. The dedicated baud rate generator output can be selected as the serial clock for each channel.
Page 466 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) 15.7.2 Serial clock generation A serial clock can be generated according to the settings of the CKSRn and BRGCn registers. The base clock to the 8-bit counter is selected by the TPSn3 to TPSn0 bits of the CKSRn register. The 8-bit counter divisor value can be set by the MDLn7 to MDLn0 bits of the BRGCn register.
Page 467 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) (2) Baud rate generator control register n (BRGCn) The BRGCn register is an 8-bit register that controls the baud rate (serial transfer speed) of UARTn. This register can be read or written in 8-bit units. Caution If the MDLn7 to MDLn0 bits are to be overwritten, the TXEn and RXEn bits should be set to 0 in the ASIMn register first.
Page 468 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) (3) Baud rate The baud rate is the value obtained by the following formula. Baud rate = [bps] 2 × k = Frequency [Hz] of base clock (Clock) selected by TPSn3 to TPSn0 bits of CKSRn register. k = Value set by MDLn7 to MDLn0 bits of BRGCn register (k = 8, 9, 10, ..., 255) (4) Baud rate error The baud rate error is obtained by the following formula.
Page 469 Remark f Internal system clock frequency Base clock frequency Setting values of MDLn7 to MDLn0 bits in BRGCn register ERR: Baud rate error [%] n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 470 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) 15.7.4 Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range.
Page 471 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) Therefore, the transfer destination’s maximum receivable baud rate (BRmax) is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows. − × ×...
Page 472 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) 15.7.5 Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock (Clock) longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit.
Page 473: Chapter 16 Clocked Serial Interface 0 (Csi0)
• Two transmission buffers (SOTBFn/SOTBFLn, SOTBn/SOTBLn) and two reception buffers (SIRBn/SIRBLn, SIRBEn/SIRBELn) are provided on chip • Single transfer mode/repeat transfer mode selectable Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 474 CHAPTER 16 CLOCKED SERIAL INTERFACE 0 (CSI0) 16.2 Configuration CSI0n is controlled via clocked serial interface mode register 0n (CSIM0n). (1) Clocked serial interface mode register 0n (CSIM0n) The CSIM0n register is an 8-bit register that specifies the operation of CSI0n. (2) Clocked serial interface clock selection register n (CSICn) The CSICn register is an 8-bit register that controls the CSI0n serial transfer operation.
Page 475 Counts the serial clock output or input during transmission/reception operation, and checks whether 8-bit or 16-bit data transmission/reception has been performed. (16) Interrupt controller Controls the interrupt request timing. Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 476 (SOTBFn/SOTBFnL) Transmit buffer register (SOTBn/SOTBnL) Shift register SI0n SO latch (SIOn/SIO0nL) Receive buffer register (SIRBn/SIRBnL) Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. f : Internal system clock User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 477: Control Registers
CHAPTER 16 CLOCKED SERIAL INTERFACE 0 (CSI0) 16.3 Control Registers (1) Clocked serial interface mode register 0n (CSIM0n) The CSIM0n register controls the CSI0n operation. These registers can be read/written in 8-bit or 1-bit units (however, bit 0 is read-only). Caution Overwriting the TRMDn, CCLn, DIRn, CSITn, and AUTOn bits of the CSIM0n register can be done only when the CSOTn bit = 0.
Page 478 CSOTn Flag indicating transfer status Idle status Transfer execution status The CSOTn bit is cleared (0) by writing 0 to the CSI0En bit. Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 479 ≤ 10 MHz Notes 1. Selectable when f 2. CSI00: TO50 CSI01: TO51 CSI02: TO51 Remarks 1. f : Internal system clock frequency 2. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 480 SIRBn SIRBn Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) (4) Clocked serial interface reception buffer register nL (SIRBnL) The SIRBnL register is an 8-bit buffer register that stores receive data. When the receive-only mode is set (TRMDn bit of CSIM0n register = 0), the reception operation is started by reading data from the SIRBnL register.
Page 481 SIRBEn SIRBEn Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) (6) Clocked serial interface read-only reception buffer register nL (SIRBEnL) The SIRBEnL register is an 8-bit buffer register that stores receive data. These registers are read-only, in 8-bit or 1-bit units.
Page 482 SOTBn SOTBn Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) (8) Clocked serial interface transmission buffer register nL (SOTBnL) The SOTBnL register is an 8-bit buffer register that stores transmit data. When the transmission/reception mode is set (TRMDn bit of CSIM0n register = 1), the transmission operation is started by writing data to the SOTBnL register.
Page 483 SOTBFn SOTBFn Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) (10) Clocked serial interface initial transmission buffer register nL (SOTBFnL) The SOTBFnL register is an 8-bit buffer register that stores initial transmission data in the repeat transfer mode.
Page 484 SIOn2 SIOn1 SIOn0 Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) (12) Serial I/O shift register 0nL (SIO0nL) The SIO0nL register is an 8-bit shift register that converts parallel data into serial data. The transfer operation is not started even if the SIO0nL register is read.
Page 485: Operation
When the 8-bit data length (CCLn bit of CSIM0n register = 0) has been set, write to the SOTBnL register. Caution When the CSOTn bit of the CSIM0n register = 1, do not manipulate the CSI0n register. Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 486 INTCSI0n interrupt Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
Page 487 INTCSI0n interrupt Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
Page 488 INTCSI0n interrupt CSOTn bit Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
Page 489 INTCSI0n interrupt CSOTn bit Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
Page 490 CSOTn bit Delay Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
Page 491 CSOTn bit Delay Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
Page 492 CHAPTER 16 CLOCKED SERIAL INTERFACE 0 (CSI0) 16.4.2 Repeat transfer mode (1) Usage (receive-only) <1> Set the repeat transfer mode (AUTOn bit of CSIM0n register = 1) and the receive-only mode (TRMDn bit of CSIM0n register = 0). <2> Read the SIRBn register (start transfer with dummy read). <3>...
Page 493 Period during which next transfer can be reserved Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_RD: Internal signal. This signal indicates that clocked serial interface receive buffer registers n and nL (SIRBn/SIRBnL) have been read.
Page 494 CHAPTER 16 CLOCKED SERIAL INTERFACE 0 (CSI0) (2) Usage (transmission/reception) <1> Set the repeat transfer mode (AUTOn bit of CSIM0n register = 1) and the transmission/reception mode (TRMDn bit of CSIM0n register = 1) <2> Write the first data to the SOTBFn register. <3>...
Page 495 Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. Reg_WR: Internal signal. This signal indicates that clocked serial interface transmit buffer registers n and nL (SOTBn/SOTBnL) have been written.
Page 496 (b) When data length: 16 bits, operation mode: CKPn bit = 0, DAPn bit = 0 SCK0n (I/O) INTCSI0n interrupt Reservation period: 15 SCK0n cycles Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 497 (d) When data length: 16 bits, operation mode: CKPn bit = 0, DAPn bit = 1 SCK0n (I/O) INTCSI0n interrupt Reservation period: 14.5 SCK0n cycles Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 498 Reg_R/W Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. rq_clr: Internal signal. Transfer request clear signal. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
Page 499 Reg_R/W Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. rq_clr: Internal signal. Transfer request clear signal. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer register n and nL (SOTBn/SOTBnL) write was performed.
Page 500: Output Pins
Other than above Fixed to low level Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) 2. When any of the CKPn and CKS0n2 to CKS0n0 bits of the CSICn register is overwritten, the SCK0n pin output changes.
Page 501 CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION The number of CSIA channels incorporated differs as follows depending on the product. Product Name V850ES/KF1 V850ES/KG1 V850ES/KJ1 Number of channels 1 channel (CSIA0) 2 channels (CSIA0, CSIA1) 17.1 Functions CSIAn has the following three modes.
Page 502 Serial data input SCKAn: Serial clock I/O • Transmission/reception completion interrupt: INTCSIAn • Internal 32-byte buffer RAM Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) 17.2 Configuration CSIAn consists of the following hardware. Table 17-1. Configuration of CSIAn...
Page 503 Figure 17-1. Block Diagram of CSIAn Automatic data Automatic data transfer address transfer address Buffer RAM point specification count register n register n (ADTPn) (ADTCn) Internal bus Serial trigger register n (CSITn) DIRn ATMn Divisor selection Serial I/O shift register n SIAn ATSTPn ATSTAn register An (SIOAn)
Page 504: Control Registers
SIOAn register to start the transfer operation, and then perform a receive operation. 2. Do not write data to SIOAn while the automatic transmit/receive function is operating. Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) (2) Automatic data transfer address count register n (ADTCn) This is a register used to indicate buffer RAM addresses during automatic transfer.
Page 505 • When the RXEn bit is 0, write to the transfer buffer RAM is not possible. DIRn Specification of transfer data direction MSB first LSB first Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 506 BRGCAn, ADTPn, ADTIn, SIOAn registers is prohibited. However, the transfer buffer RAM can be rewritten. 3. When writing to bits 1 to 5, always write 0. Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 507 Even when ATSTAn = 1, automatic data transfer does not start until 1 byte has been transferred. 1 is held until immediately before the INTCSIAn interrupt signal is generated. Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 508 This register can be set by an 8-bit memory manipulation instruction. However, when the TSFn bit of serial status register n (CSISn) is 1, rewriting the ADTPn register is prohibited. In the V850ES/KF1, V850ES/KG1, and V850ES/KJ1, 00H to 1FH can be specified because 32 bytes of buffer RAM are incorporated.
Page 509 CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION The relationship between buffer RAM address values and the ADTPn register setting values is shown below. Table 17-2. Relationship Between Buffer RAM Address Values and ADTP0 Register Setting Values Buffer RAM Address Value ADTP0 Register Setting Value Buffer RAM Address Value...
Page 510 ADTIn2 ADTIn1 ADTIn0 Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) (7) CSIAn buffer RAM (CSIAnBm) This area holds transmit/receive data (up to 32 bytes) in automatic transfer mode in 1-bit units. The CSIAnBm register can be read/written in 16-bit units only. However, when the higher 8 bits and the lower 8 bits of the CSIAnBm register are used as the CSIAnBmH register and CSIAnBmL register, respectively, these registers can be read/written in 8-bit units.
Page 511 CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Table 17-4. CSIA0 Buffer RAM Manipulatable Bits Address Symbol After Reset √ FFFFFE00H CSIA0B0 Undefined √ FFFFFE00H CSIA0B0L Undefined √ FFFFFE01H CSIA0B0H Undefined √ FFFFFE02H CSIA0B1 Undefined √ FFFFFE02H CSIA0B1L Undefined √...
Page 512 CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Table 17-5. CSIA1 Buffer RAM Manipulatable Bits Address Symbol After Reset √ FFFFFE20H CSIA1B0 Undefined √ FFFFFE20H CSIA1B0L Undefined √ FFFFFE21H CSIA1B0H Undefined √ FFFFFE22H CSIA1B1 Undefined √ FFFFFE22H CSIA1B1L Undefined √...
Page 513: Operation
CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION 17.4 Operation CSIAn can be used in the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 17.4.1 Operation stop mode Serial transfer is not executed in this mode.
Page 514 • When the RXEn bit is 0, write to the transfer buffer RAM is not possible. DIRn Specification of transfer data direction MSB first LSB first Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 515 BRGCAn, ADTPn, ADTIn, SIOAn registers is prohibited. However, the transfer buffer RAM can be rewritten. 3. When writing to bits 1 to 5, always write 0. Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 516 BRGCn1 BRGCn0 Selection of CSIAn serial clock (f division ratio) SCKA 6 (f SCKA 8 (f SCKA 16 (f /16) SCKA 32 (f /32) SCKA Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 517 V850ES/KF1, V850ES/KG1, V850ES/KJ1 Note 4 Note 4 CSIAE0 MASTER0 PM53 PFC53 PMC53 PM54 PFC54 PMC54 PM55 PFC55 PF55 PMC55 Serial I/O Shift Serial Clock Counter SIA0/P53 SOA0/P54 SCKA0/P55 Register A0 Operation Operation Control Pin Function Pin Function Pin Function ×...
Page 518 CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (3) 1-byte transmission/reception communication operation (a) 1-byte transmission/reception When the CSIAEn bit and ATEn bit of serial operation mode specification register n (CSIMAn) = 1, 0, respectively, if transfer data is written to serial I/O shift register An (SIOAn), the data is output via the SOA0 pin in synchronization with the SCKAn pin falling edge, and then input via the SIAn pin in synchronization with serial clock falling edge, and stored in the SIOAn register in synchronization with the rising edge 1 clock later.
Page 519 CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (b) Data format In the data format, data is changed in synchronization with the SCKAn pin falling edge as shown below. The data length is fixed to 8 bits and the data transfer direction can be switched by the specification of the DIRn bit of serial operation mode specification register n (CSIMAn).
Page 520 Caution If CSIAEn is set to 1 after data is written to SIOAn, transfer does not start. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request signal (INTCSIAn) is generated. Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 521 CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION 17.4.3 3-wire serial I/O mode with automatic transmit/receive function Up to 32 bytes of data can be transmitted/received without using software in the mode in which the ATEn bit of serial operation mode specification register n (CSIMAn) is set to 1.
Page 522 • When the RXEn bit is 0, write to the transfer buffer RAM is not possible. DIRn Specification of transfer data direction MSB first LSB first Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 523 BRGCAn, ADTPn, ADTIn, SIOAn registers is prohibited. However, the transfer buffer RAM can be rewritten. 3. When writing to bits 1 to 5, always write 0. Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 524 Even when ATSTAn = 1, automatic data transfer does not start until 1 byte has been transferred. 1 is held until immediately before the INTCSIAn interrupt signal is generated. Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 525 This register can be set by an 8-bit memory manipulation instruction. However, when the TSFn bit of serial status register n (CSISn) is 1, rewriting the ADTPn register is prohibited. In the V850ES/KF1, V850ES/KG1, and V850ES/KJ1, 00H to 1FH can be specified because 32 bytes of buffer RAM are incorporated.
Page 526 CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION The relationship between buffer RAM address values and the ADTPn register setting values is shown below. Table 17-6. Relationship Between Buffer RAM Address Values and ADTP0 Register Setting Values Buffer RAM Address Value ADTP0 Register Setting Value Buffer RAM Address Value...
Page 527 (CSISn) is 1, rewriting the ADTIn register is prohibited. After reset: 00H Address: FFFFFD45H, FFFFD55H ADTIn ADTIn5 ADTIn4 ADTIn3 ADTIn2 ADTIn1 ADTIn0 Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 528 ADTPn and ADTCn registers, and then repeated transmission/reception is started. • When automatic transmission/reception is terminated, the TSFn bit is cleared to 0. Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) (3) Automatic transmission/reception communication operation (a) Automatic transmission/reception mode Automatic transmission/reception can be performed using buffer RAM.
Page 529 2. When the TSFn bit is cleared, the SOAn pin becomes low level. Remarks 1. CSIAFn: Interrupt request flag TSFn: Bit n of serial status register n (CSISn) 2. n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 530 CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Figure 17-6. Automatic Transmission/Reception Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTPn to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the transmission/reception...
Page 531 SIOAn Transmit data 5 (T5) ADTPn Transmit data 4 (T4) Transmit data 3 (T3) ADTCn Transmit data 2 (T2) FA00H Transmit data 1 (T1) CSIAFn Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 532 SIOAn Receive data 5 (R5) ADTPn Receive data 4 (R4) Receive data 3 (R3) ADTCn Receive data 2 (R2) FA00H Receive data 1 (R1) CSIAFn Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 533 2. When the TSFn bit is cleared, the SOAn pin becomes low level. Remarks 1. CSIAFn: Interrupt request flag TSFn: Bit 0 of serial status register n (CSISn) 2. n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 534 Bit 0 of serial trigger register n (CSITn) SIOAn: Serial I/O shift register n ADTCn: Automatic data transfer address count register n TSFn: Bit 0 of serial status register n (CSISn) Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 535 SIOAn Transmit data 5 (T5) ADTPn Transmit data 4 (T4) Transmit data 3 (T3) ADTCn Transmit data 2 (T2) FA00H Transmit data 1 (T1) CSIAFn Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 536 SIOAn Transmit data 5 (T5) ADTPn Transmit data 4 (T4) Transmit data 3 (T3) ADTCn Transmit data 2 (T2) FA00H Transmit data 1 (T1) CSIAFn Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 537 As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon automatic data transfer interval specification register n (ADTIn) (see (4) Automatic transmit/receive interval time). Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 538 Automatic data transfer interval specification register n ATSTAn: Bit 0 of serial trigger register n (CSITn) SIOAn: Serial I/O shift register n ADTCn: Automatic data transfer address count register n Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 539 SIOAn Transmit data 5 (T5) ADTPn Transmit data 4 (T4) Transmit data 3 (T3) ADTCn Transmit data 2 (T2) FA00H Transmit data 1 (T1) CSIAFn Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 540 SIOAn Transmit data 5 (T5) ADTPn Transmit data 4 (T4) Transmit data 3 (T3) ADTCn Transmit data 2 (T2) FA00H Transmit data 1 (T1) CSIAFn Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 541 Figure 17-14. Format of CSIAn Transmit/Receive Data (a) MSB-first (DIRn bit = 0) SCKAn SIAn SOAn (b) LSB-first (DIRn bit = 1) SCKAn SIAn SOAn Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 542 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ATSTPn: Bit 1 of serial trigger register n (CSITn) ATSTAn: Bit 0 of CSITn Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 543 D7 D6 D5 D4 D3 D2 D1 D0 SIAn D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CSIAFn ACSIIF: Interrupt request flag Remark n = 0 (V850ES/KF1) n = 0, 1 (V850ES/KG1, V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 544 C bus function, set the P38/SDA0, P39/SCL0, P80/SDA1, and P81/SCL1 pins to N-ch open drain output. The number of I C bus channels incorporated differs as follows depending on the product. Product Name V850ES/KF1 V850ES/KG1 V850ES/KJ1 Number of channels 1 channel (I...
Page 545 Since the SCLn and SDAn pins are N-ch open drain outputs, the I Cn requires pull-up resistors for the serial clock line and the serial data bus line. Remark n = 0 (V850ES/KF1, V850ES/KG1) n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 546 CLDn DADn SMCn DFCn CLn1 CLn0 CLXn STCFn IICBSYn STCENn IICRSVn IIC clock selection IIC function expansion IIC flag register n (IICCLn) register n (IICXn) register n (IICFn) Internal bus Remark n = 0 (V850ES/KF1, V850ES/KG1) n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 547 CHAPTER 18 I C BUS A serial bus configuration example is shown below. Figure 18-3. Serial Bus Configuration Example Using I C Bus Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2 Slave CPU3 Address 3 Slave IC...
Page 548 IIC clock selection registers 0 and 1 (IICCL0, IICCL1) IIC function expansion registers 0 and 1 (IICX0, IICX1) Remark n = 0 (V850ES/KF1, V850ES/KG1) n = 0, 1 (V850ES/KJ1) IIC shift registers 0 and 1 (IIC0, IIC1) IICn is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8-bit serial data.
Page 549 CHAPTER 18 I C BUS (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I C interrupt is generated following either of two triggers. • Eighth or ninth clock of the serial clock (set by WTIMn bit Note Note •...
Page 550: Control Registers
IICCn is used to enable/disable I Cn operations, set wait timing, and set other I C operations. IICCn can be set by an 8-bit or 1-bit memory manipulation instruction (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). RESET input clears IICCn to 00H.
Page 551 CHAPTER 18 I C BUS (1/4) After reset: 00H Address: FFFFFD82H, FFFFFD92H <7> <6> IICCn IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn (n = 0, 1) IICEn Cn operation enable/disable specification Stops operation. Presets IIC status register n (IICSn). Stops internal operation. Enables operation.
Page 552 CHAPTER 18 I C BUS (2/4) WRELn Wait cancellation control Does not cancel wait Cancels wait. This setting is automatically cleared after wait is canceled. Note Condition for clearing (WRELn = 0) Condition for setting (WRELn = 1) • Automatically cleared after execution •...
Page 553 CHAPTER 18 I C BUS (3/4) ACKEn Acknowledge control Disable acknowledge. Enable acknowledge. During the ninth clock period, the SDAn line is set to low level. However, the ACK is invalid during address transfers and is valid when EXCn = 1. Note Condition for clearing (ACKEn = 0) Condition for setting (ACKEn = 1)
Page 554 CHAPTER 18 I C BUS (4/4) SPTn Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDAn line goes to low level, either set the SCLn line to high level or wait until it goes to high level.
Page 555 IICSn indicates the status of the I Cn bus. IICSn can be set by an 8-bit or 1-bit memory manipulation instruction. IICSn is a read-only register (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). RESET input sets IICSn to 00H. (1/3)
Page 556 CHAPTER 18 I C BUS (2/3) EXCn Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXCn = 0) Condition for setting (EXCn = 1) • When a start condition is detected •...
Page 557 CHAPTER 18 I C BUS (3/3) ACKDn Detection of ACK ACK was not detected. ACK was detected. Condition for clearing (ACKDn = 0) Condition for setting (ACKDn = 1) • When a stop condition is detected • After the SDAn line is set to low level at the rising edge •...
Page 558 (3) IIC flag registers 0, 1 (IICF0, IICF1) IICFn is used for I Cn control and as flags. IICFn is set with an 8-bit or 1-bit memory manipulation instruction (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). RESET input sets IICFn to 00H.
Page 559 CHAPTER 18 I C BUS (2/2) STCENn Initial start enable trigger After operation is enabled (IICEn = 1), generates a start condition upon detection of a stop condition. After operation is enabled (IICEn = 1), generates a start condition without detecting a stop condition. Condition for clearing (STCEn = 0) Condition for setting (STCEn = 1) •...
Page 560 IICCLn can be set by an 8-bit or 1-bit memory manipulation instruction. Bits SMCn, CLn1 and CLn0 are set in combination with CLXn bit of IIC function expansion register n (IICXn) (see 18.4 (6) I Cn transfer clock setting method) (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). RESET input clears IICCLn to 00H. Note...
Page 561 SMCn, CLn1, and CLn0 bits of IIC clock selection register n (IICCLn) (see 18.4 (6) I Cn transfer clock setting method) (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). RESET input clears these registers to 00H. After reset: 00H...
Page 562 (SMCn = 0) 4.00 MHz to 4.19 MHz Setting prohibited Remarks 1. n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) 2. x: Don’t care (7) IIC shift registers 0, 1 (IIC0, IIC1) IICn is used for serial transmission/reception (shift operations) that is synchronized with the serial clock. It can be read from or written to in 8-bit units, but data should not be written to IICn during a data transfer (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)).
Page 563 18.5 Functions 18.5.1 Pin configuration The serial clock pin (SCLn) and serial data bus pin (SDAn) are configured as follows (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). SCLn ....This pin is used for serial clock input and output.
Page 564 8-bit data). The serial clock (SCLn) is continuously output by the master device. However, in the slave device, the SCLn’s low-level period can be extended and a wait can be inserted (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)).
Page 565 (SVAn). If the address data matches the SVAn values, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). Figure 18-7. Address...
Page 566 Transfer direction specification Note INTIICn Note The interrupt request signal (INTIICn) is generated if a local address or extension code is received during slave device operation. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 567 SCLn’s eighth clock regardless of the ACKEn value. No ACK signal is output if the received address is not a local address (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). The ACK signal output method during data reception is based on the wait timing setting, as described below.
Page 568 When the SCLn pin is at high level, changing the SDAn pin from low level to high level generates a stop condition (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed.
Page 569 Setting the SCLn pin to low level notifies the communication partner of the wait status. When wait status has been canceled for both the master and slave devices, the next data transfer can begin (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)).
Page 570 Bit 2 of IIC control register n (IICCn) WRELn: Bit 5 of IIC control register n (IICCn) 2. n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) A wait may be automatically generated depending on the setting for bit 3 (WTIMn) of IIC control register n (IICCn).
Page 571: C Interrupt Requests (Intiicn)
C Interrupt Requests (INTIICn) The following shows the value of IIC status register n (IICSn) at the INTIICn interrupt request generation timing and at the INTIICn interrupt timing (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). 18.7.1 Master device operation (1) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1>...
Page 572 ∆ 7: IICSn = 00000001B L: Always generated Remark ∆: Generated only when SPIEn = 1 X: Don’t care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) <2> When WTIMn = 1 STTn = 1 SPTn = 1 ↓...
Page 573 ∆ 5: IICSn = 00000001B L: Always generated Remark ∆: Generated only when SPIEn = 1 X: Don’t care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) <2> When WTIMn = 1 SPTn = 1 ↓ AD6 to AD0...
Page 574 ∆ 4: IICSn = 00000001B L: Always generated Remark ∆: Generated only when SPIEn = 1 X: Don’t care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) <2> When WTIMn = 1 AD6 to AD0 D7 to D0 D7 to D0 ∆4...
Page 575 L: Always generated Remark ∆: Generated only when SPIEn = 1 X: Don’t care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) <2> When WTIMn = 1 (after restart, match with SVAn) AD6 to AD0 D7 to D0...
Page 576 L: Always generated Remark ∆: Generated only when SPIEn = 1 X: Don’t care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) <2> When WTIMn = 1 (after restart, extension code reception) AD6 to AD0 D7 to D0...
Page 577 Remark ∆: Generated only when SPIEn = 1 X: Don’t care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) <2> When WTIMn = 1 (after restart, mismatch with address (= not extension code)) AD6 to AD0 D7 to D0...
Page 578 ∆ 4: IICSn = 00000001B L: Always generated Remark ∆: Generated only when SPIEn = 1 X: Don’t care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) <2> When WTIMn = 1 AD6 to AD0 D7 to D0 D7 to D0 ∆5...
Page 579 L: Always generated Remark ∆: Generated only when SPIEn = 1 X: Don’t care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) <2> When WTIMn = 1 (after restart, match with SVAn) AD6 to AD0 D7 to D0...
Page 580 L: Always generated Remark ∆: Generated only when SPIEn = 1 X: Don’t care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) <2> When WTIMn = 1 (after restart, extension code reception) AD6 to AD0 D7 to D0...
Page 581 Remark ∆: Generated only when SPIEn = 1 X: Don’t care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) <2> When WTIMn = 1 (after restart, mismatch with address (= not extension code)) AD6 to AD0 D7 to D0...
Page 582 ∆ 1: IICSn = 00000001B ∆: Generated only when SPIEn = 1 Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) 18.7.5 Arbitration loss operation (operation as slave after arbitration loss) (1) When arbitration loss occurs during transmission of slave address data <1>...
Page 583 ∆ 4: IICSn = 00000001B L: Always generated Remark ∆: Generated only when SPIEn = 1 X: Don’t care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) <2> When WTIMn = 1 AD6 to AD0 D7 to D0 D7 to D0 ∆5...
Page 584 ∆ 2: IICSn = 00000001B L: Always generated Remark ∆: Generated only when SPIEn = 1 n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) (2) When arbitration loss occurs during transmission of extension code AD6 to AD0 D7 to D0 D7 to D0 ∆2...
Page 585 ∆ 3: IICSn = 00000001B L: Always generated Remark ∆: Generated only when SPIEn = 1 n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) <2> When WTIMn = 1 AD6 to AD0 D7 to D0 D7 to D0 ∆3...
Page 586 L: Always generated Remark ∆: Generated only when SPIEn = 1 X: Don’t care Dn = D6 to D0 n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) <2> Extension code AD6 to AD0 D7 to Dn AD6 to AD0 D7 to D0 ∆3...
Page 587 ∆: Generated only when SPIEn = 1 X: Don’t care Dn = D6 to D0 n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) (6) When arbitration loss occurs due to low-level data when attempting to generate a restart condition When WTIMn = 1 STTn = 1 ↓...
Page 588 ∆: Generated only when SPIEn = 1 X: Don’t care n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) (8) When arbitration loss occurs due to low-level data when attempting to generate a stop condition When WTIMn = 1 SPTn = 1 ↓...
Page 589: Interrupt Request (Intiicn) Generation Timing And Wait Control
Remarks 1. The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and wait control are both synchronized with the falling edge of these clock signals. 2. n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) (1) During address transmission/reception •...
Page 590: Address Match Detection Method
(SVAn) and when the address set to SVAn matches the slave address sent by the master device, or when an extension code has been received (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)).
Page 591 ), communication among the master devices is performed as the number of clocks is adjusted until the data differs. This kind of operation is called arbitration (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)). When one of the master devices loses in arbitration, an arbitration loss flag (ALDn) in IIC status register n (IICSn) is set via the timing by which the arbitration loss occurred, and the SCLn and SDAn lines are both set for high impedance, which releases the bus.
Page 592: Wakeup Function
However, when a stop condition is detected, bit 5 (SPIEn) of IIC control register n (IICCn) is set regardless of the wake up function, and this determines whether interrupt requests are enabled or disabled (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)).
Page 593: Communication Reservation
3, 1, and 0 (SMCn, CLn1, and CLn0) in IIC clock selection register n (IICCLn). Table 18-6. Wait Periods SMCn CLn1 CLn0 Wait Period 26 clocks 46 clocks 92 clocks 37 clocks 16 clocks 32 clocks 13 clocks Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 594 (IICSn) is set to 1, a communication reservation can be made by setting bit 1 (STTn) of IIC control register n (IICCn) to 1 before a stop condition is detected (n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1)).
Page 595 ; IICn write operation Note The communication reservation operation executes a write to IIC shift register n (IICn) when a stop condition interrupt request occurs. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 596 (a) Set IIC clock selection register n (IICCLn). (b) Set bit 7 (IICEn) of IIC control register n (IICCn). (c) Set bit 0 of IICCn. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 597 Start reception. INTIICn = 1? INTIICn = 1? Data processing Data processing ACKDn = 1? Transfer completed? Generate restart condition or stop condition. ACKEn = 0 Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 598 INTIICn = 1? INTIICn = 1? Data processing Data processing ACKDn = 1? Reception completed? ACKEn = 0 (Restart) Transfer completed? SPTn = 1 Stop condition generated Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 599 Start reception. INTIICn = 1? INTIICn = 1? Data processing Data processing ACKDn = 1? Transfer completed? Detect restart condition ACKEn = 0 or stop condition. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 600: Timing Of Data Communication
SO latch and is output (MSB first) via the SDAn pin. Data input via the SDAn pin is captured by IICn at the rising edge of SCLn. The data communication timing is shown below. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 601 ACKEn MSTSn STTn SPTn Note WRELn INTIICn (When EXCn = 1) TRCn Receive Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 602 STDn SPDn WTIMn ACKEn MSTSn STTn SPTn Note Note WRELn INTIICn TRCn Receive Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 603 MSTSn STTn SPTn Note Note WRELn INTIICn (When SPIEn = 1) TRCn Receive Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 604 IICn data ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn Note To cancel master wait, write FFH to IICn or set WRELn. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 605 IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn Transmit Note To cancel master wait, write FFH to IICn or set WRELn. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 606 SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn Note To cancel master wait, write FFH to IICn or set WRELn. Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 607: Chapter 19 Interrupt/Exception Processing Function
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.1 Overview The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are provided with a dedicated interrupt controller (INTC) for interrupt servicing and realize a high-powered interrupt function that can service interrupt requests from a total of 33 to 45 sources.
Page 608 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-1. Interrupt Source List (V850ES/KF1) (1/2) Classification Default Interrupt Exception Type Name Trigger Handler Restored Interrupt S o urce C ode Priority Address Control Register 00000000H U ndefined Reset Interrupt – RESET RESET pin input 0000H –...
Page 609 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-1. Interrupt Source List (V850ES/KF1) (2/2) Classification Default Interrupt Exception Type Name Trigger Handler Restored Interrupt S o urce C ode Priority Address Control Register Maskable Interrupt INTST0 UART0 transmission UART0 01A0H 000001AH nextPC...
Page 610 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-2. Interrupt Source List (V850ES/KG1) (1/2) Classification Default Interrupt Exception Type Name Trigger Handler Restored Interrupt S o urce C ode Priority Address Control Register 00000000H U ndefined Reset Interrupt – RESET RESET pin input 0000H –...
Page 611 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-2. Interrupt Source List (V850ES/KG1) (2/2) Classification Default Interrupt Exception Type Name Trigger Handler Restored Interrupt S o urce C ode Priority Address Control Register Maskable Interrupt INTST0 UART0 transmission UART0 01A0H 000001AH nextPC STIC0 completion INTSRE1...
Page 612 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-3. Interrupt Source List (V850ES/KJ1) (1/2) Classification Default Interrupt Exception Type Name Trigger Handler Restored Interrupt S o urce C ode Priority Address Control Register 00000000H U ndefined Reset Interrupt – RESET RESET pin input 0000H –...
Page 613 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-3. Interrupt Source List (V850ES/KJ1) (2/2) Classification Default Interrupt Exception Type Name Trigger Handler Restored Interrupt S o urce C ode Priority Address Control Register Maskable Interrupt INTSRE1 UART1 reception error UART1 01B0H 000001B0H nextPC SREIC1 occurrence INTSR1...
Page 614: Non-Maskable Interrupts
Non-maskable interrupt requests are acknowledged unconditionally, even when interrupts are disabled (DI state). Non-maskable interrupts (NMI) are not subject to priority control and take precedence over all other interrupt requests. The following three types of non-maskable interrupt requests are available in the V850ES/KF1, V850ES/KG1, and V850ES/KJ1.
Page 615 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-1. Acknowledging Non-Maskable Interrupt Requests (1/2) (a) If two or more NMI requests are simultaneously generated · NMI and INTWDT1 requests simultaneously generated · NMI and INTWDT2 requests simultaneously generated Main routine Main routine INTWDT1 INTWDT2 processing...
Page 616 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-1. Acknowledging Non-Maskable Interrupt Requests (2/2) (b) If a new NMI request is generated during a non-maskable interrupt servicing Non-maskable Non-maskable interrupt request newly generated during non-maskable interrupt servicing interrupt currently INTWDT1 INTWDT2 being serviced ·...
Page 617 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.2.1 Operation Upon generation of a non-maskable interrupt request, the CPU performs the following processing and transfers control to a handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3>...
Page 618 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.2.2 Restore Execution is restored from non-maskable interrupt servicing by the RETI instruction. (1) In case of NMI Restore from NMI processing is done with the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC.
Page 619 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt servicing is in progress. This flag is set when a non-maskable interrupt request has been acknowledged, and masks all non-maskable requests to prevent multiple interrupts.
Page 620 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.2.5 Edge detection function for NMI pin The NMI valid edge can be selected from the following four types: falling edge, rising edge, both edges, and no edge detection. Rising edge specification register 0 (INTR0) and falling edge specification register 0 (INTF0) specify the valid edge of non-maskable interrupts (NMI).
Page 621 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-4. NMI Valid Edge Specification INTF02 INTR02 NMI Valid Edge Specification No edge detection Rising edge Falling edge Both edges User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 622: Maskable Interrupts
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 have 33 to 45 maskable interrupt sources (refer to 19.1.1 Features). If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 623 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-4. Maskable Interrupt Servicing INT input Interrupt mask released? Priority higher than INTC acknowledged that of interrupt currently being serviced? Priority higher than that of other interrupt requests? Highest default priority of interrupt requests with the same priority? Maskable interrupt request Interrupt request pending...
Page 624 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.2 Restore Execution is restored from maskable interrupt servicing by the RETI instruction. Operation of RETI instruction When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. (1) Loads the values of the restored PC and PSW from EIPC and EIPSW because the EP bit and NP bit of the PSW are both 0.
Page 625 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.3 Priorities of maskable interrupts The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 provide a multiple interrupt servicing in which an interrupt can be acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels.
Page 626 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-6. Example of Interrupt Nesting (1/2) Main routine Servicing of a Servicing of b Interrupt request a Interrupt request b Interrupt request b is acknowledged (level 3) (level 2) because the priority of b is higher than that of a and interrupts are enabled.
Page 627 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-6. Example of Interrupt Nesting (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k priority is lower than that of i.
Page 628 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-7. Example of Servicing Simultaneously Generated Interrupt Requests Main routine Interrupt request a (level 2) Note 1 Interrupt request b (level 1) ·Interrupt requests b and c are Servicing of interrupt Note 2 Interrupt request c (level 1) acknowledged first according to their request b priorities.
Page 629 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.4 Interrupt control register (xxlCn) An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. The interrupt control registers can be read/written in 8-bit or 1-bit units. Caution Be sure to read the xxIFn bit of the xxICn register while interrupts are disabled (DI).
Page 630 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-5. Interrupt Control Registers (xxlCn) (V850ES/KF1) Address Register Bits <7> <6> FFFFF110H WDT1IC WDT1IF WDT1MK WDT1PR2 WDT1PR1 WDT1PR0 FFFFF112H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF114H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF116H PIC2...
Page 631 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-6. Interrupt Control Registers (xxlCn) (V850ES/KG1) Address Register Bits <7> <6> FFFFF110H WDT1IC WDT1IF WDT1MK WDT1PR2 WDT1PR1 WDT1PR0 FFFFF112H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF114H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF116H PIC2 PIF2 PMK2 PPR22...
Page 632 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-7. Interrupt Control Registers (xxlCn) (V850ES/KJ1) (1/2) Address Register Bits <7> <6> FFFFF110H WDT1IC WDT1IF WDT1MK WDT1PR2 WDT1PR1 WDT1PR0 FFFFF112H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF114H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF116H PIC2 PIF2 PMK2...
Page 633 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-7. Interrupt Control Registers (xxlCn) (V850ES/KJ1) (2/2) Address Register Bits <7> <6> FFFFF162H SREIC2 SREIF2 SREMK2 SREPR22 SREPR21 SREPR20 FFFFF164H SRIC2 SRIF2 SRMK2 SRPR22 SRPR21 SRPR20 FFFFF166H STIC2 STIF2 STMK2 STPR22 STPR21 STPR20 Note FFFFF168H IICIC1 IICIF1...
Page 634 Caution In the device file, the xxMKn bit of the xxICn register is defined as a reserved word. Therefore, if bit manipulation is performed using the name xxMKn, the xxICn register, not the IMRm register, is rewritten (as a result, the IMRm register is also rewritten). (i) V850ES/KF1 After reset: FFFFH Address: FFFFF100H (IMR0, IMR0L), FFFFF101H (IMR0H)
Page 635 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (ii) V850ES/KG1 After reset: FFFFH Address: FFFFF100H (IMR0, IMR0L), FFFFF101H (IMR0H) Note IMR0 (IMR0H CSI0MK1 CSI0MK0 TM5MK1 TM5MK0 TM0MK11 TM0MK10 TM0MK01 TM0MK00 (IMR0L) PMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 WDT1MK After reset: FFFFH Address: FFFFF102H (IMR1, IMR1L), FFFFF103H (IMR1H) Note IMR1 (IMR1H TM0MK20...
Page 636 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (iii) V850ES/KJ1 After reset: FFFFH Address: FFFFF100H (IMR0, IMR0L), FFFFF101H (IMR0H) Note IMR0 (IMR0H CSI0MK1 CSI0MK0 TM5MK1 TM5MK0 TM0MK11 TM0MK10 TM0MK01 TM0MK00 (IMR0L) PMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 WDT1MK After reset: FFFFH Address: FFFFF102H (IMR1, IMR1L), FFFFF103H (IMR1H) Note IMR1 (IMR1H TM0MK20...
Page 637 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently being acknowledged. When the interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set (1) and remains set while the interrupt is being serviced.
Page 638 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.7 Maskable interrupt status flag The interrupt disable flag (ID) is allocated to the PSW and controls the maskable interrupt’s operating state, and stores control information regarding enabling/disabling reception of interrupt requests. After reset: 00000020H ID SAT CY OV Note Maskable interrupt servicing specification...
Page 639 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.8 Watchdog timer mode register 1 (WDTM1) This register is a special register that can be written to only in a special sequence. To generate a maskable interrupt (INTWDT1), set the WDTM14 bit to 0. This register can be read/written in 8-bit or 1-bit units (for details, refer to CHAPTER 12 WATCHDOG TIMER FUNCTIONS).
Page 640 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.10 INTP0 to INTP6 edge detection function The valid edges of the INTP0 to INTP6 pins can be selected from the following four types. • Rising edge • Falling edge • Both edges • No edge detection (1) External interrupt rising edge specification register 0 (INTR0) This is an 8-bit register that specifies detection of the rising edge of the INTP0 to INTP3 pins.
Page 641 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-8. INTP0 to INTP3 Pins Valid Edge Specification INTF0n INTR0n Valid edge specification (n = 3 to 6) No edge detection Rising edge Falling edge Both edges Remark n = 3 to 6: Control of INTP0 to INTP3 pins (3) External interrupt rising edge specification register 9H (INTR9H) This is an 8-bit register that specifies detection of the rising edge of the INTP4 to INTP6 pins.
Page 642 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-9. INTP4 to INTP6 Pins Valid Edge Specification INTF9n INTR9n Valid edge specification (n = 13 to 15) No edge detection Rising edge Falling edge Both edges Remark n = 13 to 15: Control of INTP4 to INTP6 pins User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 643: Software Exceptions
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.4 Software Exceptions A software exception is generated when the CPU executes the TRAP instruction. Software exceptions can always be acknowledged. 19.4.1 Operation If a software exception occurs, the CPU performs the following processing and transfers control to a handler routine.
Page 644 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.4.2 Restore Execution is restored from software exception processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. <1>...
Page 645 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.4.3 Exception status flag (EP) The EP flag, which is bit 6 of the PSW, is a status flag that indicates that exception processing is in progress. It is set when an exception occurs. After reset: 00000020H NP EP ID SAT CY OV Exception processing status...
Page 646: Exception Trap
The exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/KF1, V850ES/KG1, and V850ES/KJ1, an illegal op code trap (ILGOP: illegal OP code trap) is considered as an exception trap.
Page 647 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-10. Exception Trap Processing Exception trap (ILGOP) occurs DBPC Restored PC DBPSW PSW.NP PSW.EP CPU processing PSW.ID 00000060H Exception processing (2) Restore Execution is restored from exception trap processing by the DBRET instruction. When the DBRET instruction is executed, the CPU performs the following processing and transfers control to the address of the restored <1>...
Page 648 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.5.2 Debug trap A debug trap is an exception that occurs upon execution of the DBTRAP instruction and that can be acknowledged at all times. When a debug trap occurs, the CPU performs the following processing. (1) Operation <1>...
Page 649 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restore Execution is restored from debug trap processing by the DBRET instruction. When the DBRET instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. <1>...
Page 650: Multiple Interrupt Servicing Control
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.6 Multiple Interrupt Servicing Control Multiple interrupt servicing control is a function that stops an interrupt service routine currently in progress if a higher priority interrupt request is generated, and processes the acknowledgement operation of the higher priority interrupt.
Page 651 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) To generate exception in service program Service program for maskable interrupt or exception … … • EIPC saved to memory or register • EIPSW saved to memory or register … • TRAP instruction ←Acknowledges exceptions such as TRAP instruction. …...
Page 652: Interrupt Response Time
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.7 Interrupt Response Time Except in the following cases, the CPU interrupt response time is a minimum of 4 clocks. If inputting consecutive interrupt requests, at least 4 clocks must be placed between each interrupt. •...
Page 653: Periods In Which Interrupts Are Not Acknowledged By Cpu
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.8 Periods in Which Interrupts Are Not Acknowledged by CPU Interrupts are acknowledged by the CPU while an instruction is being executed. However, no interrupt is acknowledged between an interrupt request non-sample instruction and the next instruction. The following instructions are interrupt request non-sample instructions.
Page 654: Chapter 20 Key Interrupt Function
CHAPTER 20 KEY INTERRUPT FUNCTION 20.1 Function A key interrupt (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the key return mode register (KRM). Table 20-1. Assignment of Key Return Detection Pins Flag Pin Description KRM0...
Page 655 CHAPTER 20 KEY INTERRUPT FUNCTION 20.2 Key Interrupt Control Register (1) Key return mode register (KRM) The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals. This register can be read/written in 8-bit or 1-bit units. RESET input clears KRM to 00H.
Page 656: Chapter 21 Standby Function
CHAPTER 21 STANDBY FUNCTION 21.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 21-1. Table 21-1.
Page 657 CHAPTER 21 STANDBY FUNCTION Figure 21-1. Status Transition (1/2) Normal operation mode (operation with main clock) End of oscillation End of oscillation stabilization time count stabilization time count Note 3 Setting of HALT mode Interrupt request End of oscillation stabilization time count Wait for stabilization Wait for stabilization of oscillation...
Page 658 CHAPTER 21 STANDBY FUNCTION Figure 21-1. Status Transition (2/2) Normal operation mode (operation with main clock) End of oscillation End of oscillation stabilization time count stabilization time count Setting of subclock operation mode Wait for stabilization Wait for stabilization of oscillation of oscillation Setting of normal operation mode...
Page 659: Halt Mode
CHAPTER 21 STANDBY FUNCTION 21.2 HALT Mode 21.2.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues.
Page 660 CHAPTER 21 STANDBY FUNCTION Table 21-3. Operation Status in HALT Mode Setting of HALT Mode When CPU Is Operating with Main Clock Item When Subclock Is Not Used When Subclock Is Used Stops operation ROM correction Stops operation Main clock oscillator Oscillation enabled −...
Page 661: Idle Mode
CHAPTER 21 STANDBY FUNCTION 21.3 IDLE Mode 21.3.1 Setting and operation status The IDLE mode is set by clearing the PSM bit of the power save mode register (PSMR) to 0 and setting the STP bit of the power save control register (PSC) to 1 in the normal operation mode. In the IDLE mode, the clock oscillator continues operation but clock supply to the CPU and other on-chip peripheral functions stops.
Page 662 CHAPTER 21 STANDBY FUNCTION (2) Releasing IDLE mode by RESET pin input The same operation as the normal reset operation is performed. Table 21-5. Operation Status in IDLE Mode Setting of IDLE Mode When CPU Is Operating with Main Clock Item When Subclock Is Not Used When Subclock Is Used...
Page 663: Stop Mode
CHAPTER 21 STANDBY FUNCTION 21.4 STOP Mode 21.4.1 Setting and operation status The STOP mode is set when the PSM bit of the power save mode register (PSMR) is set to 1 and the STP bit of the power save control register (PSC) is set to 1 in the normal operation mode. In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops.
Page 664 CHAPTER 21 STANDBY FUNCTION (2) Releasing STOP mode by RESET pin input The same operation as the normal reset operation is performed. Table 21-7. Operation Status in STOP Mode Setting of STOP When CPU Is Operating with Main Clock Mode Item When Subclock Is Not Used When Subclock Is Used...
Page 665 CHAPTER 21 STANDBY FUNCTION 21.5 Securing Oscillation Stabilization Time When the STOP mode is released, only the oscillation stabilization time set by the oscillation stabilization time selection register (OSTS) elapses. If the software STOP mode has been released by RESET pin input, however, the reset value of the OSTS register, 2 (8.192 ms at f = 4 kHz) elapses.
Page 666: Subclock Operation Mode
CHAPTER 21 STANDBY FUNCTION 21.6 Subclock Operation Mode 21.6.1 Setting and operation status The subclock operation mode is set when the CK3 bit of the processor clock control register (PCC) is set to 1 in the normal operation mode. When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock.
Page 667 CHAPTER 21 STANDBY FUNCTION Table 21-8. Operation Status in Subclock Operation Mode Setting of Subclock Operation Status Operation Mode When Main Clock Is Oscillating When Main Clock Is Stopped Item Operable ROM correction Operable Subclock oscillator Oscillation enabled Interrupt controller Operable 16-bit timers (TM00 to TM05) Operable...
Page 668: Sub-Idle Mode
CHAPTER 21 STANDBY FUNCTION 21.7 Sub-IDLE Mode 21.7.1 Setting and operation status The sub-IDLE mode is set when the PSM bit of the power save mode register (PSMR) is cleared to 0 and the STP bit of the power save control register (PSC) is set to 1 in the subclock operation mode. In this mode, the clock oscillator continues operation but clock supply to the CPU and the other on-chip peripheral functions is stopped.
Page 669 CHAPTER 21 STANDBY FUNCTION Table 21-10. Operation Status in Sub-IDLE Mode Setting of Sub-IDLE Mode Operation Status Item When Main Clock Is Oscillating When Main Clock Is Stopped Stops operation ROM correction Stops operation Subclock oscillator Oscillation enabled Interrupt controller Stops operation 16-bit timers (TM00 to TM05) Stops operation...
Page 670: Control Registers
CHAPTER 21 STANDBY FUNCTION 21.8 Control Registers (1) Power save control register (PSC) This is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the STOP mode. The PSC register is a special register (refer to 3.4.7 Special registers). Data can be written to this register only in a specific sequence so that its contents are not rewritten by mistake due to a program hang-up.
Page 671: Chapter 22 Reset Function
CHAPTER 22 RESET FUNCTION 22.1 Overview The following reset functions are available. • Reset function by RESET pin input • Reset function by overflow of watchdog timer 1 (WDTRES1) • Reset function by overflow of watchdog timer 2 (WDTRES2) If the RESET pin goes high, the reset status is released, and the CPU starts executing the program. Initialize the contents of each register in the program as necessary.
Page 672: Operation
CHAPTER 22 RESET FUNCTION 22.3 Operation The system is reset, initializing each hardware unit, when a low level is input to the RESET pin or if watchdog timer 1 or watchdog timer 2 overflows (WDTRES1 or WDTRES2). While a low level is being input to the RESET pin, the main clock oscillator stops. Therefore, the overall power consumption of the system can be reduced.
Page 673 CHAPTER 22 RESET FUNCTION Table 22-1. Hardware Status on RESET Pin Input or Occurrence of WDTRES2 Item During Reset After Reset Main clock oscillator (f Oscillation stops (f = 0 level). Oscillation starts Note Subclock oscillator (f Oscillation can continue without effect from reset Peripheral clock (f to f /1024), internal...
Page 674 CHAPTER 22 RESET FUNCTION Figure 22-2. Hardware Status on RESET Input Initialized to f /8 operation RESET Analog delay Analog Analog delay Analog (eliminated as noise) delay (eliminated as noise) delay Internal system reset signal Oscillation stabilization time count Overflow of timer for oscillation stabilization Figure 22-3.
Page 675 CHAPTER 23 REGULATOR 23.1 Overview The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 include a regulator to reduce the power consumption and noise. This regulator supplies a stepped-down V power supply voltage to the oscillator block and internal logic circuits (except the A/D converter, D/A converter, and output buffer). The regulator output voltage is set to 3.6 V (TYP.).
Page 676 CHAPTER 23 REGULATOR Figure 23-2. REGC Pin Connection (a) When REGC = V Input voltage = 2.7 to 5.5 V Voltage supply to oscillator/internal logic = 2.7 to 5.5 V REGC (b) When connecting REGC pin to V via a capacitor Input voltage = 4.0 to 5.5 V Voltage supply to oscillator/internal logic = 3.6 V REGC...
Page 677: Chapter 24 Rom Correction Function
CHAPTER 24 ROM CORRECTION FUNCTION 24.1 Overview The ROM correction function is used to replace part of the program in the mask ROM with the program of an external RAM or the internal RAM. By using this function, instruction bugs found in the mask ROM can be corrected at up to four places. Figure 24-1.
Page 678 CHAPTER 24 ROM CORRECTION FUNCTION 24.2 Control Registers 24.2.1 Correction address registers 0 to 3 (CORAD0 to CORAD3) These registers are used to set the first address (correction address) of the instruction to be corrected in the ROM. The program can be corrected at up to four places because four correction address register n (CORADn) are provided (n = 0 to 3).
Page 679: Rom Correction Operation And Program Flow
CHAPTER 24 ROM CORRECTION FUNCTION 24.2.2 Correction control register (CORCN) This register disables or enables the correction operation of correction address register n (CORADn) (n = 0 to 3). Each channel can be enabled or disabled by this register. This register is set by using an 8-bit or 1-bit memory manipulation instruction. After reset: 00H Address: FFFFF880H CORCN...
Page 680 CHAPTER 24 ROM CORRECTION FUNCTION Figure 24-2. ROM Correction Operation and Program Flow Reset & start Initialize microcontroller Read data for setting ROM correction from external memory Set CORADn register Set CORCN register Fetch address = CORADn Change fetch code to DBTRAP instruction Execute fetch code DBTRAP instruction...
Page 681: Chapter 25 Flash Memory
CHAPTER 25 FLASH MEMORY The following products are the on-chip flash memory versions of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1. (1) V850ES/KF1 µ PD70F3210, 70F3210Y: Products with 128 KB flash memory (2) V850ES/KG1 µ PD70F3214, 70F3214Y: Products with 128 KB flash memory (3) V850ES/KJ1 µ...
Page 682: Writing With Flash Programmer
Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) On-board programming The contents of the flash memory can be rewritten after the V850ES/KF1, V850ES/KG1, or V850ES/KJ1 has been mounted on the target system. The connectors that connect the dedicated flash programmer must be mounted on the target system.
Page 683 CHAPTER 25 FLASH MEMORY Figure 25-1. Wiring Example of V850ES/KF1 Flash Writing Adapter (FA-80GC-8BT, FA-80GK-9EU) µ PD70F3210, µ PD70F3210Y Connect to GND. Connect to VDD. Note /RESET RESERVE/HS Note Be sure to connect the REGC pin in either of the following ways.
Page 684 CHAPTER 25 FLASH MEMORY Table 25-2. Wiring Between µ µ µ µ PD70F3214 and 70F3214Y (V850ES/KG1), and PG-FP3 Pin Configuration of Flash Programmer (PG-FP3) With CSI00-HS With CSI00 With UART0 Signal Name Pin Function Pin Name Pin No. Pin Name Pin No.
Page 685 CHAPTER 25 FLASH MEMORY Figure 25-2. Wiring Example of V850ES/KG1 Flash Writing Adapter (FA-100GC-8EU) µ PD70F3214, µ PD70F3214Y Connect to GND. Connect to VDD. Note /RESET RESERVE/HS Note Be sure to connect the REGC pin in either of the following ways. •...
Page 686 CHAPTER 25 FLASH MEMORY Table 25-3. Wiring Between µ µ µ µ PD70F3217 and 70F3217Y (V850ES/KJ1), and PG-FP3 Pin Configuration of Flash Programmer (PG-FP3) With CIS00-HS With CSI00 With UART0 Signal Name Pin Function Pin Name Pin No. Pin Name Pin No.
Page 687 CHAPTER 25 FLASH MEMORY Figure 25-3. Wiring Example of V850ES/KJ1 Flash Writing Adapter (FA-144GJ-UEN) 104103 µ PD70F3217, µ PD70F3217Y Connect to GND. Connect to VDD. Note 8 9 10 11 12 13 14 23 24 /RESET RESERVE/HS Note Be sure to connect the REGC pin in either of the following ways. •...
Page 688: Programming Environment
CHAPTER 25 FLASH MEMORY 25.3 Programming Environment The environment required for writing a program to the flash memory of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 is illustrated below. Figure 25-4. Environment for Writing Program to Flash Memory RS-232-C Axxxx Bxxxxx Cxxxxxx...
Page 689 Bxxxxx Cxxxxxx STATVE RESET RESET PG-FP4 SO00 Dedicated flash programmer SI00 V850ES/KF1, V850ES/KG1, SCK00 V850ES/KJ1 (3) CSI communication mode supporting handshake Transfer rate: 200 kHz to 1 MHz (MSB first) Figure 25-7. Communication with Flash Programmer (CSI00+HS) Axxxx Bxxxxx Cxxxxxx...
Page 690 CHAPTER 25 FLASH MEMORY If the PG-FP3 is used as the flash programmer, the PG-PF3 generates the following signal for the V850ES/KF1, V850ES/KG1, and V850ES/KJ1. For details, refer to the PG-FP3 User's Manual (U13502E). Table 25-4. Signals Generated by Dedicated Flash Programmer (PG-FP3)
Page 691: Pin Processing
In the flash memory programming mode, a write voltage of 10.3 V is supplied to the V pin. An example of connection of the V pin is illustrated below. Figure 25-8. Example of Connection of V V850ES/KF1, V850ES/KG1, V850ES/KJ1 Flash programmer connection pin Pull-down resistor (R User’s Manual U15862EJ3V0UD...
Page 692 (output), signal collision takes place. To avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state. Figure 25-9. Signal Collision (Input Pin of Serial Interface) V850ES/KF1, V850ES/KG1, V850ES/KJ1...
Page 693 V850ES/KG1, V850ES/KJ1 Flash programmer connection pin Other device Input pin If the signal output by the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 in the flash memory programming mode affects the other device, isolate the signal of the other device. V850ES/KF1, V850ES/KG1, V850ES/KJ1...
Page 694 If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed. Do not input any signal other than the reset signal of the flash programmer. Figure 25-11. Signal Collision (RESET Pin) V850ES/KF1, V850ES/KG1, V850ES/KJ1 Flash programmer Signal collision...
Page 695: Programming Method
CHAPTER 25 FLASH MEMORY 25.6 Programming Method 25.6.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 25-12. Flash Memory Manipulation Procedure Start Flash memory programming RESET pulse supply mode is set Selecting communication mode Manipulate flash memory End? User’s Manual U15862EJ3V0UD...
Page 696 CHAPTER 25 FLASH MEMORY 25.6.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer, set the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 in the flash memory programming mode. To set the mode, set the V pin and clear the reset signal.
Page 697 V850ES/KG1, V850ES/KJ1 The flash memory control commands of the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are listed in the table below. All these commands are issued from the programmer and the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 perform processing corresponding to the respective commands.
Page 698 CHAPTER 25 FLASH MEMORY Table 25-8. Response Commands Command Name Function ACK (acknowledge) Acknowledges command/data. NAK (not acknowledge) Acknowledges illegal command/data. 25.6.5 Resources used The resources used in the flash memory programming mode are the areas other than addresses 03FFE800H to 03FFEFFFH (2 KB) of the internal RAM, and all the registers.
Page 699: Chapter 26 Electrical Specifications
CHAPTER 26 ELECTRICAL SPECIFICATIONS = 25° ° ° ° C) (1/2) Absolute Maximum Ratings (T Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage = EV = AV REF0 −0.3 to +10.5 Flash memory version, Note 1 ≤ V −0.3 to V + 0.3 Note 2...
Page 700 Storage temperature Mask ROM version −40 to +125 °C Flash memory version Note In the V850ES/KF1, the specifications of the total of all pins for I and I are as follows since BV system pins do not exist. Total of pins:...
Page 701 DC characteristics and AC characteristics represent the quality assurance range during normal operation. 3. The following pins are not provided in the V850ES/KF1. P10, P11, P36, P37, P60 to P615, P78 to P715, P80, P81, P92 to P95, P910 to P912, PCD0 to...
Page 702 CHAPTER 26 ELECTRICAL SPECIFICATIONS Operating Conditions = − − − − 40 to + + + + 85° ° ° ° C, V = 2.7 to 5.5 V, 2.7 V ≤ ≤ ≤ ≤ BV ≤ ≤ ≤ ≤ V , 2.7 V ≤...
Page 703 CHAPTER 26 ELECTRICAL SPECIFICATIONS = − − − − 40 to + + + + 85° ° ° ° C, V Main Clock Oscillator Characteristics (T = 2.7 to 5.5 V, V = 0 V) Resonator Recommended Circuit Parameter Conditions MIN.
Page 704 The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850ES/KF1, V850ES/KG1, and V850ES/KJ1 so that the internal operating conditions are within the specifications of the DC and AC characteristics.
Page 705 CHAPTER 26 ELECTRICAL SPECIFICATIONS = − − − − 40 to + + + + 85° ° ° ° C, V Subclock Oscillator Characteristics (T = 2.7 to 5.5 V, V = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP.
Page 706 PCS7, PCT0 to PCT7 Total of PDL0 to PDL15, PDH0 to PDH7 Caution The following pins are not provided in the V850ES/KF1. P10, P11, P36, P37, P60 to P615, P78 to P715, P80, P81, P92 to P95, P910 to P912, PCD0 to PCD3,...
Page 707 5. When pull-up is not specified by a mask option. EV when pull-up is specified. Caution The following pins are not provided in the V850ES/KF1. P10, P11, P36, P37, P60 to P615, P78 to P715, P80, P81, P92 to P95, P910 to P912, PCD0 to PCD3,...
Page 708 = 30 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: I = 30 mA. Caution The following pins are not provided in the V850ES/KF1. P10, P11, P36, P37, P60 to P615, P78 to P715, P80, P81, P92 to P95, P910 to P912, PCD0 to PCD3,...
Page 709 CHAPTER 26 ELECTRICAL SPECIFICATIONS DC Characteristics = − − − − 40 to + + + + 85° ° ° ° C, V = 2.7 to 5.5 V, 2.7 V ≤ ≤ ≤ ≤ BV ≤ ≤ ≤ ≤ V , 2.7 V ≤...
Page 710 CHAPTER 26 ELECTRICAL SPECIFICATIONS DC Characteristics = − − − − 40 to + + + + 85° ° ° ° C, V = 2.7 to 5.5 V, 2.7 V ≤ ≤ ≤ ≤ BV ≤ ≤ ≤ ≤ V , 2.7 V ≤...
Page 711 CHAPTER 26 ELECTRICAL SPECIFICATIONS Data Retention Characteristics = − − − − 40 to + + + + 85° ° ° ° C) STOP Mode (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention voltage STOP mode DDDR µ s STOP release signal input time DREL Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated...
Page 712 CHAPTER 26 ELECTRICAL SPECIFICATIONS AC Characteristics AC Test Input Measurement Points (V , AV , EV Measurement points AC Test Output Measurement Points Measurement points Load Conditions (Device under measurement) = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
Page 713 CHAPTER 26 ELECTRICAL SPECIFICATIONS CLKOUT Output Timing = − − − − 40 to + + + + 85° ° ° ° C, V = 2.7 to 5.5 V, 2.7 V ≤ ≤ ≤ ≤ BV ≤ ≤ ≤ ≤ V , 2.7 V ≤...
Page 714 CHAPTER 26 ELECTRICAL SPECIFICATIONS Bus Timing (1) In multiplex bus mode (a) CLKOUT asynchronous: In multiplex bus mode = − − − − 40 to + + + + 85° ° ° ° C, V = 4.0 to 5.5 V, 4.0 V ≤ ≤ ≤ ≤ BV ≤...
Page 715 CHAPTER 26 ELECTRICAL SPECIFICATIONS = − − − − 40 to + + + + 85° ° ° ° C, V = 2.7 to 5.5 V, 2.7 V ≤ ≤ ≤ ≤ BV ≤ ≤ ≤ ≤ V , 2.7 V ≤ ≤ ≤ ≤ AV ≤...
Page 716 CHAPTER 26 ELECTRICAL SPECIFICATIONS (b) CLKOUT synchronous: In multiplex bus mode = − − − − 40 to + + + + 85° ° ° ° C, V = 4.0 to 5.5 V, 4.0 V ≤ ≤ ≤ ≤ BV ≤...
Page 717 CHAPTER 26 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait): In Multiplex Bus Mode CLKOUT (output) <39> A16 to A23 (output) <14> <43> <44> <40> Hi-Z AD0 to AD15 (I/O) Address Data <41> <41> <11> <12> <17> ASTB (output) <22> <42>...
Page 718 CHAPTER 26 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait): In Multiplex Bus Mode CLKOUT (output) <39> A16 to A23 (output) <45> AD0 to AD15 (I/O) Address Data <41> <41> <11> <12> ASTB (output) <22> <42> <19> <42> <23> <16> <24>...
Page 719 CHAPTER 26 ELECTRICAL SPECIFICATIONS Bus Hold: In Multiplex Bus Mode CLKOUT (output) <48> <48> <49> <34> HLDRQ (input) <51> <51> <37> <38> HLDAK (output) <36> <35> <50> Hi-Z A16 to A23 (output) Data Hi-Z AD0 to AD15 (I/O) Hi-Z ASTB (output) Hi-Z RD (output), WR0 (output), WR1 (output)
Page 720 (1 + n)T <65> HAWT2 Cautions 1. The separate bus mode is not supported in the V850ES/KF1. 2. Set the following in accordance with the usage conditions of the CPU operation clock frequency (n = 0 to 3). • 1/ <...
Page 721 (1 + n)T <65> HAWT2 Cautions 1. The separate bus mode is not supported in the V850ES/KF1. 2. Set the following in accordance with the usage conditions of the CPU operation clock frequency (n = 0 to 3). • 1/ <...
Page 722 <71> HKWT Caution The separate bus mode is not supported in the V850ES/KF1. Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. = − − − − 40 to + + + + 85° ° ° ° C, V = 2.7 to 5.5 V, 2.7 V ≤...
Page 723 (1 + n)T <86> HAWT2 Cautions 1. The separate bus mode is not supported in the V850ES/KF1. 2. Set the following in accordance with the usage conditions of the CPU operation clock frequency (n = 0 to 3). • 1/ <...
Page 724 (1 + n)T <86> HAWT2 Cautions 1. The separate bus mode is not supported in the V850ES/KF1. 2. Set the following in accordance with the usage conditions of the CPU operation clock frequency (n = 0 to 3). • 1/ <...
Page 725 <91> HKWT Caution The separate bus mode is not supported in the V850ES/KF1. Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
Page 726 CHAPTER 26 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Asynchronous, 1 Wait): In Separate Bus Mode CLKOUT (output) CS0 to CS3 (output) A0 to A23 (output) <53> <57> Hi-Z Hi-Z AD0 to AD15 (I/O) <56> <52> <55> <54> (output) <61> <59> <60> <58>...
Page 727 CHAPTER 26 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Synchronous, 1 Wait): In Separate Bus Mode CLKOUT (output) <66> <66> CS0 to CS3 (output) A0 to A23 (output) <67> <68> Hi-Z Hi-Z AD0 to AD15 (I/O) <69> <69> (output) <70> <71> <70> <71>...
Page 728 CHAPTER 26 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Asynchronous, 1 Wait): In Separate Bus Mode CLKOUT (output) CS0 to CS3 (output) A0 to A23 (output) <73> <78> Hi-Z Hi-Z AD0 to AD15 (I/O) <75> <77> <72> <76> <74> WR0, WR1 (output) <82>...
Page 729 CHAPTER 26 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Synchronous, 1 Wait): In Separate Bus Mode CLKOUT (output) <87> <87> CS0 to CS3 (output) A0 to A23 (output) <88> <88> Hi-Z Hi-Z AD0 to AD15 (I/O) <89> <89> WR0, WR1 (output) <90> <91>...
Page 730 CHAPTER 26 ELECTRICAL SPECIFICATIONS Basic Operation = − − − − 40 to + + + + 85° ° ° ° C, V = 2.7 to 5.5 V, 2.7 V ≤ ≤ ≤ ≤ BV ≤ ≤ ≤ ≤ V , 2.7 V ≤...
Page 731 However, f /4 when the TI0n valid edge is selected as the timer count clock. Remark V850ES/KF1: n = 00, 01, 10, 11 V850ES/KG1: n = 00, 01, 10, 11, 20, 21, 30, 31 V850ES/KJ1: n = 00, 01, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51 UART Timing = −...
Page 732 REGC = V = 2.7 to 5.5 V Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) (2) Slave mode = − − − − 40 to + + + + 85° ° ° ° C, V = 2.7 to 5.5 V, 2.7 V ≤...
Page 733 CHAPTER 26 ELECTRICAL SPECIFICATIONS <99> <100> <100> SCK0n (I/O) <101> <102> Hi-Z Hi-Z SI0n (input) Input data <103> SO0n (output) Output data Remark n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 734 = 4.0 to 5.5 V, REGC = V = 2.7 to 5.5 V Remark n = 0 (V850ES/KF1), n = 0, 1 (V850ES/KG1, V850ES/KJ1) (2) Slave mode = − − − − 40 to + + + + 85° ° ° ° C, V = 2.7 to 5.5 V, 2.7 V ≤...
Page 735 CHAPTER 26 ELECTRICAL SPECIFICATIONS <99> <100> <100> SCKAn (I/O) <101> <102> Hi-Z Hi-Z SIAn (input) Input data <103> SOAn (output) Output data Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 736 = 1000 Rmax. SU:DAT + 250 = 1250 ns: Normal mode I C bus specification). 5. Cb: Total capacitance of one bus line (unit: pF) Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 737 <107> SCLn (I/O) <110> <108> <112> <111> <109> <113> <105> <114> <105> SDAn (I/O) <104> <111> <112> Stop Start Restart Stop condition condition condition condition Remark n = 0 (V850ES/KF1, V850ES/KG1), n = 0, 1 (V850ES/KJ1) User’s Manual U15862EJ3V0UD www.DataSheet.in...
Page 738 CHAPTER 26 ELECTRICAL SPECIFICATIONS A/D Converter = − − − − 40 to + + + + 85° ° ° ° C, V = 2.7 to 5.5 V, 2.7 V ≤ ≤ ≤ ≤ BV ≤ ≤ ≤ ≤ V , 2.7 V ≤...
Page 739 CHAPTER 26 ELECTRICAL SPECIFICATIONS Flash Memory Programming Characteristics = +10 to + + + + 40° ° ° ° C, V = 2.7 to 5.5 V, 2.7 V ≤ ≤ ≤ ≤ BV ≤ ≤ ≤ ≤ V , 2.7 V ≤ ≤ ≤ ≤ AV ≤...
Page 740 CHAPTER 26 ELECTRICAL SPECIFICATIONS (2) Serial write operation characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit ↑ to V ↑ µ s Setup time from V DPRSR ↑ to RESET↑ µ s Setup time from V PSRRF µ s Count start time from RESET↑ to V RFOF Count complete time COUNT...
Page 741: Chapter 27 Package Drawings
CHAPTER 27 PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.13 mm of 17.20±0.20 its true position (T.P.) at maximum material condition. 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20...
Page 742 CHAPTER 27 PACKAGE DRAWINGS 80-PIN PLASTIC TQFP (FINE PITCH) (12x12) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 14.0±0.2 its true position (T.P.) at maximum material condition. 12.0±0.2 12.0±0.2 14.0±0.2 1.25 1.25 0.22±0.05 0.08 0.5 (T.P.)
Page 743 CHAPTER 27 PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 16.00±0.20 its true position (T.P.) at maximum material condition. 14.00±0.20 14.00±0.20 16.00±0.20 1.00 1.00 0.22 +0.05 −0.04 0.08...
Page 744 CHAPTER 27 PACKAGE DRAWINGS 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 22.0±0.2 its true position (T.P.) at maximum material condition. 20.0±0.2 20.0±0.2 22.0±0.2 1.25 1.25 0.22±0.05 0.08 0.5 (T.P.)
Page 745: Chapter 28 Recommended Soldering Conditions
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Table 28-1. Surface Mounting Type Soldering Conditions (1/3) (1) µ...
Page 746 CHAPTER 28 RECOMMENDED SOLDERING CONDITIONS Table 28-1. Surface Mounting Type Soldering Conditions (2/3) (2) µ µ µ µ PD703208GC-xxx-8BT: 80-pin plastic QFP (14 × × × × 14) µ µ µ µ PD703208YGC-xxx-8BT: 80-pin plastic QFP (14 × × × × 14) µ...
Page 747 CHAPTER 28 RECOMMENDED SOLDERING CONDITIONS Table 28-1. Surface Mounting Type Soldering Conditions (3/3) (3) µ µ µ µ PD703216GJ-xxx-UEN: 144-pin plastic LQFP (fine pitch) (20 × × × × 20) µ µ µ µ PD703216YGJ-xxx-UEN: 144-pin plastic LQFP (fine pitch) (20 × × × × 20) µ...
Page 748: Appendix A Register Index
APPENDIX A REGISTER INDEX (1/7) Symbol Name Unit Page ADCR A/D conversion result register ADIC Interrupt control register INTC A/D converter mode register Analog input channel specification register ADTC0 Automatic data transfer address count register 0 ADTC1 Automatic data transfer address count register 1 ADTI0 Automatic data transfer interval specification register 0 510, 527...
Page 749 APPENDIX A REGISTER INDEX (2/7) Symbol Name Unit Page CORCN Correction control register ROMC CR000 16-bit timer capture/compare register 000 Timer CR001 16-bit timer capture/compare register 001 Timer CR010 16-bit timer capture/compare register 010 Timer CR011 16-bit timer capture/compare register 011 Timer CR020 16-bit timer capture/compare register 020...
Page 750 APPENDIX A REGISTER INDEX (3/7) Symbol Name Unit Page DWC0 Data wait control register 0 EXIMC External bus interface mode control register IIC0 IIC shift register 0 IIC1 IIC shift register 1 IICC0 IIC control register 0 IICC1 IIC control register 1 IICCL0 IIC clock selection register 0 IICCL1...
Page 751 APPENDIX A REGISTER INDEX (4/7) Symbol Name Unit Page Port 4 function register Port Port 5 function register Port Port 6 function register Port Port 8 function register Port PF9H Port 9 function register H Port PFC3 Port 3 function control register Port PFC5 Port 5 function control register...
Page 752 APPENDIX A REGISTER INDEX (5/7) Symbol Name Unit Page PMDH Port DH mode register Port PMDL Port DL mode register Port PRCMD Command register PRM00 Prescaler mode register 00 Timer PRM01 Prescaler mode register 01 Timer PRM02 Prescaler mode register 02 Timer PRM03 Prescaler mode register 03...
Page 753 APPENDIX A REGISTER INDEX (6/7) Symbol Name Unit Page SIRBE2 Clocked serial interface read-only receive buffer register 2 SIRBE2L Clocked serial interface read-only receive buffer register 2L SOTB0 Clocked serial interface transmit buffer register 0 SOTB0L Clocked serial interface transmit buffer register 0L SOTB1 Clocked serial interface transmit buffer register 1 SOTB1L...
Page 754 APPENDIX A REGISTER INDEX (7/7) Symbol Name Unit Page TM0IC41 Interrupt control register INTC TM0IC50 Interrupt control register INTC TM0IC51 Interrupt control register INTC Timer 16-bit timer counter 5 Timer TM50 8-bit timer counter 50 Timer TM51 8-bit timer counter 51 TM5IC0 Interrupt control register INTC...
Page 755 µ PD703208(A), 703208Y(A), 703209(A), 703209Y(A), 703210(A), 703210Y(A), 703212(A), 703212Y(A), 703213(A), 703213Y(A), 703214(A), 703214Y(A), 703216(A), 703216Y(A), 703217(A), 703217Y(A), 70F3210(A), 70F3210Y(A), 70F3214(A), 70F3214Y(A), 70F3217(A), 70F3217Y(A) Addition of Caution in 1.2.4 Pin configuration (top view) (V850ES/KF1) CHAPTER 1 INTRODUCTION Addition of Caution in 1.3.4 Pin configuration (top view) (V850ES/KG1) Addition of Caution in 1.4.4 Pin configuration (top view) (V850ES/KJ1)
Page 756 Addition to Cautions in Table 25-1 Wiring Between µ PD70F3210 and 70F3210Y CHAPTER 25 FLASH (V850ES/KF1), and PG-FP3 MEMORY Addition of Figure 25-1 Wiring Example of V850ES/KF1 Flash Writing Adapter (FA- 80GC-8BT, FA-80GK-9EU) Addition of Cautions in Table 25-2 Wiring Between µ PD70F3214 and 70F3214Y (V850ES/KG1), and PG-FP3 User’s Manual U15862EJ3V0UD...
Page 757 APPENDIX B REVISION HISTORY (3/3) Edition Major Revision from Previous Edition Applied to: Addition of Figure 25-2 Wiring Example of V850ES/KG1 Flash Writing Adapter (FA- CHAPTER 25 FLASH 100GC-8EU) MEMORY Addition of Cautions in Table 25-3 Wiring Between µ PD70F3217 and 70F3217Y (V850ES/KJ1), and PG-FP3 Addition of Figure 25-3 Wiring Example of V850ES/KJ1 Flash Writing Adapter (FA- 144GJ-UEN)