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Chapter 1
CPU
Core
Number of instructions
Minimum instruction execution time
General registers
Instruction set
V850E (compatible with V850 plus additional powerful instructions for reducing code and increasing execution
speed)
Signed multiplication (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64 bits): 1 to 2 clocks
Saturated operation instructions (with overflow/underflow detection)
32-bit shift instructions: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
Signed load instructions
Internal flash memory
Size
Flash protection
Secure self programming
Internal mask ROM memory
Size
24
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A full range of software development tools
A development system is available that includes an optimized C compiler,
debugger, in-circuit emulator, simulator, system performance analyzer, and
other elements.
1.2 Features Summary
The following table provides a quick summary of the most outstanding
features.
Table 1-1
V850E/Dx3 features summary (1/4)
Preliminary User's Manual U17566EE1V2UM00
V850E1
81
• 19.841 ns (@ φ = 50.4 MHz) (µPD70F3424,
µPD70F3425, µPD70F3426, µPD70F3427)
• 39.683 ns (@ φ = 25.2 MHz) (µPD70(F)3420,
µPD70(F)3421, µPD70(F)3422, µPD70F3423)
32 registers (32 bits each)
• 2 MB (µPD70F3426)
• 1 MB (µPD70F3427, µPD70F3425)
• 512 KB (µPD70F3424, µPD70F3423)
• 384 KB (µPD70F3422)
• 256 KB (µPD70F3421)
• 128KB (µPD70F3420)
• N-Wire security function
• external programmer security function
• 384 KB (µPD703422)
• 256 KB (µPD703421)
• 128 KB (µPD703420)
Introduction
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