Table of Contents
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Index
ROM correction address regis-
ters
COR2ADn 337
CORADn 336
ROM correction control regis-
ters
COR2CN 335
CORCN 335
ROM Correction Function 331
DBTRAP operation and
ROMC (ROM controller) 252
RSUDIS write protection regis-
ter (RSUDIS) 881
RSUDISC 880
RSUDISCP 881
S
SAR 771
Saturated operation
instructions 110
SCC 154
SCFC0 145
SCFC1 146
SCFMC 147
SCPS 149
Segment signals (LCD Control-
ler/Driver) 817
SEGREG0k 815
SELFEN 234, 235
SELFENP 234, 235
Self-programming enable con-
trol register (SELFEN) 234,
235
Self-programming enable pro-
tection register
(SELFENP) 234, 235
SFR (special function
register) 891
SG0 control register
(SG0CTL) 845
SG0 frequency high register
(SG0FH) 847
SG0 frequency low register
(SG0FL) 846
SG0 volume register
(SG0PWM) 848
SG0CTL 845
SG0FH 847
SG0FL 846
SG0PWM 848
Slave address registers
(SVAn) 592
928
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Software exception 220
Sound Generator 841
SPCLK control register
Special clocks 132
Special function registers
program flow 333
SSCG control registers 144
SSCG frequency control regis-
SSCG frequency control regis-
SSCG frequency modulation
SSCG post scaler control regis-
Stack pointer 106
Stand-by
Stand-by control protection reg-
Stand-by control register
STBCTL 161
STBCTLP 162
Stepper Motor Controller/
STOP mode 173
Sub oscillator
Sub oscillator clock monitor
Sub oscillator clock monitor reg-
Sub-WATCH mode 172
Successive approximation reg-
SVAn 592
System register set 107
T
TCC 152
Text pointer 106
Preliminary User's Manual U17566EE1V2UM00
Application hints 853
Operation 849
Registers 844
(SCC) 154
(list) 891
ter 0 (SCFC0) 145
ter 1 (SCFC1) 146
control register
(SCFMC) 147
ter (SCPS) 149
Control 132
Mode of Voltage
Comparator 872
ister (STBCTLP) 162
(STBCTL) 161
Driver 795
Operation 803
Registers 797
Operation after power
save mode 184
control register
(CLMCS) 166
ister (CLMS) 165
ister (SAR) 771
TGnCCmIC 210
TGnOV0IC 210
TGnOV1IC 210
Time base status register
(TMGSTn) 446
Timer G 437
Basic Operation 450
Control registers 441
Edge Noise
Elimination 473
Match and Clear
Mode 462
Operation in Free-Run
Mode 451
Output Delay
Operation 449
Precautions 474
Timer G capture/compare regis-
ters with external PWW-out-
put function (GCCnm) 448
Timer Gn 16-bit counter regis-
ters (TMGn0, TMGn1) 446
Timer Gn capture/compare reg-
isters (GCCn0, GCCn5) 447
Timer Gn channel mode regis-
ter (TMGCMn/TMGCMnL/
TMGCMnH) 444
Timer Gn mode register (TMG-
Mn/TMGMnL/
TMGMnH) 442
Timer Gn output control register
(OCTLGn/OCTLGnL/
OCTLGnH) 445
Timer mode control registers
(MCNTCn0, MCNTCn1) 799
Timer Z 429
Registers 431
Timer Z timing 435
Steady operation 435
Timer start and stop 436
Timer/Event Counter P 343
Configuration 344
External event count
mode 367
External trigger pulse out-
put mode 376
Free-running timer
mode 403
Interval timer mode 358
One-shot pulse output
mode 387
Operation 358
Pulse width measurement
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