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Application Note
V850E/MA1, V850E/MA2, V850E/MA3, V850E/ME2
32-Bit Single-Chip Microcontrollers
PCI Host Bridge Macro
V850E/MA1:
µ
PD703103A
µ
PD703105A
µ
PD703106A
µ
PD703106A(A)
µ
PD703107A
µ
PD703107A(A)
µ
PD70F3107A
µ
PD70F3107A(A)
Document No. U17121EJ1V1AN00 (1st edition)
Date Published September 2004 N CP(K)
Printed in Japan
V850E/MA2:
µ
PD703108
2004
V850E/MA3:
µ
PD703131A
µ
PD703131AY
µ
PD703132A
µ
PD703132AY
µ
PD703133A
µ
PD703133AY
µ
PD703134A
µ
PD703134AY
µ
PD70F3134A
µ
PD70F3134AY
V850E/ME2:
µ
PD703111A
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Table of Contents
Related Manuals for NEC V850E/MA1
Summary of Contents for NEC V850E/MA1
- Page 1 Application Note V850E/MA1, V850E/MA2, V850E/MA3, V850E/ME2 32-Bit Single-Chip Microcontrollers PCI Host Bridge Macro V850E/MA1: V850E/MA2: V850E/MA3: V850E/ME2: µ µ µ µ PD703103A PD703108 PD703131A PD703111A µ µ PD703105A PD703131AY µ µ PD703106A PD703132A µ µ PD703106A(A) PD703132AY µ µ PD703107A PD703133A µ...
- Page 2 [MEMO] Application Note U17121EJ1V1AN...
- Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
- Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
- Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
- Page 6 It is assumed that the readers of this application note have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. For details of the hardware functions and electrical specifications of the V850E/MA1, V850E/MA2, V850E/MA3, and V850E/ME2 → Refer to the Hardware User’s Manual of each product.
- Page 7 U16031E V850E/ME2 Hardware Application Note U16794E V850E/ME2 USB Function Driver Application Note U17069E V850E/MA1, V850E/MA2, V850E/MA3, V850E/ME2 PCI Host Bridge Macro Application Note This manual Documents related to development tools (user’s manuals) Document Name Document No. IE-V850E-MC, IE-V850E-MC-A In-Circuit Emulator...
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Page 8: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW OF EACH PRODUCT..................10 1.1 Outline ............................10 1.2 Features............................11 1.3 Ordering Information........................12 1.4 Pin Configuration..........................14 1.5 Internal Block Diagram ........................25 CHAPTER 2 OVERVIEW OF PCI HOST BRIDGE MACRO..............29 2.1 Outline ............................29 2.2 Features............................30 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO ...........31 3.1 Internal Blocks of PCI Host Bridge Macro .................31 3.2 Relationship Between Internal Blocks and Signals ..............32 3.3 Pin Functions ..........................33... - Page 9 4.5.1 Internal connection diagram of external bus interface ............... 61 4.5.2 Internal connection diagram of PCI bus interface ................62 4.5.3 External connection diagram of external bus interface (example of connection with V850E/ME2)..63 4.5.4 External connection diagram of PCI bus interface ................64 4.6 Cautions on Designing FPGA .....................65 4.6.1 FPGA fitting design..........................
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Page 10: Chapter 1 Overview Of Each Product
CHAPTER 1 OVERVIEW OF EACH PRODUCT The V850E/MA1, V850E/MA2, V850E/MA3, and V850E/ME2 are products in NEC Electronics’ V850 Series of single-chip microcontrollers. This chapter gives a simple outline of each product. 1.1 Outline The V850E/MA1, V850E/MA2, V850E/MA3, and V850E/ME2 are 32-bit single-chip microcontrollers that integrate the V850E1 CPU, which is a 32-bit RISC-type CPU core for ASIC, newly developed as the CPU core central to system LSI in the current age of system-on-chip. -
Page 11: Features
CHAPTER 1 OVERVIEW OF EACH PRODUCT 1.2 Features Commercial Name V850E/MA1 V850E/MA2 V850E/MA3 V850E/ME2 Maximum operating 50 MHz 40 MHz 80 MHz 150 MHz frequency − − − − − Internal Mask ROM memory − − − − Flash memory... -
Page 12: Ordering Information
CHAPTER 1 OVERVIEW OF EACH PRODUCT 1.3 Ordering Information (1) V850E/MA1 Part Number Package Internal ROM µ 144-pin plastic LQFP (fine pitch) (20 × 20) PD703103AGJ-UEN ROMless µ 144-pin plastic LQFP (fine pitch) (20 × 20) PD703105AGJ-xxx-UEN Mask ROM (128 KB) µ... - Page 13 CHAPTER 1 OVERVIEW OF EACH PRODUCT (3) V850E/MA3 Part Number Package Internal ROM µ 144-pin plastic LQFP (fine pitch) (20 × 20) PD703131AGJ-xxx-UEN Mask ROM (256 KB) µ 161-pin plastic FBGA (13 × 13) PD703131AF1-xxx-EN4 Mask ROM (256 KB) µ 144-pin plastic LQFP (fine pitch) (20 ×...
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Page 14: Pin Configuration
CHAPTER 1 OVERVIEW OF EACH PRODUCT 1.4 Pin Configuration (1) V850E/MA1 • 144-pin plastic LQFP (fine pitch) (20 × 20) µ µ µ PD703103AGJ-UEN PD703106AGJ(A)-xxx-UEN PD70F3107AGJ-UEN µ µ µ PD703105AGJ-xxx-UEN PD703107AGJ-xxx-UEN PD70F3107AGJ(A)-UEN µ µ PD703106AGJ-xxx-UEN PD703107AGJ(A)-xxx-UEN Top View D14/PDL14 PCD3/UBE/SDRAS... - Page 15 CHAPTER 1 OVERVIEW OF EACH PRODUCT • 161-pin plastic FBGA (13 × 13) µ PD703106AF1-xxx-EN4 µ PD703107AF1-xxx-EN4 µ PD70F3107AF1-EN4 Top View Bottom View A B C D E F G H J K L M N P P N M L K J H G F E D C B A Index mark Index mark (1/2)
- Page 16 CHAPTER 1 OVERVIEW OF EACH PRODUCT (2/2) Pin No. Name Pin No. Name Pin No. Name D3/PDL3 ANI6/P76 D4/PDL4 DMAAK1/PBD1 ANI5/P75 − DMAAK3/PBD3 − RD/PCT4 ANI1/P71 ANI0/P70 PWM1/P10 LCAS/LWR/LDQM/PCT0 TC3/INTP113/P27 UCAS/UWR/UDQM/PCT1 TC0/INTP110/P24 − MODE2 (MODE2/V NMI/P20 DMARQ3/INTP103/P07 DMAAK2/PBD2 ADTRG/INTP123/P37 D0/PDL0 TI010/INTP010/P11 TXD2/INTP133/P33 D6/PDL6...
- Page 17 CHAPTER 1 OVERVIEW OF EACH PRODUCT (2) V850E/MA2 • 100-pin plastic LQFP (fine pitch) (14 × 14) µ PD703108GC-8EU Top View A1/PAL1 PAH7/A23 A0/PAL0 PAH8/A24 D15/PDL15 PCD0/SDCKE D14/PDL14 PCD1/SDCLK D13/PDL13 PCD2/LBE/SDCAS D12/PDL12 PCD3/UBE/SDRAS D11/PDL11 PCS0/CS0 D10/PDL10 PCS3/CS3 D9/PDL9 PCS4/CS4 D8/PDL8 PCS7/CS7 PCT0/LWR/LDQM PCT1/UWR/UDQM...
- Page 18 CHAPTER 1 OVERVIEW OF EACH PRODUCT (3) V850E/MA3 • 144-pin plastic LQFP (fine pitch) (20 × 20) µ µ µ PD703131AGJ-xxx-UEN PD703133AGJ-xxx-UEN PD70F3134AGJ-UEN µ µ µ PD703131AYGJ-xxx-UEN PD703133AYGJ-xxx-UEN PD70F3134AYGJ-UEN µ µ PD703132AGJ-xxx-UEN PD703134AGJ-xxx-UEN µ µ PD703132AYGJ-xxx-UEN PD703134AYGJ-xxx-UEN Top View AD14/PDL14 PCD3/SDRAS AD13/PDL13 PCS0/CS0...
- Page 19 CHAPTER 1 OVERVIEW OF EACH PRODUCT • 161-pin plastic FBGA (13 × 13) µ µ µ PD703131AF1-EN4 PD703133AF1-xxx-EN4 PD70F3134AF1-EN4 µ µ µ PD703131AYF1-xxx-EN4 PD703133AYF1-xxx-EN4 PD70F3134AYF1-EN4 µ µ PD703132AF1-xxx-EN4 PD703134AF1-xxx-EN4 µ µ PD703132AYF1-xxx-EN4 PD703134AYF1-xxx-EN4 Top View Bottom View A B C D E F G H J K L M N P P N M L K J H G F E D C B A Index mark Index mark...
- Page 20 CHAPTER 1 OVERVIEW OF EACH PRODUCT (2/2) Pin No. Name Pin No. Name Pin No. Name CS7/PCS7 NMI/P20 TOQT1/INTP011/INTPQ1/TOQ1/P11 ANI6/P76 AD2/PDL2 TC3/TDO/P27 ANI5/P75 − AD3/PDL3 TC0/INTP124/P24 AD4/PDL4 TC2/TDI/INTP126/P26 ANI1/P71 DMARQ3/TCK/INTP107/P07 RD/PCT4 ANI0/P70 DMAAK3/PBD3 DMAAK0/PBD0 Note LBE/LWR/LDQM/PCT0 TXD3/SDA /INTP133/P33 UBE/UWR/UDQM/PCT1 TXD2/SO2/INTP130/P30 TOP01/INTP001/INTPP01/P01 TC1/TIUD10/TO10/INTP125/P25 ASCK0/SCK0/P42...
- Page 21 CHAPTER 1 OVERVIEW OF EACH PRODUCT (4) V850E/ME2 • 176-pin plastic LQFP (fine pitch) (24 × 24) µ PD703111AGM-10-UEU µ PD703111AGM-13-UEU µ PD703111AGM-15-UEU Top View JIT1 TRCDATA3 JIT0 PDH15/D31/INTPD15/PWM1 PDH14/D30/INTPD14/PWM0 REFP ANI0 ANI1 PDH13/D29/INTPD13/TIUD11 ANI2 PDH12/D28/INTPD12/TO11 ANI3 PDH11/D27/INTPD11/INTP111/TCLR11 ANI4 PDH10/D26/INTPD10/INTP110/TCUD11 ANI5 PDH9/D25/INTPD9/TIUD10 ANI6...
- Page 22 CHAPTER 1 OVERVIEW OF EACH PRODUCT • 240-pin plastic FBGA (16 × 16) µ PD703111AF1-10-GA3 µ PD703111AF1-13-GA3 µ PD703111AF1-15-GA3 Bottom View Top View V U T R P N M L K J H G F E D C B A A B C D E F G H J K L M N P R T U V Index mark...
- Page 23 CHAPTER 1 OVERVIEW OF EACH PRODUCT (1/2) Pin No. Name Pin No. Name Pin No. Name − PAH2/A18 PCT0/LLWR/LLBE/LLDQM PAH4/A20 PCM1 − PAH6/A22 PCM3/HLDRQ − PCT4/RD PCM4/REFRQ − PCS0/CS0 PCM5/ADTRG/SELFREF − − − − PCD0/SDCKE − PCT1/LUWR/LUBE/LUDQM − RESET − PAL0/INTPL0/A0 −...
- Page 24 CHAPTER 1 OVERVIEW OF EACH PRODUCT (2/2) Pin No. Name Pin No. Name Pin No. Name − PDH5/D21/INTPD5/TOC5 PDH6/D22/INTPD6/INTP100/ TRCCLK TCUD10 − P11/INTP11/SCK0 DRST ANI6 P25/INTP25/SO1 P22/INTP22/TXD1 REFM ANI7 PLLV − PDH7/D23/INTPD7/INTP101/ SSEL0 TCLR10 − PDH8/D24/INTPD8/TO10 OSCV − PDH9/D25/INTPD9/TIUD10 REFP −...
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Page 25: Internal Block Diagram
CHAPTER 1 OVERVIEW OF EACH PRODUCT 1.5 Internal Block Diagram (1) V850E/MA1 HLDRQ MEMC HLDAK INTP100 to INTP103, INTC CS0, CS7 INTP110 to INTP113, CS1/RAS1, CS3/RAS3 INTP120 to INTP123, Instruction CS4/RAS4, CS6/RAS6 DRAMC INTP130 to INTP133 CS2/IORD queue CS5/IOWR INTP000, INTP001,... - Page 26 CHAPTER 1 OVERVIEW OF EACH PRODUCT (2) V850E/MA2 MEMC HLDRQ INTP100, INTP101, INTC HLDAK INTP110 CS0, CS3, CS4, CS7 Instruction SDRAMC REFRQ queue LBE/SDCAS INTP000, INTP001, UBE/SDRAS INTP010, INTP011 Multiplier (32 × 32 → 64) SDCLK 32-bit SDCKE barrel shifter TO00 TI000, TI010 UWR/UDQM...
- Page 27 CHAPTER 1 OVERVIEW OF EACH PRODUCT (3) V850E/MA3 WAIT MEMC INTP000, INTP001, INTP004, INTP005 HLDRQ INTC HLDAK INTP010 to INTP013, INTP114, INTP115 BUSCLK INTP021, INTP022, INTP124 to INTP126 A0 to A25 INTP130 to INTP134, INTP137, INTP050, Instruction AD0 to AD15 INTP051, INTP106, INTP107 SRAM CS0 to CS7...
- Page 28 CHAPTER 1 OVERVIEW OF EACH PRODUCT (4) V850E/ME2 DRST, DCK, DMS, DDI, MEMC WAIT DDO, TRCCLK, HLDRQ TRCDATA0 to TRCDATA3, HLDAK TRCEND A0 to A25 SRAM D0 to D31 INTP10, INTP11 INTC INTP21 to INTP25 Instruction CS0, CS1, CS3, INTP50 to INTP52 queue CS4, CS6, CS7 Multiplier...
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Page 29: Chapter 2 Overview Of Pci Host Bridge Macro
PCI bus interface. This chapter gives an outline of the PCI host bridge macro. 2.1 Outline The PCI host bridge macro is a bridge control macro that connects V850E/MA1, V850E/MA2, V850E/MA3, V850E/ME2 external bus interfaces (memory controller (MEMC)) to the PCI bus interface. -
Page 30: Features
CHAPTER 2 OVERVIEW OF PCI HOST BRIDGE MACRO 2.2 Features The features of the PCI host bridge macro are as follows. • PCI bus master cycle control PCI configuration register read/write single cycle PCI I/O register read/write single cycle PCI memory read/write single cycle •... -
Page 31: Chapter 3 Specifications Of Pci Host Bridge Macro
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO This chapter describes the block diagram, signals, register specifications, and operation specifications of the PCI host bridge macro. 3.1 Internal Blocks of PCI Host Bridge Macro The PCI host bridge macro consists of the four blocks shown in Figure 3-1 General Block Diagram of PCI Host Bridge Macro. -
Page 32: Relationship Between Internal Blocks And Signals
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.2 Relationship Between Internal Blocks and Signals The I/O signals for each block of the PCI host bridge macro are as follows. Figure 3-2. Blocks and Pin Signals of PCI Host Bridge Macro External bus interface PCI bus interface I_SRST_B... -
Page 33: Pin Functions
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.3 Pin Functions The pin functions of each interface are described below. 3.3.1 External bus slave interface pins Pin Name Function Active I_SRST_B Input System reset input I_CPU_CS0_B Input PCI host bridge register chip select input I_CPU_CS1_B Input PCI I/O area chip select input... -
Page 34: Pci Bus Interface Pins
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.3.3 PCI bus interface pins Pin Name Function Active − I_PCLK Input PCI clock input O_PCIRST_B Output PCI reset output − I_AD0 to I_AD31 Input PCI address/data input − O_AD0 to O_AD31 Output PCI address/data output EN_AD... -
Page 35: Registers
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.4 Registers The registers of the PCI host bridge macro are listed below. The bit width of all registers is 32 bits. The offset address of each register is the offset value from the base address in the area in which the I_CPU_CS0_B pin becomes active. -
Page 36: Pci_Config_Add Register
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.4.2 PCI_CONFIG_ADD register After reset: 00000000H Offset address: 04H CADD Bit Name Function CADD Sets PCI configuration register address of access target. (1) How to set PCI_CONFIG_ADD register (a) Type 0 (PCI device) 11 10 IDSEL specification Function... -
Page 37: Pci_Control Register
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO (2) How to access PCI configuration register • Write access Set the access target register address to the PCI_CONFIG_ADD register ↓ Write the access target register setting value to the PCI_CONFIG_DATA register •... -
Page 38: Pci_Io_Base Register
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.4.4 PCI_IO_BASE register When I/O accessing the PCI bus I/O space via the PCI I/O area (area in which the I_CPU_CS1_B pin becomes active: 64 KB), any area of the 4 GB PCI bus I/O space can be accessed by setting this register. After reset: 00000000H Offset address: 10H 16 15... -
Page 39: Pci_Int_Ctl Register
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.4.6 PCI_INT_CTL register The PCI_INT_CTL register shows the interrupt sources of the PCI bus error interrupt (O_PCIHOST_INT) and controls masking and clearing of these interrupts. This function is used only for debugging and is not used in normal operation. After reset: 000x0F00H Offset address: 18H 20 19 18 17 16 15... -
Page 40: Pci_Err_Add Register
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.4.7 PCI_ERR_ADD register The PCI_ERR_ADD register retains the PCI bus address when the following errors occur. • System error (SERR# reception) • Parity error (PERR# reception) • Master abort • Target abort When the PCI_ERR_ADD register is read, all the bits are cleared. -
Page 41: System_Mem_Base Register
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.4.8 SYSTEM_MEM_BASE register When the main memory is accessed from the PCI device by setting the SYSTEM_MEM_BASE register and SYSTEM_MEM_RANGE register, the register responds to an access of a matching address. After reset: 00000000H Offset address: 40H 16 15 S_BASE... -
Page 42: Sdram_Ctl Register
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.4.10 SDRAM_CTL register After reset: 00070230H Offset address: 48H 24 23 16 15 13 12 11 10 9 CYCLE_LATENCY Bit Name Function CYCLE_LATENCY Sets the latency for successive main memory (SDRAM) accesses from the PCI device. A latency of up to 7,650 ns can be set. - Page 43 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO The correspondence between the output address signals when the main memory (SDRAM) is accessed and the PCI bus address signals is shown below. Table 3-1. Row Address Output COLUMN_SIZE Correspondence Between PCI Bus Address Signal and Main Memory (SDRAM) Address Pins Field Setting Value (O_SD_ADR1 to O_SD_ADR25) 25 to 18...
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Page 44: Address Map
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.5 Address Map The address maps of the CPU memory space and PCI bus I/O or memory space are shown below. Figure 3-3. CPU Memory Space/PCI Bus I/O Space Address Map CPU memory space PCI bus I/O space FFFF FFFFH FFFFH... -
Page 45: Initializing Pci Host Bridge Macro
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.6 Initializing PCI Host Bridge Macro The PCI host bridge macro must be initialized according to the following procedure to acknowledge memory access and I/O access to the PCI bus and main memory (SDRAM) access from the PCI device. Figure 3-5. -
Page 46: Bus Width Of External Bus Interface
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.7 Bus Width of External Bus Interface The operation mode of the data bus with respect to the external bus interface can be changed via the I_MODE16 pin status. Cautions 1. Do not change the status of the I_MODE16 pin during operation. 2. -
Page 47: Timing
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.8 Timing The timing for each interface of the PCI host bridge macro is shown below. 3.8.1 External bus interface timing CPU write/CPU read access is performed from the CPU using the bus interface (Figures 3-6 and 3-7). When accessing SDRAM from the PCI host bridge macro, bus hold is performed and the main memory is write/read accessed (Figures 3-8 to 3-10). - Page 48 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO Figure 3-8. Hold Request/Hold Acknowledge I_SDCLK O_HOLDREQ_B I_HOLDACK_B EN_SD_CTL SDRAM control signal output Figure 3-9. Main Memory (SDRAM) Write Access (8-Burst) I_SDCLK O_HOLDREQ_B I_HOLDACK_B O_SD_CS_B O_SD_RAS_B O_SD_CAS_B O_SD_WR_B O_SD_ADR1 to CA2 CA3 CA4 CA5 CA6 CA7 O_SD_ADR25 O_SD_DATA0 to WD0 WD1...
- Page 49 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO Figure 3-10. Main Memory (SDRAM) Read Access (8-Burst) I_SDCLK O_HOLDREQ_B I_HOLDACK_B O_SD_CS_B O_SD_RAS_B O_SD_CAS_B O_SD_WR_B O_SD_ADR1 to CA2 CA3 CA4 CA5 CA6 CA7 O_SD_ADR25 I_SD_DATA0 to RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 I_SD_DATA31 O_SD_DQM_B0 to 0000...
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Page 50: Pci Bus Interface Timing
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.8.2 PCI bus interface timing The PCI host bridge macro supports the following PCI bus interface timing. (1) PCI bus master cycle timing The timing of access from the CPU to the PCI device is shown below. (a) Configuration read/write cycle, I/O read/write cycle, and memory read/write cycle Read cycle Timing type: Configuration register read, internal I/O register read, memory read... - Page 51 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO (b) Target abort cycle Timing type: Target abort Figure 3-13. Target Abort Cycle PCICLK FRAME# IRDY# DEVSEL# TRDY# STOP# (c) Master abort cycle Timing type: Master abort cycle Figure 3-14. Master Abort Cycle PCICLK FRAME# IRDY#...
- Page 52 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO (d) Data parity error Timing type: Single read & write cycle data parity error Figure 3-15. Data Parity Error PCICLK FRAME# IRDY# DEVSEL# TRDY# STOP# PERR# (2) PCI bus slave cycle timing The timing of access from the PCI device to SDRAM is shown below.
- Page 53 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO (b) Memory single write cycle Timing type: Memory single write cycle Figure 3-17. Single Write Cycle PCICLK REQ# GNT# FRAME# IRDY# DEVSEL# TRDY# STOP# (c) Burst read cycle Timing type: Memory burst read cycle − Not disconnect Figure 3-18.
- Page 54 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO (d) Burst write cycle Timing type: Memory burst write cycle − Not disconnect Figure 3-19. Burst Write Cycle PCICLK REQ# GNT# FRAME# IRDY# DEVSEL# TRDY# STOP# (e) Abort cycle Timing type: Target abort cycle & master abort cycle Figure 3-20.
- Page 55 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO (f) Data parity error Read data parity error 1 Timing type: Single read cycle data parity error Figure 3-21. Read Data Parity Error PCICLK FRAME# IRDY# DEVSEL# TRDY# STOP# PERR# (ii) Read data parity error 2 Timing type: Burst read cycle data parity error Figure 3-22.
- Page 56 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO (iii) Write data parity error 1 Timing type: Single write cycle data parity error Figure 3-23. Write Data Parity Error 1 PCICLK FRAME# IRDY# DEVSEL# TRDY# STOP# PERR# SERR# (iv) Write data parity error 2 Timing type: Burst write cycle data parity error Figure 3-24.
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Page 57: Chapter 4 Configuration Examples Of Fpga Integration
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION This chapter describes configuration examples in which the PCI host bridge macro is integrated in an FPGA (Altera’s EP20K200EQC240-1X). 4.1 Conditions for Configuration Examples of FPGA Integration The conditions in the configuration examples are as follows. (1) CPU: V850E/ME2 (2) Bus width of external bus interface: 32 bits... -
Page 58: Reference Diagram For Fpga Top Connection
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.3 Reference Diagram for FPGA Top Connection The reference diagram for connecting the PCI host bridge macro with the FPGA top layer is shown below. FPGA top PCI host bridge macro VBRESETZ I_SRST_B I_PCLK PCLK CSZ6... -
Page 59: Fpga Top Pin Functions
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.4 FPGA Top Pin Functions The pin information when integrating the PCI host bridge macro with an FPGA is shown below. 4.4.1 CPU bus slave interface pins Pin Name Function VBRESETZ Input System reset input CSZ6 Input PCI host bridge chip select input... -
Page 60: Pci Bus Interface Pins
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.4.3 PCI bus interface pins Pin Name Function PCLK Input PCI clock input PCIRST Output PCI reset output AD0 to AD31 PCI address/data I/O CBE0 to CBE3 PCI command/byte enable I/O FRAME PCI frame I/O IRDY PCI initiator ready I/O DEVSEL... -
Page 61: Fpga Top Pin Configuration
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.5 FPGA Top Pin Configuration The connection diagram of the PCI host bridge macro pins in an FPGA is shown below. 4.5.1 Internal connection diagram of external bus interface FPGA top VBRESETZ RESET PCI host I_SRST_B bridge macro... -
Page 62: Internal Connection Diagram Of Pci Bus Interface
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.5.2 Internal connection diagram of PCI bus interface FPGA top PCLK PCI host I_PCLK bridge macro PCIRST RST# O_PCIRST_B I_AD0 to I_AD31 AD0 to AD31 AD0 to AD31 O_AD0 to O_AD31 EN_AD I_CBE0 to I_CBE3 CBE0 to CBE3 C/BE0# to C/BE3# O_CBE0 to O_CBE3... -
Page 63: External Connection Diagram Of External Bus Interface (Example Of Connection With V850E/Me2)
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.5.3 External connection diagram of external bus interface (example of connection with V850E/ME2) System reset FPGA SDRAM1 (PCI host bridge) SDRAM2 VBRESETZ RA2 to RA14 A0 to A12 RA24, RA25 BA0, BA1 RD0 to RD31 DQ0 to DQ31 BENZ0 to BENZ3 DQM0, DQM1... -
Page 64: External Connection Diagram Of Pci Bus Interface
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.5.4 External connection diagram of PCI bus interface PCI bus clock PCI host bridge PCI device 1 PCLK AD00 to AD31 AD00 to AD31 Note IDSEL CBE0 to CBE3 C/BE0# to C/BE3# PCIRST RST# FRAME FRAME#... -
Page 65: Cautions On Designing Fpga
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.6 Cautions on Designing FPGA Cautions when fitting an FPGA using Altera’s “Quartusll Design Software” are shown below. 4.6.1 FPGA fitting design (1) Set the “I/O Standard” buffer type to “3.3-V PCI” for the following PCI bus interface pins. Pin Name/Usage I/O Standard INTA... -
Page 66: Sdram Interface Timing
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION (2) CLK to signal valid delay signals MIN. MAX. All PCI pins 2 ns 11 ns The following specification values apply to the PCI bus timing (PCI CLK = 33 MHz). Figure 4-1. Output Timing Output delay Figure 4-2. -
Page 67: Chapter 5 Application Examples
CHAPTER 5 APPLICATION EXAMPLES This chapter introduces the configuration of an evaluation board that mounts the V850E/ME2, as well as program examples. This is an example of an application used to operate a HDD with an IDE controller mounted on the PCI connecter. 5.1 Block Diagram of Evaluation Board A block diagram of the evaluation board is shown below. -
Page 68: Specifications Of Evaluation Board
CHAPTER 5 APPLICATION EXAMPLES 5.2 Specifications of Evaluation Board The specifications of the evaluation board are as follows. Table 5-1. Specifications of Evaluation Board Item Description V850E/ME2 CPU operating frequency 30 MHz MEMC bus operating frequency 30 MHz Evaluation board memory Flash memory CSZ0 area (32-bit width): 8 MB SRAM... -
Page 69: Example Of Evaluation Board Connection Circuit
CHAPTER 5 APPLICATION EXAMPLES 5.3 Example of Evaluation Board Connection Circuit A circuit example of connection of the V850E/ME2 with SDRAM, FPGA, and a PCI device (slot) is shown below. Figure 5-2. Example of Evaluation Board Connection Circuit System reset PCI bus clock V850E/ME2 FPGA... -
Page 70: Evaluation Board Memory Space
CHAPTER 5 APPLICATION EXAMPLES 5.4 Evaluation Board Memory Space The evaluation board memory space is shown below. Figure 5-3. Evaluation Board Memory Space FFF FFFFH On-chip peripheral I/O area (4 KB) FFF F000H FFF EFFFH On-chip data RAM area (16 KB) FFF B000H FFF AFFFH Access-prohibited area... - Page 71 CHAPTER 5 APPLICATION EXAMPLES The PCI memory I/O space is assigned to the CSZ6 area. The base address of the PCI memory space is set to CC0 0000H. The base address of the PCI I/O space is set to C80 0000H. Figure 5-4.
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Page 72: Sample Program Examples
CHAPTER 5 APPLICATION EXAMPLES 5.5 Sample Program Examples This sample program is assumed to be used in an environment with the PCI-IDE board connected to the V850E/ME2 evaluation board as the PCI device. The PCI-IDE board is connected to the IDE HDD, and the sample program accesses the IDE HDD. 5.5.1 Development tools (1) MULTI 1.8.9... -
Page 73: V850E/Me2 Pci Host Bridge Macro Initialization Sample Program List
CHAPTER 5 APPLICATION EXAMPLES 5.5.3 V850E/ME2 PCI host bridge macro initialization sample program list ///////////////////////////////////////////////////////////////// V850E/ME2 - PCI Host Bridge Macro initialization sample Overview: Initializes PCI Host Bridge Macro by setting PCI Bridge IO area register group. Specific initialization is described in function PCI_HBM_Init(). - Page 74 CHAPTER 5 APPLICATION EXAMPLES ///////////////////////////////////////////////////////////////////////// // Function name: PCI_HBM_Init // Function: Initializes PCI Host Bridge Macro. // Argument: None // Return value: None // Remark: Base addresses of this initialization sample are as follows.// - Base address of PCI I/O space: 0C80_0000H - Base address of PCI memory space: 0CC0_0000H - Base address on PCI bus memory space in which...
- Page 75 CHAPTER 5 APPLICATION EXAMPLES V850EME2_REGW(PHBMR_SYSTEM_MEM_RANGE) = RANGE_SDRAM; // SYSTEM_MEM_RANGE register Set range of PCI bus memory space in which main memory (SDRAM) is mapped to 3FFFFFFH (64 MB). V850EME2_REGW(PHBMR_SDRAM_CTL) = 0x00071211; // SDRAM_CTL register bit 23-16: CYCLE_LATENCY = 07H (Set latency for successive main memory (SDRAM) access from PCI device to 210 ns) BUS_SIZE = 1B (Set bit width of data bus to 32 bits)
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Page 76: Pci Configuration Space Access Sample Program List
CHAPTER 5 APPLICATION EXAMPLES 5.5.4 PCI configuration space access sample program list ///////////////////////////////////////////////////////////////////////// PCI configuration space access sample Overview: Configuration space is accessed using procedure shown below. 1) Write 32-bit value indicating PCI device, function number, and register number to be accessed to PCI_CONFIG_ADD register of PCI Host Bridge Macro. - Page 77 CHAPTER 5 APPLICATION EXAMPLES ///////////////////////////////////////////////////////////////// // Function name: PCI_ConfigWrite // Function: Writes 32-bit value to PCI configuration space. // Argument: ConfigAdd: Register address of configuration space// ConfigData: Register data of configuration space // Return value: None ///////////////////////////////////////////////////////////////// void PCI_ConfigWrite(UWORD ConfigAdd, UWORD ConfigData) V850EME2_REGW(PHBMR_PCI_CONFIG_ADD) = ConfigAdd;...
- Page 78 CHAPTER 5 APPLICATION EXAMPLES /////////////////////////////////////// // ATA Control Register Base Address // /////////////////////////////////////// ConfigAddress = 0x40000014; // bit 31-11 : IDSEL specification = 010000000000000000000b Select PCI device connected to AD30 // bit 10-08 : Function number = 00b // bit 07-02 : Register number = 5 (000101b), ->...
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Page 79: Ide Hdd Access Sample Program List
CHAPTER 5 APPLICATION EXAMPLES 5.5.5 IDE HDD access sample program list /////////////////////////////////////////////////////////////////////////////// IDE HDD access sample Overview: Issues ATA commands to HDD, which is ATA device, via PCI-IDE // ASIC board connected to PCI slot of evaluation board. ATA commands to be issued are as follows. IDLE IMMEDIATE, IDENTIFY DEVICE, SET FEATURE, READ SECTOR(S), WRITE SECTOR(S), READ DMA, WRITE DMA ATA command is executed by executing device selection... - Page 80 CHAPTER 5 APPLICATION EXAMPLES #define IDEREG_ALTERNATE_STATUS ((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x0E)) #define IDEREG_DEVICE_CONTROL ((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x0E)) ///////////////////////// // Bus Master I/O Area // ///////////////////////// #define IDEREG_BUSMASTER_START_STOP ((VUWORD*)(BASE_ADDRESS_PCI_IO + 0x10)) #define IDEREG_DSCTBL_START_ADDRESS ((VUWORD*)(BASE_ADDRESS_PCI_IO + 0x14)) #define IDEREG_INTERRUPT_CONTROL ((VUWORD*)(BASE_ADDRESS_PCI_IO + 0x18)) /////////////////////////// // Error code definition // /////////////////////////// #define STATUS_SUCCESS #define STATUS_TIMEOUT_BSY0_DRQ0...
- Page 81 CHAPTER 5 APPLICATION EXAMPLES UBYTE cylinder_low; // Cylinder Low register UBYTE cylinder_high; // Cylinder High register UBYTE device_head; // Device/Head register UBYTE command; // Command register } ATA_COMMAND; //////////////////////////////////////////// // Descriptor table for UltraDMA transfer // //////////////////////////////////////////// typedef struct{ UWORD transfer_address; // Transfer address UWORD transfer_byte;...
- Page 82 CHAPTER 5 APPLICATION EXAMPLES when Parity Error is detected. // bit 2 : Bus Master = 1b : Enable PCI Bus Master transfer // bit 0 : IO Space = 1b : Enable IO access to PCI-IDE ASIC board PCI_ConfigWrite(ConfigAddress, ConfigData); //////////////////////////// // Setting DES to disable // ////////////////////////////...
- Page 83 CHAPTER 5 APPLICATION EXAMPLES ConfigData = 0x00000001; // bit 0 : IDE I/F RESET Port = 1b : Output IDE RESETX signal output to IDE I/F. PCI_ConfigWrite(ConfigAddress, ConfigData); return; //////////////////////////////////// // Transfer mode setting function // //////////////////////////////////// ///////////////////////////////////////////////////////////////////////// // Function name: Set_Transfer_Mode // Function: Setting of transfer mode // Argument: dev_num : Device selection (0:Master/1:Slave) mode : Transfer mode...
- Page 84 CHAPTER 5 APPLICATION EXAMPLES // bit 07-02 : Register number = 18 (010010b) -> PIO Timing (In the case of PCI-IDE ASIC board used in this application) // bit 01-00 : 00b (fixed) PCI_ConfigWrite( ConfigAddress, pio_timing ); return; ///////////////////////////////////////////////////////////////////////// // Function name: Set_UDMA_Timing // Function: Setting of UltraDMA Timing1, 2 registers // Argument: udma_timing1 : Value set to UltraDMA Timing1 register udma_timing2 : Value set to UltraDMA Timing2 register...
- Page 85 CHAPTER 5 APPLICATION EXAMPLES // ATA command execution function // //////////////////////////////////// ///////////////////////////////////////////////////////////////////////// // Function name: ATA_Set_Features // Function: Executes SET FEATURES command (Protocol:ND, Command:EFh). // // Argument: dev_num : Device selection (0:Master/1:Slave) // Return value: STATUS_SUCCESS : Normal end STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end STATUS_TIMEOUT_INTRQ : INTRQ timeout error end STATUS_IDE_ERROR : Error end after command execution...
- Page 86 CHAPTER 5 APPLICATION EXAMPLES ac.features = 0x00; // Features register ac.sector_count = 0x00; // SectorCount register ac.sector_number = 0x00; // SectorNumber register ac.cylinder_low = 0x00; // CylinderLow register ac.cylinder_high = 0x00; // CylinderHigh register ac.device_head = dev_num<<4; // Device/Head register ac.command = 0xE1;...
- Page 87 CHAPTER 5 APPLICATION EXAMPLES // Function: Executes READ SECTOR(S) command (Protocol:PI, Command:20h).// // Argument: dev_num : Device selection (0:Master/1:Slave) lba : LBA sec_cnt : Number of sectors buff : Buffer pointer // Return value: STATUS_SUCCESS : Normal end STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end STATUS_TIMEOUT_INTRQ : INTRQ timeout error end STATUS_IDE_ERROR : Error end after command execution...
- Page 88 CHAPTER 5 APPLICATION EXAMPLES int status; ATA_COMMAND ac; ac.features = 0x00; // Features register ac.sector_count = sector_count; // SectorCount register ac.sector_number = (lba & 0xFF); // SectorNumber register ac.cylinder_low = (lba>>8 & 0xFF); // CylinderLow register ac.cylinder_high = (lba>>16 & 0xFF); // CylinderHigh register ac.device_head = 0x40|(dev_num<<4)|(lba>>24 &...
- Page 89 CHAPTER 5 APPLICATION EXAMPLES ///////////////////////////////////////////////////////////////////////// // Function name: ATA_Write_DMA // Function: Executes WRITE DMA command (Protocol:DM, Command:CAh). // Argument: dev_num : Device selection (0:Master/1:Slave) lba : LBA sec_cnt : Number of sectors // Return value: STATUS_SUCCESS : Normal end STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end STATUS_TIMEOUT_BSY0_DRQ0 : BSY=0,DRQ=0 timeout error end STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end STATUS_TIMEOUT_INTRQ : INTRQ timeout error end...
- Page 90 CHAPTER 5 APPLICATION EXAMPLES int status; status = Wait_IDE_BSY0_DRQ0(); // Wait until BSY=0, DRQ=0 if ( status != 0 ) { return STATUS_TIMEOUT_BSY0_DRQ0; // Timeout error end *IDEREG_DEVICE_HEAD = dev_num << 4; // Device selection wait(TIMER400ns); // Wait 400 ns status = Wait_IDE_BSY0_DRQ0();...
- Page 91 CHAPTER 5 APPLICATION EXAMPLES *IDEREG_SECTOR_NUMBER = atacom->sector_number; // SectorNumber register *IDEREG_CYLINDER_LOW = atacom->cylinder_low; // CylinderLow register *IDEREG_CYLINDER_HIGH = atacom->cylinder_high; // CylinderHigh register status = Wait_IDE_DRDY1(); // Loop until DRDY=1 if ( status != 0 ) { return STATUS_TIMEOUT_DRDY1 // DRDY1 timeout *IDEREG_COMMAND = atacom->command;...
- Page 92 CHAPTER 5 APPLICATION EXAMPLES ///////////////////////////////////////////////////////////////////////// int ATA_PIO_dataout(ATA_COMMAND *atacom, UHWORD sector_count, void *buff) UBYTE dev, idestat; UWORD *buffp; int i, j, status; buffp = (UWORD*)buff; dev = ( atacom->device_head >> 4 ) & 1; status = ATA_Device_Selection(dev); // DEVICE SELECTION if ( status != 0 ) { return STATUS_TIMEOUT_DEVICE_SELECTION;...
- Page 93 CHAPTER 5 APPLICATION EXAMPLES return STATUS_IDE_ERROR(*IDEREG_ERROR); // Error end (after command execution) return STATUS_SUCCESS; // Normal end ///////////////////////////////////////////////////////////////////////// // Function name: ATA_PIO_nondata // Function: Executes PIO non data command protocol. // Argument: atacom : ATA_COMMAND structure pointer // Return value: STATUS_SUCCESS : Normal end STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end...
- Page 94 CHAPTER 5 APPLICATION EXAMPLES idestat = *IDEREG_ALT_STATUS; // Alt Status register empty read idestat = *IDEREG_STATUS; // Status register read if ( idestat & IDEREG_ERROR_ERR_BIT ) { return STATUS_IDE_ERROR(*IDEREG_ERROR); // Error end (after command execution) return STATUS_SUCCESS; // Normal end ///////////////////////////////////////////////////////////////////////// // Function name: ATA_DMA // Function: Executes DMA command protocol.
- Page 95 CHAPTER 5 APPLICATION EXAMPLES wait(TIMER400ns); // Wait 400 ns idestat = *IDEREG_ALT_STATUS; // Alt Status register empty read *IDEREG_BUSMASTER_START_STOP |= 0x01; // Bus Master Start status = Wait_IDE_BMEND(); if ( status != 0 ) { return STATUS_TIMEOUT_BMEND; // BMEND timeout error end status = Wait_IDE_INTRQ();...
- Page 96 CHAPTER 5 APPLICATION EXAMPLES ///////////////////////////////////////////////////////////////////////////////// // Function name: main // Function: Accesses IDE HDD via PCI bus and PCI-IDE ASIC board. // Argument: None // Return value: 0: Normal end // Overview: Issues IDLE IMMEDIATE, IDENTIFY DEVICE, SET FEATURE, READ SECTOR(S), WRITE SECTOR(S), READ DMA, and WRITE DMA commands.
- Page 97 CHAPTER 5 APPLICATION EXAMPLES // Sets transfer mode to PIO transfer Mode0 using SET_FEATURE command. Set_Transfer_Mode(0, PIO_MODE0); // Sets PIO Timing register of configuration register of // PCI-IDE ASIC board. Set_PIO_Timing(IDE_PIO_TIMING_IDE33MHz_MODE0); // Buffer initialization InitBuffer(wbuff, 4096); ////////////////// // PIO transfer // ////////////////// ATA_Write_Sector( // Issues WRITE SECTOR command.
- Page 98 CHAPTER 5 APPLICATION EXAMPLES dsc_tbl->transfer_address = BASE_ADDRESS_SDRAM; dsc_tbl->transfer_byte = 0x1000; // = 4096byte = 8Sector dsc_tbl->next_table_address = 0x00000001; // Last table *IDEREG_DSCTBL_START_ADDRESS = dsc_tbl; // Sets transfer direction of UltraDMA transfer. *IDEREG_BUSMASTER_START_STOP &= 0xFFFFFEFF; // Ultra DMA (PCI->IDE) // Buffer initialization InitBuffer((UBYTE*)dsc_tbl->transfer_address, 512*8);...
- Page 99 CHAPTER 5 APPLICATION EXAMPLES Figure 5-6. IDE_Write_DMA Function WRITE DMA (Data transfer from SDRAM to IDE HDD) Bus master transfer of 8 sectors (4096 bytes) 700 0000H 6FF FFFFH is performed from 400 0000H (SDRAM area) to LBA0 of IDE HDD. Number of transfer bytes 0000 1000H Descriptor table Transfer address...