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Bus and Memory Control (BCU, MEMC)
15
PA15
Bit Position
15
13 to 0
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7.3.1 BCU registers
The following registers are part of the BCU. They define the usage of the
programmable peripheral I/O area (PPA), the data bus width, the endian format
of word data, and they control access to external devices.
(1)
BPC - Peripheral area selection control register
The 16-bit BPC register defines whether the programmable peripheral I/O area
(PPA) is used or not and determines the starting address of the PPA.
Access
This register can be read/written in 16-bit units.
Address
FFFF F064
H
Initial Value
0000
H
14
13
12
11
10
0
PA13 PA12 PA11 PA10
Table 7-7
BPC register contents
Bit Name
Function
PA15
Select usage of programmable peripheral I/O area (PPA).
0: PPA disabled
1: PPA enabled
PA[13:0]
Bits PA[13:0] specify bits 27 to 14 of the starting address of the PPA. The other bits
of the address are fixed to 0.
Caution
Bit 14 must always be 0.
The base address PBA of the programmable peripheral area sets the start
address of the 16 KB PPA in a range of 256 MB. The 256 MB page is mirrored
16 times to the entire 32-bit address range.
The base address PBA is calculated by
PBA = BPC.PA[13:0] x 2
Table 7-8 shows how the base address PBA of the programmable peripheral
area is assembled.
Table 7-8
Address range of programmable peripheral area (16 KB)
31
...
0
...
...
0
...
0
...
Preliminary User's Manual U17566EE1V2UM00
9
8
7
6
PA9
PA8
PA7
PA6
PA5
14
28 27
...
0
BPC.PA[13:0]
...
0
BPC.PA[13:0]
0
BPC.PA[13:0]
Chapter 7
5
4
3
2
1
PA4
PA3
PA2
PA1
14 13
...
1
0
1
...
1
1
...
0
...
0
1
0
...
0
0
0
PA0
bit
PBA
261
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