NEC V850E/Dx3 Preliminary User's Manual page 169

Clock Generator
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(1) HALT mode
The HALT mode can be entered from normal run mode. In HALT mode, all
clock settings remain unchanged. Only the CPU clock is suspended and hence
program execution.
Table 4-24 Clock Generator status in HALT mode
Item
Main oscillator
Sub oscillator
Ring oscillator
SSCG
PLL
VBCLK (CPU system)
IICLK
PCLK0, PCLK1
PCLK2...PCLK15
SPCLK0, SPCLK1
SPCLK2...SPCLK15
FOUTCLK
WTCLK / LCDCLK
WDTCLK
WCTCLK
The HALT mode can be released by any unmasked maskable interrupt, NMI or
system reset.
On HALT mode release, all clock settings remain unchanged. The CPU clock
resumes operation.
Preliminary User's Manual U17566EE1V2UM00
Status Remarks
unchanged
operates
operates
unchanged
unchanged
suspended Clock setup is unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
Chapter 4
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