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Bus and Memory Control (BCU, MEMC)
BCT0
15
ME3
BCT1
15
ME7
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7.3.2 Memory controller registers (µPD70F3427 only)
The following registers are part of the Memory Controller. They specify the
type of external device that is connected, the number of data wait states, the
number of address wait states, the number of idle states, and they control
features for page ROM.
(1)
BCTn - Bus cycle configuration registers
The 16-bit BCT0 register specifies the external devices that are connected to
the microcontroller device. The register enables the operation of the Memory
Controller for each chip select signal.
Access
These registers can be read/written in 16-bit units.
Address
BCT0: FFFF F480
BCT1: FFFF F482
Initial Value
4444
H
14
13
12
11
10
1
0
BT30 ME2
1
CS3
14
13
12
11
10
1
0
BT70 ME6
1
CS7
Table 7-18
BCTn register contents
Bit Position
15, 11, 7, 3
12, 8, 4, 0
Caution
1.
The bits marked with 0 must always be 0.
2.
The bits marked with 1 must always be 1.
3.
To initialize an external memory area after a reset, registers BCTn have to
be set. Do not change this register after initialization. Do not access external
devices before initialization is finished.
I
Preliminary User's Manual U17566EE1V2UM00
H
H
9
8
7
6
0
BT20 ME1
1
CS2
CS1
9
8
7
6
0
BT60 ME5
1
CS6
CS5
Bit Name
Function
MEk
Enables/disables Memory Controller operation for
chip select area k.
0: Operation disabled
1: Operation enabled
BTk0
Specifies the devices that are connected to chip
select area k.
0: SRAM or external I/O connected
1: Page ROM connected
Chapter 7
5
4
3
2
1
0
BT10 ME0
1
0
CS0
5
4
3
2
1
0
BT50 ME4
1
0
CS4
0
BT00
0
BT40
271
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