External Trigger Pulse Output Mode (Tpnmd2 To Tpnmd0 = 010) - NEC V850E/Dx3 Preliminary User's Manual

Chapter 11
TIPn0 pin
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11.5.3 External trigger pulse output mode
(TPnMD2 to TPnMD0 = 010)
In the external trigger pulse output mode, 16-bit timer/event counter P waits for
a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an
external trigger input signal is detected, 16-bit timer/event counter P starts
counting, and outputs a PWM waveform from the TOPn1 pin.
Pulses can also be output by generating a software trigger instead of using the
external trigger. When using a software trigger, a square wave that has one
cycle of the PWM waveform as half its cycle can also be output from the
TOPn0 pin.
Edge
detector
Software trigger
generation
Count
Count
clock
selection
control
TPnCE bit
Figure 11-14 Configuration in external trigger pulse output mode
Preliminary User's Manual U17566EE1V2UM00
TPnCCR1 register
CCR1 buffer register
Match signal
start 16-bit counter
Match signal
CCR0 buffer register
TPnCCR0 register
16-bit Timer/Event Counter P (TMP)
Transfer
Output
S
controller TOPn1 pin
R
(RS-FF)
INTTPnCC1 signal
Clear
Output
TOPn0 pin
controller
INTTPnCC0 signal
Transfer