In-Service Priority Register (Ispr); Maskable Interrupt Status Flag (Id) - NEC V850E/MS1 UPD703100 User Manual

7.3.5 In-service priority register (ISPR)

This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request
is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set (1) and
remains set while the interrupt is serviced.
When the RETI instruction is executed, the bit corresponding to the interrupt request having the highest priority is
automatically cleared (0) by hardware. However, it is not cleared (0) when execution is returned from non-maskable
interrupt servicing or exception processing.
This register is read-only in 8- or 1-bit units.
7 6
ISPR ISPR7 ISPR6
Bit Position Bit Name
7 to 0 ISPR7 to ISPR0
Remark n = 0 to 7 (priority level)

7.3.6 Maskable interrupt status flag (ID)

The ID flag is bit 5 of the PSW.
This controls the maskable interrupt's operating state, and stores control information on enabling/disabling
acknowledgement of interrupt requests.
31
PSW
0 0 0 0
Bit Position Bit Name
5 ID
218
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
5 4 3
ISPR5 ISPR4 ISPR3
In-Service Priority Flag
Indicates priority of interrupt currently acknowledged.
0: Interrupt request with priority n not acknowledged
1: Interrupt request with priority n acknowledged
0 0 0 0 0 0 0 0 0 0 0
Interrupt Disable
Indicates whether maskable interrupt processing is enabled or disabled.
0: Maskable interrupt acknowledgement enabled
1: Maskable interrupt acknowledgement disabled (pending)
It is set to 1 by the DI instruction and reset to 0 by the EI instruction. Its value is
also modified by the RETI instruction or LDSR instruction when referencing the
PSW.
Non-maskable interrupts and exceptions are acknowledged regardless of this
flag. When a maskable interrupt is acknowledged, the ID flag is automatically
set to 1 by hardware.
The interrupt request generated during the acknowledgement disabled period
(ID = 1) is acknowledged when the xxIFn bit of xxICn is set to 1, and the ID flag
is cleared to 0.
User's Manual U12688EJ4V0UM00
2 1 0
ISPR2 ISPR1 ISPR0
Function
8 7 6 5
0 0 0 0 0 0 0 0 0 NP EP ID
Function
Address After reset
FFFFF166H 00H
4 3 2 1 0
After reset
SAT CY OV S Z
00000020H