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Chapter 13
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13.8 Match and Clear Mode
The match and clear mode is mainly used reduce the number of valid bits of
the counters (TMGn0, TMGn1).
Therefore the fixed assigned register GCCn0 (GCCn1) is used to compare its
value with the counter TMGn0 (TMGn1). If the values match, than an interrupt
is generated and the counter is cleared. Than the counter starts up counting
again.
(1)
Capture operation (match and clear)
Basic settings (m = 1 to 4):
Bit
CCSGn0
CCSGn5
SWFGnm
CCSGnm
TBGnm
(a) Example: Pulse width measurement or period measurement of the
TIGnm input signal
Setting method:
(1)
When using one of TOGn1 to TOGn4-pin, select the corresponding
counter with the TBGnm bit. When CCSGn0 = 1, TI0 cannot be used.
When CCSGn5 = 1, TIGn5 cannot be used.
(2)
Select a count clock cycle with the CSE12 to CSE10 (TMGn1) bits or
CSE02 to CSE00 (TMGn0) bits.
(3)
Select a valid TIGnm edge with the IEGnm1 and IEGnm0 bit. A rising
edge, falling edge, or both edges can be selected.
(4)
Set an upper limit on the value of the counter in GCCn0 or GCCn5.
(5)
Start timer operation by setting POWERn bit and TMGn0E bit (or
TMGn1E bit).
Operation:
(1)
When a specified edge is detected, the value of the counter is stored in
GCCnm, and an edge detection interrupt (INTCCGnm) is output.
(2)
When the value of GCCn0 or GCCn5 matches the value of the counter,
INTCCGn0 (INTCCGn5) is output, and the counter is cleared. This
operation is referred to as "match and clear".
(3)
If a match and clear event has occurred between capture operations, the
CCFGny flag is set when GCCny is read. Correct capture data by
checking the value of CCFGny.
Preliminary User's Manual U17566EE1V2UM00
16-bit Multi-Purpose Timer G (TMG)
Value
Remark
1
match and clear mode
1
0
disable TOGnm
0
Capture mode for GCCnm
assign counter
for GCCnm
X
0: TMGn0
1: TMGn1
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