Byte Access With 8-Bit Bus Or Byte/Half Word Access With 16-Bit Bus - NEC V850E/Dx3 Preliminary User's Manual

Chapter 7
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7.7.2 Byte access with 8-bit bus or byte/half word access with 16-
bit bus
(1) Read operation
Note that during on-page access, less data wait states are inserted than during
off-page access.
T1
BCLK
A[23:0] (output)
CSk (output)
RD (output)
WR (output)
D[7:0] (I/O)
D[15:0] (I/O)
WAIT (input)
Figure 7-19 Reading page ROM
Register settings:
• BCTm.BTk0 = 1 (connected external device is page ROM)
• ASC.ACk[1:0] = 00
• DWCm.DWk[2:0] = 010
access inserted)
• PRC.PRW[2:0] = 001
access inserted)
• BCC.BCk[1:0] = 00
Note 1. The circles indicate the sampling timing.
2. The broken line indicates the high-impedance state (bus is not driven).
Preliminary User's Manual U17566EE1V2UM00
Bus and Memory Control (BCU, MEMC)
TW TW T2 TO1
Off-page address
Data
(no address setup wait states inserted)
B
(two programmable data wait states for off-page
B
(one programmable data wait state for on-page
B
(no idle states inserted)
B
TOW TO2
On-page address
Data