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LCD Bus Interface (LCD-I/F)
LBDATA0
LBCTL0.TPF0
LBCTL0.BYF0
LBCTL .EL=0
LBCTL .EL=1
DBWR(R/W)
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Reading bytes
The following figure shows a byte read operation in mod68 mode.
Dummy read byte from LBDATA0 register
SPCLK
INTLCD
DBRD(E)
DBRD(E)
st
DBD[7:0]
1
Byte
Figure 23-7
Timing (mod68: LBTCTL0.IMD0 = 1): read consecutive bytes,
LBWST0.WST0 = 4, LBCYC0.CYC0 = 7, LBTCTL0.TCIS0 = 0
Note
The timing diagrams are for functional explanation purposes only without any
relevance to the real hardware implementation.
Sequence
1. A dummy read to the LBDATA0 register starts the transfer of one byte from
the external LCD controller. The busy flag LBCTL0.BYF0 is set
immediately. The "transfer in progress" flag LBCTL0.TPF0 is set on the
rising edge of the clock.
The data that is read from LBDATA0 belongs to a previous transfer and
may be ignored.
2. When the data on the LCD Bus Interface is sampled, LBCTL0.BYF0 is
cleared and the data is available in LBDATA0. The interrupt output INTLCD
becomes active for one clock cycle.
3. A new read to LBDATA0 is performed while the previous transfer has not
been finished (cycle time not elapsed). The busy flag LBCTL0.BYF0 is set
immediately, but the new transfer is started after the previous one is
complete. The "transfer in progress flag" LBCTL0.TPF0 remains set.
The data that is read from LBDATA0 is the first LCD data byte.
4. Again, the data that has been sampled is available in LBDATA0 and the
busy flag LBCTL0.BYF0 is cleared.
5. Steps 2 to 4 are repeated until the last byte to be read has been sampled.
6. The last byte is not read from the LBDATA0 register but from LBDATAR0 in
order to avoid a further read transfer on the LCD bus.
Preliminary User's Manual U17566EE1V2UM00
nd
Read 2
byte from LBDATA0 register
st
Read 1
byte from LBDATA0 register
st
nd
1
Byte
2
Byte
nd
2
Byte
sample point
Chapter 23
rd
Read 3
byte from LBDATA0 R register
without initiating a new transfer
rd
3
Byte
rd
3
Byte
839
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