Voltage Comparator
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27.3 Timing
The following figure shows the timing of the Voltage Comparator 0. In this
example, the interrupt INTVCn is generated at the falling edge
(VCCTLn.ESTn[1:0] = 00
External voltage
Internal reference
voltage
Delay
VCMPO0
INTVCn
VCSTRn.VCFn
Figure 27-2
Voltage Comparator timing
Note
For details on the delay time refer to the Electrical Target Specification.
Preliminary User's Manual U17566EE1V2UM00
) of the comparator's output signal.
B
Delay
Delay
Delay
Chapter 27
Time
Delay
875