System Register Set - NEC V850E/Dx3 Preliminary User's Manual

CPU System Functions
System register
regID
0
1
2
3
4
5
6 to 15
16
17
18
19
20
21 to 31
a)
Reading from this register is only enabled between a DBTRAP exception (exception handler address
0000 0060
upon ILGOP and ROM Correction detections (refer to "Interrupt Controller (INTC)" on page 187 and "ROM
Correction Function (ROMC)" on page 331).
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3.2.2 System register set

System registers control the status of the CPU and hold interrupt information.
Additionally, the program counter holds the instruction address during program
execution.
To read/write the system registers, use instructions LDSR (load to system
register) or STSR (store contents of system register), respectively, with a
specific system register number (regID) indicated below.
The program counter states an exception. It cannot be accessed via LDSR or
STSR instructions. No regID is allocated to the program counter.
Example STSR 0, r2
Stores the contents of system register 0 (EIPC) in general purpose register r2.
The table below gives an overview of all system registers and their system
numbers register number (regID). It shows whether a load/store instruction is allowed (
for the register or not (
Table 3-3 System register numbers
System register name
Status saving register during interrupt
(stores contents of PC)
Status saving register during interrupt
(stores contents of PSW)
Status saving register during non-maskable interrupts
(stores contents of PC)
Status saving register during non-maskable interrupts
(stores contents of PSW)
Interrupt source register
Program status word
Reserved (operations that access these register numbers
cannot be guaranteed).
Status saving register during CALLT execution
(stores contents of PC)
Status saving register during CALLT execution
(stores contents of PSW)
Status saving register during exception/debug trap
(stores contents of PC)
Status saving register during exception/debug trap
(stores contents of PSW)
CALLT base pointer
Reserved (operations that access these register numbers
cannot be guaranteed).
) and the exception handler terminating DBRET instruction. DBTRAP exceptions are generated
H
Preliminary User's Manual U17566EE1V2UM00
).
–
Shortcut
EIPC
EIPSW
FEPC
FEPSW
ECR
PSW
CTPC
CTPSW
DBPC
DBPSW
CTBP
Chapter 3
)
×
Operand specification
LDSR STSR
× ×
× ×
× ×
× ×
– ×
× ×
– –
× ×
× ×
a
× ×
a
× ×
× ×
– –
107