NEC V850E/Dx3 Preliminary User's Manual page 568

Chapter 17
568
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(5) Continuous reception
Yes
CBnRX register read
CBnOVE bit clear
(CBnSTR)
Note Set the CBnSCE bit to 1 in the initial setting.
Caution In the master mode, the clock is output without limit when dummy data is read
from the CBnRX register. To stop the clock, execute the flow marked
above flowchart.
In the slave mode, malfunction due to noise during communication can be
prevented by executing the flow marked
Before resuming communication, set the CBnCTL0.CBnSCE bit to 1, and read
dummy data from the CBnRX register.
Preliminary User's Manual U17566EE1V2UM00
START
Note
Initial setting (CBnCTL0 ,
CBnCTL1 registers, etc.)
CBnRX register dummy read
(start reception)
No
INTCBnR bit = 1?
Yes
CBnOVE bit = 1?
(CBnSTR)
No
No
Is data being
received last data?
Yes
CBnSCE bit = 0
(CBnCTL0)
CBnRX register read
No
INTCBnR bit = 1?
Yes
CBnRX register read
CBnSCE bit = 1
(CBnCTL0)
END
in the above flowchart.
Clocked Serial Interface (CSIB)
CBnRX register read
in the