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16-bit Multi-Purpose Timer G (TMG)
Compare mode
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GCCn0, GCCn5 - Timer Gn capture/compare registers of the 2 counters
The GCCn0, GCCn5 registers are 16-bit capture/compare registers of Timer
Gn. These registers are fixed assigned to the counter registers:
• GCCn0 is fixed assigned to timebase TMGn0
• GCCn5 is fixed assigned to timebase TMGn1
Capture mode
In the capture register mode, GCCn0 (GCCn5) captures the TMGn0 (TMGn1)
count value if an edge is detected at Pin TIGn0 (TIGn5).
In the compare register mode, GCCn0 (GCCn5) detects match with TMGn0
(TMGn1) and clears the assigned Timebase. So this "match and clear mode"
is used to reduce the number of valid bits of the counter TMGn0 (TMGn1).
Caution
If in Compare Mode write to this registers before POWERn and ENFGnx bit
are "1" at the same time.
Access
In capture mode, these registers can be read in 16-bit units.
In compare mode, these registers can be read/written in 16-bit units.
Address
GCCn0:
GCCn5:
Initial Value
0000
. These registers are cleared by any reset.
H
15
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Preliminary User's Manual U17566EE1V2UM00
<base> + C
H
<base> + 16
H
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8
GGCn0/GGCn5 value
R/W
Chapter 13
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