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16-bit Multi-Purpose Timer G (TMG)
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ENFG0
0FFFH
Ma tch
TM G n0
GCCn1
INTTGnCC1
INTTGnCC0
Figure 13-13
Timing of compare operation (match and clear)
In this example, the data N is set in GCCn1, and TMGn0 is selected.
0FFFH is set in GCCn0. Here, N < 0FFFH.
(b) When 0000H is set in GCCn0 or GCCn5 (match and clear)
When 0000H is set in GCCn0 or GCCn5, the value of the counter is fixed at
0000H, and does not operate. Moreover, INTCCGn0 (or INTCCGn5) continues
to be active.
(c) When FFFFH is set in GCCn0 or GCCn5 (match and clear)
When FFFFH is set in GCCn0 or GCCn5, operation equivalent to the free-run
mode is performed. When an overflow occurs, INTTMGn0 (or INTTMGn1) is
generated, but INTCCGn0 (or INTCCGn5) is not generated.
(d) When 0000H is set in GCCnm (m = 1 to 4) (match and clear)
INTCCGnm is activated when the value of the counter becomes 0001H.
Note, however, that even if no data is set in GCCnm, INTCCGnm is activated
immediately after the counter starts.
(e) When a value exceeding the value of GCCn0 or GCCn5 is set in
GCCnm (m = 1 to 4) (match and clear)
INTCCGnm is not generated.
Preliminary User's Manual U17566EE1V2UM00
0FFFH
0FFFH
N
Chapter 13
465
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