In-Service Priority Register (Ispr) - NEC PD703114 User Manual

7.3.6 In-service priority register (ISPR)

This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is
acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains
set while the interrupt is serviced.
When the RETI instruction is executed, the bit corresponding to the interrupt request having the highest priority is
automatically cleared to 0 by hardware. However, it is not cleared to 0 when execution is returned from non-maskable
interrupt servicing or exception processing.
This register is read-only, in 8-bit or 1-bit units.
Caution In the interrupt enabled (EI) state, if an interrupt is acknowledged during the reading of the ISPR
register, the value of the ISPR register may be read after the bit is set (1) by this interrupt
acknowledgment.
acknowledgment, read it in the interrupt disabled (DI) state.
<7> <6>
ISPR ISPR7 ISPR6
Bit position
7 to 0 ISPR7 to ISPR0
Remark n = 0 to 7 (priority level)
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
To read the value of the ISPR register properly before interrupt
<5> <4> <3>
ISPR5 ISPR4 ISPR3
Bit name
Indicates priority of interrupt currently acknowledged
0: Interrupt request with priority n not acknowledged
1: Interrupt request with priority n acknowledged
User's Manual U15195EJ5V0UD
<2> <1> <0>
ISPR2 ISPR1 ISPR0
Function
Address After reset
FFFFF1FAH 00H