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Chapter 11
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FFFFH
16-bit counter
0000H
TPnCE bit
INTTPnOV signal
TPnOVF bit
Note
TPnOVF0 flag
TIPn0 pin input
TPnCCR0 register
Note
TPnOVF1 flag
TIPn1 pin input
TPnCCR1 register
Figure 11-34
Example when two capture registers are used (without using overflow
interrupt)
Note
The TPnOVF0 and TPnOVF1 flags are set on the internal RAM by software.
<1> Read the TPnCCR0 register (setting of the default value of the TIPn0
pin input).
<2> Read the TPnCCR1 register (setting of the default value of the TIPn1
pin input).
<3> An overflow occurs. Nothing is done by software.
<4> Read the TPnCCR0 register.
Read the overflow flag. If the overflow flag is 1, set only the TPnOVF1
flag to 1, and clear the overflow flag to 0.
Because the overflow flag is 1, the pulse width can be calculated by
(10000H + D
<5> Read the TPnCCR1 register.
Read the overflow flag. Because the overflow flag is cleared in <4>, 0
is read.
Read the TPnOVF1 flag. If the TPnOVF1 flag is 1, clear it to 0.
Because the TPnOVF1 flag is 1, the pulse width can be calculated by
(10000H + D
<6> Same as <3>
Preliminary User's Manual U17566EE1V2UM00
D
10
D
01
D
00
D
00
D
10
<1>
<2>
<3>
- D
).
01
00
- D
) (correct).
11
10
16-bit Timer/Event Counter P (TMP)
D
11
D
01
D
11
<4>
<5> <6>
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