NEC V850E/Dx3 Preliminary User's Manual page 95

Pin Functions
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Table 2-54 DFEN0 register contents
Bit position
15 to 0
Table 2-55 Assignment of input signals to bit positions for register DFEN0
Bit
Bit name
position
0 DFENC0
1 DFENC1
2 DFENC2
3 DFENC3
4 DFENC4
5 DFENC5
6 DFENC6
7 DFENC7
8 DFENC8
9 DFENC9
10 DFENC10 TIP20
11 DFENC11 TIP21
12 DFENC12 TIP30
13 DFENC13 TIP31
14 DFENC14 TIG01
15 DFENC15 TIG02
a)
Note that for high clock rates of the Clocked Serial Interface, the digital filter should
be disabled. Otherwise, desired input pulses may be removed by the digital filter.
Preliminary User's Manual U17566EE1V2UM00
Bit name
Enables/disables the digital noise elimination filter for
the corresponding input signal:
0: Digital filter is disabled.
DFENC[15:0]
1: Digital filter is enabled.
For an assignment of bit positions to input signals see
table Table 2-55.
Input signal Description
SIB0 CSIB0 data input
SIB1 CSIB1 data input
SIB2 CSIB2 data input
SCKIB0 CSIB0 clock input
SCKIB1 CSIB1 clock input
SCKIB2 CSIB2 clock input
TIP00 Timer TMP0 channel 0 capture input
TIP01 Timer TMP0 channel 1 capture input
TIP10 Timer TMP1 channel 0 capture input
TIP11 Timer TMP1 channel 1 capture input
Timer TMP2 channel 0 capture input
Timer TMP2 channel 1 capture input
Timer TMP3 channel 0 capture input
Timer TMP3 channel 1 capture input
Timer TMG0 channel 1 capture input
Timer TMG0 channel 2 capture input
Chapter 2
Function
a
a
a
a
a
a
95