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Bus and Memory Control (BCU, MEMC)
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7.2.7 Initialization for access to external devices
To enable access to external devices, initialize the following registers after any
reset.
1. Chip area select control registers CSCn
Define the memory banks that are allocated to external devices. Memory
banks that are not allocated to external devices, must be deactivated.
2. Bus cycle type configuration registers BCTn
Specify the external devices that are connected to the microcontroller
device. For memory banks that are not allocated to external devices, the
corresponding bits in registers BCT0 and BCT1 should be reset.
3. LOcal bus size configuration register LBS
Set the data bus width for the active chip select areas.
4. Data wait control registers DWCn
Set the number of data wait states with respect to the starting bus cycle.
5. Bus cycle control register BCC
Set the number of idle states for each chip select area.
6. Page ROM configuration register PRC
If page ROM mode is selected (BCTn.BTk0 = 1), set whether a page ROM
cycle is on-page or off-page.
7. Endian configuration register (BEC)
Set the endian format for each chip select area.
8. Address setup wait control register (ASC)
Set the number of address setup wait states for each chip select area.
9. Read delay control register (RDDLY)
Activate the delay of the rising edge of RD strobe, as required.
Caution
1.
Do not change these registers after initialization.
2.
Do not access external devices before initialization is finished.
7.2.8 External bus mute function
If no access via the external memory interface is performed the external bus is
set into a mute status. During mute the external bus interface pins take
following states:
• A[22:0]: hold the address of the last external access
• D[31:0]: 3-state
• WR, RD, CS0, CS1, CS3, CS4: high level (inactive state)
Preliminary User's Manual U17566EE1V2UM00
Chapter 7
259
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