NEC V850E/Dx3 Preliminary User's Manual page 545

32-bit single-chip microcontroller
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Clocked Serial Interface (CSIB)
Bit position
4
1
0
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Table 17-3
CBnCTL0 register contents (2/2)
Bit name
Function
CBnDIR
Transfer direction mode specification (MSB/LSB):
0: MSB first transfer
1: LSB first transfer
CBnTMS
Transfer direction mode specification (MSB/LSB):
0: Single transfer mode
1: Continuous transfer mode
CBnSCE
Transfer direction mode specification (MSB/LSB):
0: Communication start trigger invalid
1: Communication start trigger valid
• In master mode
This bit enables or disables the communication start trigger.
(a)In single transmission or transmission/reception mode, or continuous
transmission or continuous transmission/reception mode
A communication operation can be started only when the CBnSCE bit is
1.
Set the CBnSCE bit to 1.
(b)In single reception mode
Clear the CBnSCE bit to 0 before reading the receive data
(CBnRX register).
If the CBnSCE bit is read while it is 1, the next communication operation is
started.
(c)In continuous reception mode
Clear the CBnSCE bit to 0 one communication clock before reception of
the last data is completed
The CBnSCE bit is not cleared to 0 one communication clock before the
completion of the last data reception, the next communication operation is
automatically started.
• In slave mode
This bit enables or disables the communication start trigger.
Set the CBnSCE bit to 1.
Preliminary User's Manual U17566EE1V2UM00
Chapter 17
545

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