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NEC V850E/IA3 User Manual

NEC V850E/IA3 User Manual

32-bit single-chip microcontrollers

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User's Manual

V850E/IA3, V850E/IA4

32-bit Single-Chip Microcontrollers

Hardware

V850E/IA3:

μ

PD703183

μ

PD70F3184

V850E/IA4:

μ

PD703185

μ

PD703186

μ

PD70F3186

Document No. U16543EJ4V0UD00 (4th edition)

Date Published

April 2008 N

Printed in Japan

2003

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Page 1 User’s Manual V850E/IA3, V850E/IA4 32-bit Single-Chip Microcontrollers Hardware V850E/IA3: μ PD703183 μ PD70F3184 V850E/IA4: μ PD703185 μ PD703186 μ PD70F3186 Document No. U16543EJ4V0UD00 (4th edition) Date Published April 2008 N 2003 Printed in Japan...
Page 2 [MEMO] User’s Manual U16543EJ4V0UD...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 This manual is intended to give users an understanding of the hardware functions. Organization The V850E/IA3, V850E/IA4 User’s Manual is divided into two parts: Hardware (this manual) and Architecture (V850E1 Architecture User’s Manual). The organization of each manual is as follows:...
Page 6 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the bottom Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark:...
Page 7 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850E/IA3 and V850E/IA4 Document Name Document No. V850E1 Architecture User’s Manual U14559E V850E/IA3, V850E/IA4 Hardware User’s Manual...
Page 8: Table Of Contents
V850E/IA3 ...........................18 1.2.1 Features (V850E/IA3) ........................18 1.2.2 Applications (V850E/IA3) ......................20 1.2.3 Ordering information (V850E/IA3)....................20 1.2.4 Pin configuration (V850E/IA3).......................21 1.2.5 Function blocks (V850E/IA3) ......................23 V850E/IA4 ...........................26 1.3.1 Features (V850E/IA4) ........................26 1.3.2 Applications (V850E/IA4) ......................28 1.3.3 Ordering information (V850E/IA4)....................28 1.3.4 Pin configuration (V850E/IA4).......................29 1.3.5...
Page 9 4.2.1 V850E/IA3 ............................ 82 4.2.2 V850E/IA4 ............................ 83 Port Configuration ........................84 4.3.1 Port 0............................89 4.3.2 Port 1............................96 4.3.3 Port 2 (V850E/IA4 only) ......................105 4.3.4 Port 3............................111 4.3.5 Port 4............................122 4.3.6 Port 5 (V850E/IA4 only) ......................129 4.3.7...
Page 10 Overview ..........................274 Functions ..........................275 Configuration.......................... 275 Registers ..........................279 Timer Output Operations....................... 295 Operation ..........................296 7.6.1 Interval timer mode (TQnMD2 to TQnMD0 = 000)..............304 7.6.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) ...........316 7.6.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) ........326 7.6.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011)..........340...
Page 11 CHAPTER 11 WATCHDOG TIMER FUNCTIONS................486 11.1 Functions ..........................486 11.2 Configuration ..........................486 11.3 Control Registers........................487 11.4 Operation ..........................488 11.5 Caution.............................488 CHAPTER 12 A/D CONVERTERS 0 AND 1..................489 12.1 Features ...........................489 12.2 Configuration ..........................491 12.3 Control Registers........................498 12.4 Operation ..........................509 12.4.1 Basic operation........................... 509 12.4.2 Operation mode and trigger mode ....................
Page 12 13.7.1 Writing to the ADA2CTL1 and ADA2CTL3 registers during conversion........569 13.7.2 Conflict with timing of storing data in the conversion result register..........569 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ..........571 14.1 Mode Switching Between UARTA1 and CSIB1 ..............571 14.2 Features ..........................
Page 13 16.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3)..............649 16.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) ............ 650 16.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)............652 16.3.6 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) .............. 654 16.4 Transfer Modes ........................658 16.4.1 Single transfer mode ........................
Page 14 CHAPTER 18 STANDBY FUNCTION ....................706 18.1 Overview ..........................706 18.2 Control Registers ........................708 18.3 HALT Mode ..........................710 18.3.1 Setting and operation status .......................710 18.3.2 Releasing HALT mode........................710 18.4 IDLE Mode..........................712 18.4.1 Setting and operation status .......................712 18.4.2 Releasing IDLE mode .........................712 18.5 STOP Mode ..........................
Page 15 22.5.3 Standard self programming flow ....................761 22.5.4 Flash functions ........................... 762 22.5.5 Pin processing ..........................762 22.5.6 Internal resources used ......................763 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3)............764 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4)............782 CHAPTER 25 PACKAGE DRAWINGS....................801 CHAPTER 26 RECOMMENDED SOLDERING CONDITIONS ............804 APPENDIX A CAUTIONS........................805...
Page 16: Chapter 1 Introduction
V850E/IA3 and V850E/IA4. 1.1 Overview The V850E/IA3 and V850E/IA4 are 32-bit single-chip microcontrollers that integrate the V850E1 CPU, which is a 32-bit RISC-type CPU core for ASIC, newly developed as the CPU core central to system LSI for the current age of system-on-chip.
Page 17 CHAPTER 1 INTRODUCTION Table 1-1 shows the differences in functions between the V850E/IA3 and V850E/IA4. Table 1-1. Differences in Functions Between V850E/IA3 and V850E/IA4 Item V850E/IA3 V850E/IA4 Internal ROM/RAM (mask ROM version) 128 KB/6 KB 128 KB/6 KB 256 KB/12 KB...
Page 18: V850E/Ia3
CHAPTER 1 INTRODUCTION 1.2 V850E/IA3 1.2.1 Features (V850E/IA3) Minimum instruction execution time: 15.6 ns (at internal 64 MHz operation) General-purpose registers: 32 bits × 32 Signed multiplication (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64 bits):...
Page 19 CHAPTER 1 INTRODUCTION Timer/counter function: 16-bit up/down counter/timer (TMENC) for 2-phase encoder input: 1 channel 16-bit interval timer M (TMM): 1 channel 16-bit timer/event counter Q (TMQ): 2 channels 16-bit timer/event counter P (TMP): 4 channels Motor control function (uses timer TMQ: 1 channel (TMQ0), TMP: 1 channel (TMP0)) 16-bit accuracy 6-phase PWM function with deadtime: 1 channel High-impedance output control function Timer tuning operation function...
Page 20: Applications (V850E/Ia3)
CHAPTER 1 INTRODUCTION 1.2.2 Applications (V850E/IA3) • Commercial equipment (such as inverter air conditioners, washing machines, driers, refrigerators, etc.) • Industrial equipment (such as motor control and general-purpose inverters, etc.) 1.2.3 Ordering information (V850E/IA3) Part Number Package Internal ROM/Flash Memory μ...
Page 21: Pin Configuration (V850E/Ia3)
CHAPTER 1 INTRODUCTION 1.2.4 Pin configuration (V850E/IA3) • 80-pin plastic QFP (14 × 14) μ PD703183GC-xxx-8BT-A μ PD70F3184GC-8BT-A Top view ANI00 PDL9 PDL8 ANI01 P70/ANI20 PDL7 P71/ANI21 PDL6 Note 1 P72/ANI22 PDL5/FLMD1 P73/ANI23 PDL4 PDL3 PDL2 CMPREF PDL1 P74/ANI24 PDL0...
Page 22 CHAPTER 1 INTRODUCTION Pin Identification (V850E/IA3) ADTRG0, ADTRG1: A/D trigger input TOP2OFF, TOQ0OFF: Timer output off ANI00, ANI01, TRGQ0: Timer trigger input ANI10 to ANI13, TXDA0, TXDA1: Transmit data ANI20 to ANI25: Analog input Power supply Analog power supply Ground...
Page 23: Function Blocks (V850E/Ia3)
CHAPTER 1 INTRODUCTION 1.2.5 Function blocks (V850E/IA3) (1) Internal block diagram INTC INTP0, INTP2 to INTP7 Instruction queue TCLR10, TIUD10, TCUD10 TMENC ×1 ch Multiplier TO10 (32 × 32 → 64) 32-bit barrel shifter ×1 ch ROMC System registers TIQ00 to TIQ03, EVTQ0,...
Page 24 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (32 bits × 32 bits → 64 bits) and a barrel shifter (32 bits), help accelerate complex processing.
Page 25 (i) Serial interface The V850E/IA3 includes four serial interface channels: for two asynchronous serial interface A (UARTA) channels and two clocked serial interface B (CSIB) channels. Of these, UARTA1 and CSIB1 share a pin. For UARTA, data is transferred via the TXDAn and RXDAn pins (n = 0, 1).
Page 26: V850E/Ia4
CHAPTER 1 INTRODUCTION 1.3 V850E/IA4 1.3.1 Features (V850E/IA4) Minimum instruction execution time: 15.6 ns (at internal 64 MHz operation) General-purpose registers: 32 bits × 32 Signed multiplication (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64 bits): CPU features: 1 to 2 clocks Saturated operation instructions (with overflow/underflow detection function)
Page 27 CHAPTER 1 INTRODUCTION Timer/counter function: 16-bit up/down counter/timer (TMENC) for 2-phase encoder input: 2 channels 16-bit interval timer (TMM): 1 channel 16-bit timer/event counter (TMQ): 2 channels 16-bit timer/event counter (TMP): 4 channels Motor control function (uses timer TMQ: 2 channels (TMQ0 and TMQ1), TMP: 2 channels (TMP0 and TMP1)) 16-bit accuracy 6-phase PWM function with deadtime: 2 channels High-impedance output control function...
Page 28: Applications (V850E/Ia4)
CHAPTER 1 INTRODUCTION 1.3.2 Applications (V850E/IA4) • Commercial equipment (such as inverter air conditioners, washing machines, driers, refrigerators, etc.) • Industrial equipment (such as motor control and general-purpose inverters, etc.) 1.3.3 Ordering information (V850E/IA4) Part Number Package Internal ROM/Flash Memory μ...
Page 29: Pin Configuration (V850E/Ia4)
CHAPTER 1 INTRODUCTION 1.3.4 Pin configuration (V850E/IA4) • 100-pin plastic LQFP (fine pitch) (14 × 14) μ PD703185GC-xxx-8EU-A μ PD703186GC-xxx-8EU-A μ PD70F3186GC-8EU-A Top view ANI00 PDL9 ANI01 PDL8 ANI02 ANI03 P70/ANI20 PDL7 P71/ANI21 PDL6 Note 1 P72/ANI22 PDL5/FLMD1 P73/ANI23 PDL4 PDL3 PDL2 CMPREF...
Page 30 CHAPTER 1 INTRODUCTION • 100-pin plastic QFP (14 × 20) μ PD703185GF-xxx-3BA-A μ PD703186GF-xxx-3BA-A μ PD70F3186GF-3BA-A Top view P30/RXDA0 PDL8 PDL9 P44/TOP01/TIP01 PDL10 PDL11 P43/TOP00/TIP00 PDL12 RESET PDL13 PDL14 PDL15 Note 1 P50/DDI /TIUD11/TO11 Note 1 P51/DCK /TCUD11 P25/TOQ1B3 Note 1 P24/TOQ1T3 P52/DMS /TCLR11...
Page 31 CHAPTER 1 INTRODUCTION Pin Identification (V850E/IA4) ADTRG0, ADTRG1: A/D trigger input TO10, TO11, ANI00 to ANI03, TOP00, TOP01, ANI10 to ANI13, TOP21, TOP31, ANI20 to ANI27: Analog input TOQ0B1 to TOQ0B3, Analog power supply TOQ0T1 to TOQ0T3, Analog ground TOQ00 to TOQ03, CMPREF: Comparator reference voltage TOQ1B1 to TOQ1B3,...
Page 32: Function Blocks (V850E/Ia4)
CHAPTER 1 INTRODUCTION 1.3.5 Function blocks (V850E/IA4) (1) Internal block diagram INTC INTP0 to INTP7 Instruction TCLR10, TCLR11, queue TIUD10, TIUD11, TMENC TCUD10, TCUD11 ×2 ch Multiplier TO10, TO11 (32 × 32 → 64) 32-bit barrel shifter ×1 ch ROMC System registers TIQ00 to TIQ03, EVTQ0, TRGQ0,...
Page 33 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (32 bits × 32 bits → 64 bits) and a barrel shifter (32 bits), help accelerate complex processing.
Page 34 CHAPTER 1 INTRODUCTION (g) Timer/counter This unit incorporates two 16-bit up/down counter/timer (TMENC1) channels for 2-phase encoder input, one 16-bit interval timer (TMM) channel, two 16-bit timer/event counter (TMQ) channels, and four 16-bit timer/event counter (TMP) channels, and can measure pulse interval widths or frequency, enable an inverter function for motor control, and output a programmable pulse.
Page 35: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS The names and functions of the pins in the V850E/IA3 and V850E/IA4 are listed below. These pins can be divided into port pins and non-port pins according to their function. 2.1 List of Pin Functions There are two power supplies for the I/O buffer of a pin: AV and EV .
Page 36 SCKB1 pin)). TCUD10 TCLR10 Note V850E/IA4 only Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20) User’s Manual U16543EJ4V0UD...
Page 37 Notes 1. V850E/IA4 only μ PD70F3186 (V850E/IA4) only Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20) User’s Manual U16543EJ4V0UD...
Page 38 Note PD70F3184 (V850E/IA3), PD70F3186 (V850E/IA4) only Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20) User’s Manual U16543EJ4V0UD...
Page 39 4. For details on the power supply connection specifications, see 12.2 Configuration. Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20) User’s Manual U16543EJ4V0UD...
Page 40 GC (V850E/IA4): 39, 72, 91 GF (V850E/IA4): 19, 67, 100 Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20) User’s Manual U16543EJ4V0UD...
Page 41 Notes 1. V850E/IA4 only μ PD70F3186 (V850E/IA4) only Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20) User’s Manual U16543EJ4V0UD...
Page 42 GF (V850E/IA4): 13, 59, 79, 93 Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20) User’s Manual U16543EJ4V0UD...
Page 43: Pin I/O Circuits And Recommended Connection Of Unused Pins
TIUD10/TO10 TCUD10 TCLR10 Note V850E/IA4 only Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20) User’s Manual U16543EJ4V0UD...
Page 44 μ PD70F3184 (V850E/IA3), PD70F3186 (V850E/IA4) only Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20) User’s Manual U16543EJ4V0UD...
Page 45 PD703186 (V850E/IA4) only Remarks 1. IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20) 2. n = 0, 1...
Page 46: Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits Type 5-AH Type 2 Pullup P-ch enable Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output N-ch disable Input enable Type 2-M Type 7 P-ch Comparator N-ch – (Threshold voltage) Type 3-C Type 7-C P-ch Comparator...
Page 47: Chapter 3 Cpu Function
CHAPTER 3 CPU FUNCTION The CPU of the V850E/IA3 and V850E/IA4 are based on RISC architecture and executes almost all the instructions in one clock cycle using 5-stage pipeline control. 3.1 Features Minimum instruction execution time: 15.6 ns (@ 64 MHz internal operation)
Page 48: Cpu Register Set
CHAPTER 3 CPU FUNCTION 3.2 CPU Register Set The registers of the V850E/IA3 and V850E/IA4 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers have a 32-bit width. For details, refer to V850E1 Architecture User’s Manual.
Page 49: Program Register Set
CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable.
Page 50: System Register Set
CHAPTER 3 CPU FUNCTION 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. To read/write these system registers, specify a system register number indicated below using the system register load/store instruction (LDSR or STSR instruction). Table 3-2.
Page 51 CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the contents of the program status word (PSW) are saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)).
Page 52 CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the program status word (PSW) are saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to FEPC, except for some instructions.
Page 53 CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of LDSR instruction execution.
Page 54 CHAPTER 3 CPU FUNCTION (2/2) Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set (to 1) only when the OV flag is set (to 1) during saturated operation. Operation result status Flag status Saturated...
Page 55 CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW.
Page 56: Operating Modes
3.3 Operating Modes 3.3.1 Operating modes The V850E/IA3 and V850E/IA4 have the following operating modes. Mode specification is carried out using the FLMD0 and FLMD1 pins. (1) Normal operation mode In this mode, execution branches to the reset entry address in the internal ROM and instruction processing is started when system reset is released.
Page 57: Address Space
CPU address space The CPU of the V850E/IA3 and V850E/IA4 has 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). Also, in instruction address addressing, a maximum of 64 MB of linear address space (program space) is supported.
Page 58: Image
CHAPTER 3 CPU FUNCTION 3.4.2 Image A 256 MB physical address space is seen as 16 images in the 4 GB CPU address space. In actuality, the same 256 MB physical address space is accessed regardless of the values of bits 31 to 28 of the CPU address. Figure 3-3 shows the image of the virtual addressing space.
Page 59: Wraparound Of Cpu Address Space
CHAPTER 3 CPU FUNCTION 3.4.3 Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to 26 as a result of a branch address calculation, the higher 6 bits ignore the carry or borrow.
Page 60: Memory Map
CHAPTER 3 CPU FUNCTION 3.4.4 Memory map The V850E/IA3 and V850E/IA4 reserve areas as shown in Figure 3-4. Figure 3-4. Memory Map μ PD70F3184 (V850E/IA3) μ μ PD703186 (V850E/IA4) PD703183 (V850E/IA3) μ μ PD70F3186 (V850E/IA4) PD703185 (V850E/IA4) x F F F F F F F H...
Page 61: Area
(1) Internal ROM area 1 MB of internal ROM area, addresses 00000H to FFFFFH, is reserved. μ μ PD703183 (V850E/IA3), PD703185 (V850E/IA4) 128 KB are provided at addresses 000000H to 01FFFFH as physical internal ROM. Figure 3-5. Internal ROM Area (128 KB)
Page 62 The 12 KB area of addresses FFFC000H to FFFEFFFH is reserved for the internal RAM area. μ μ PD703183 (V850E/IA3), PD703185 (V850E/IA4) The 6 KB area of addresses FFFD800H to FFFEFFFH is provided as physical internal RAM. Caution The following areas are access-prohibited.
Page 63 If the 6 KB internal RAM is selected and if addresses FFFC000H to FFFD7FFH are accessed, this register cannot be written. When it is read, the CPU reads an undefined value. 2. The IMS register is provided only in the flash memory versions; V850E/IA3 μ μ...
Page 64 I/O are all memory-mapped to the on-chip peripheral I/O area. Program fetches cannot be executed from this area. Cautions 1. In the V850E/IA3 and V850E/IA4, if a register is word accessed, halfword access is performed twice in the order of lower address, then higher address of the word area, disregarding the lower 2 bits of the address.
Page 65: Recommended Use Of Address Space
(2) Data space With the V850E/IA3 and V850E/IA4, a 256 MB physical address space is seen as 16 images in the 4 GB CPU address space. The highest bit (bit 25) of this 26-bit address is assigned as an address sign-extended to 32 bits.
Page 66 CHAPTER 3 CPU FUNCTION Figure 3-10. Recommended Memory Map Program space Data space F F F F F F F F H On-chip peripheral I/O F F F F F 0 0 0 H F F F F E F F F H Internal RAM F F F F C 0 0 0 H F F F E B F F F H...
Page 67: On-Chip Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.7 On-chip peripheral I/O registers (1/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset √ FFFFF004H Port DL register Undefined √ √ FFFFF004H Port DL register L PDLL Undefined √ √ FFFFF005H Port DL register H PDLH Undefined √...
Page 68 CHAPTER 3 CPU FUNCTION (2/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset √ FFFFF104H Interrupt mask register 2 IMR2 FFFFH √ √ FFFFF104H Interrupt mask register 2L IMR2L √ √ FFFFF105H Interrupt mask register 2H IMR2H √...
Page 69 CHAPTER 3 CPU FUNCTION (3/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset √ √ FFFFF158H Interrupt control register TP2CCIC1 √ √ FFFFF15AH Interrupt control register TP3OVIC √ √ FFFFF15CH Interrupt control register TP3CCIC0 √ √ FFFFF15EH Interrupt control register TP3CCIC1 √...
Page 70 CHAPTER 3 CPU FUNCTION (4/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset √ FFFFF21CH A/D0 conversion result register 6 ADA0CR6 Undefined √ FFFFF21DH A/D0 conversion result register 6H ADA0CR6H Undefined √ FFFFF21EH A/D0 conversion result register 7 ADA0CR7 Undefined √...
Page 71 CHAPTER 3 CPU FUNCTION (5/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset √ √ FFFFF260H Operational amplifier 0 control register 0 OP0CTL0 √ √ FFFFF261H Operational amplifier 0 control register 1 OP0CTL1 √ √ FFFFF268H Operational amplifier 1 control register 0 OP1CTL0 √...
Page 72 CHAPTER 3 CPU FUNCTION (6/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset √ √ FFFFF596H CC101 capture input select register CSL10 √ √ FFFFF598H Noise elimination time select register 10 NRC10 √ Note FFFFF5A0H Timer ENC11 TMENC11 0000H √...
Page 73 CHAPTER 3 CPU FUNCTION (7/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset √ √ Note FFFFF621H TMQ1 option register 2 TQ1OPT2 √ √ Note FFFFF622H TMQ1 I/O control register 3 TQ1IOC3 √ √ Note FFFFF623H TMQ1 option register 3 TQ1OPT3 √...
Page 74 UARTA1 control register 2 UA1CTL2 √ √ FFFFFA13H UARTA1 option control register 0 UA1OPT0 √ √ FFFFFA14H UARTA1 status register UA1STR √ FFFFFA16H UARTA1 receive data register UA1RX μ μ Note PD70F3184 (V850E/IA3) and PD70F3186 (V850E/IA4) only User’s Manual U16543EJ4V0UD...
Page 75 CHAPTER 3 CPU FUNCTION (9/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset √ FFFFFA17H UARTA1 transmit data register UA1TX √ √ FFFFFC00H External interrupt falling edge specification INTF0 register 0 √ √ FFFFFC20H External interrupt rising edge specification INTR0 register 0 √...
Page 76: Special Registers
Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850E/IA3 and V850E/IA4 have the following four special registers. • Power save control register (PSC) • Processor clock control register (PCC) •...
Page 77 CHAPTER 3 CPU FUNCTION (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Prepare data to be set to the special register in a general-purpose register. <2> Write the data prepared in <1> to the command register. <3>...
Page 78 CHAPTER 3 CPU FUNCTION (2) Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first write access to a special register is valid after data has been written in advance to the PRCMD register.
Page 79 CHAPTER 3 CPU FUNCTION (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. If this register is not written in the correct sequence including an access to the PRCMD register, data is not written to the intended register, a protection error occurs, and the PRERR flag is set.
Page 80: System Wait Control Register (Vswc)
Access to on-chip peripheral I/O registers of the V850E1 CPU core is basically made in 3 clocks; however, in the V850E/IA3 and V850E/IA4, a wait set by the VSWC register is required in addition to those 3 clocks. Set 13H (set wait for 4 clocks) to VSWC.
Page 81: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS Features 4.1.1 V850E/IA3 Input-only ports: 6 I/O ports: Input and output can be specified in 1-bit units. On-chip pull-up resistor can be connected in 1-bit units (ports 0, 1, 3, 4, and DL only) However, an on-chip pull-up resistor can only be connected when the pins are in input mode in the port mode, or when the pins function as input pins in the alternate-function mode.
Page 82: Port Configuration
4.2.1 V850E/IA3 The V850E/IA3 incorporates a total of 50 input/output ports (including 6 input-only ports) labeled ports 0, 1, 3, 4, 7, and DL. The port configuration is shown in Figure 4-1. There are two power supplies for the I/O buffer of a pin: AV and EV .
Page 83: V850E/Ia4
CHAPTER 4 PORT FUNCTIONS 4.2.2 V850E/IA4 The V850E/IA4 incorporates a total of 64 input/output ports (including 8 input-only ports) labeled ports 0 to 5, 7, and DL. The port configuration is shown in Figure 4-2. There are two power supplies for the I/O buffer of a pin: AV and EV .
Page 84: Port Configuration
CHAPTER 4 PORT FUNCTIONS Port Configuration Table 4-3. Port Configuration (V850E/IA3) Item Configuration Control registers Port n register (Pn: n = 0, 1, 3, 4, 7, DL) Port n mode register (PMn: n = 0, 1, 3, 4, DL) Port n mode control register (PMCn: n = 0, 1, 3, 4, 7)
Page 85 CHAPTER 4 PORT FUNCTIONS (1) Port n register (Pn) Data is input from or output to an external device by writing or reading the Pn register. The Pn register consists of a port latch that holds output data, and a circuit that reads the status of pins. Each bit of the Pn register corresponds to one pin of port n, and can be read or written in 1-bit units.
Page 86 CHAPTER 4 PORT FUNCTIONS (2) Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit units.
Page 87 CHAPTER 4 PORT FUNCTIONS (5) Port n function control expansion register (PFCEn) The PFCEn register specifies the alternate function of a port pin to be used if the pin has three or more alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units.
Page 88 CHAPTER 4 PORT FUNCTIONS (7) Port settings Set the ports as follows. Figure 4-3. Register Settings and Pin Functions Port mode Output mode "0" PMn register Input mode "1" Alternate function (when two alternate functions are available) "0" Alternate function 1 "0"...
Page 89: Port 0
0 AND 1) after noise is eliminated by a port (analog delay). In addition, a signal whose edge was detected is input to the interrupt controller (INTC) as INTPn (V850E/IA3: n = 0, 2 to 5, V850E/IA4: n = 0 to 5). Edge detection is performed by the high-impedance output controller and A/D converters 0 and 1.
Page 90 INTF07 Caution To control high-impedance output of the external interrupt function and motor output control function, set the PMC0a bit to 1 (V850E/IA3: a = 0, 2, or 4 to 7, V850E/IA4: a = 0 to 7). Remark n = 0, 2, 3 (n = 0, 2 only in PMC0n bit) (V850E/IA3)
Page 91 Control of output data (in output mode) Output 0. Output 1 Note Valid only for the V850E/IA4. With the V850E/IA3, the read value of this register is undefined. Remark V850E/IA3: n = 0, 2 to 7 V850E/IA4: n = 0 to 7...
Page 92 INTP1 input/TOQ1OFF input PMC00 Specification of operating mode of P00 pin I/O port INTP0 input/TOQ0OFF input Notes 1. Valid only in the V850E/IA4. With the V850E/IA3, be sure to clear these bits to 0. 2. V850E/IA4 only User’s Manual U16543EJ4V0UD...
Page 93 Connect Notes 1. Valid only in the V850E/IA4. With the V850E/IA3, be sure to clear this bit to 0. 2. An on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or when the pins function as alternate-function pins.
Page 94 Noise elimination noise Note INTP7, INPT1 input Edge detection elimination Note TOQ0OFF, TOQ1OFF Note TOP2OFF, TOP3OFF ADTRG0, ADTRG1 input Note V850E/IA4 only Remark V850E/IA3: n = 0, 2 to 5, 7 V850E/IA4: n = 0 to 5, 7 User’s Manual U16543EJ4V0UD...
Page 95 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P06 Pin PU06 P-ch INTR INTR0 INTR06 INTF INTF0 INTF06 PMC0 PMC06 PM06 PORT P06/INTP6 Address Digital Noise elimination INTP6 input noise Edge detection elimination User’s Manual U16543EJ4V0UD...
Page 96: Port 1
• Output of clock stop detection signal from clock monitor Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20) User’s Manual U16543EJ4V0UD...
Page 97 CHAPTER 4 PORT FUNCTIONS (1) Registers (a) Port 1 register (P1) After reset: Undefined Address: FFFFF402H Control of output data (in output mode) Output 0. Output 1. Remark n = 0 to 7 (b) Port 1 mode register (PM1) After reset: FFH Address: FFFFF422H PM17 PM16...
Page 98 CHAPTER 4 PORT FUNCTIONS (c) Port 1 mode control register (PMC1) After reset: 00H Address: FFFFF442H PMC1 PMC17 PMC16 PMC15 PMC14 PMC13 PMC12 PMC11 PMC10 PMC17 Specification of operating mode of P17 pin I/O port TOP21 output/TIP21 input Specification of operating mode of P16 pin PMC16 I/O port TOQ00 output/TIP20 input...
Page 99 CHAPTER 4 PORT FUNCTIONS (d) Port 1 function control register (PFC1) After reset: 00H Address: FFFFF462H PFC1 PFC17 PFC16 PFC15 PFC14 PFC13 PFC12 PFC11 PFC10 Remark For the specification of alternate function, see 4.3.2 (1) (f) Setting of alternate function of port 1. (e) Port 1 function control function expansion register (PFCE1) After reset: 00H Address: FFFFF702H...
Page 100 CHAPTER 4 PORT FUNCTIONS (f) Setting of alternate function of port 1 PFC17 Specification of Alternate Function of P17 Pin TOP21 output TIP21 input PFC16 Specification of Alternate Function of P16 Pin TOQ00 output TIP20 input PFC15 Specification of Alternate Function of P15 Pin TOQ0B3 output TRGQ0 input PFC14...
Page 101 CHAPTER 4 PORT FUNCTIONS (g) Pull-up resistor option register 1 (PU1) After reset: 00H Address: FFFFFC42H PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 PU1n Control of on-chip pull-up resistor connection Do not connect Note Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or when the pins function as input pins in the alternate-function mode.
Page 102 CHAPTER 4 PORT FUNCTIONS (2) Block diagram Figure 4-6. Block Diagram of P10 to P12 Pins PU1n P-ch Note 1 Note 2 PFCE PFCE1 PFCE1n PFC1 PFC1n PMC1 PMC1n PM1n TOQ0T1, TOQ0B1, TOQ0T2 output TOQ01 to TOQ03 output P10/TOQ0T1/TIQ01/TOQ01 PORT P11/TOQ0B1/TIQ02/TOQ02 P12/TOQ0T2/TIQ03/TOQ03 Address...
Page 103 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P13 to P15 and P17 Pins PU1n P-ch Note 1 Note 2 PFC1 PFC1n PMC1 PMC1n PM1n TOQ0B2, TOQ0T3, TOQ0B3, TOP21 output P13/TOQ0B2/TIQ00 P14/TOQ0T3/EVTQ0 PORT P15/TOQ0B3/TRGQ0 P17/TOP21/TIP21 Address Digital noise TIQ00, EVTQ0, TRGQ0, TIP21 input elimination Notes 1.
Page 104 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P16 Pin PU16 P-ch PFC1 PFC16 PMC1 PMC16 PM16 TOQ00 output PORT P16/TOQ00/TIP20 Address Digital noise TIP20 input elimination User’s Manual U16543EJ4V0UD...
Page 105: Port 2 (V850E/Ia4 Only)
CHAPTER 4 PORT FUNCTIONS 4.3.3 Port 2 (V850E/IA4 only) Port 2 can be set to the input or output mode in 1-bit units. Port 2 has an alternate function as the following pins. Table 4-8. Alternate-Function Pins of Port 2 Note Port Pin No.
Page 106 CHAPTER 4 PORT FUNCTIONS (1) Registers (a) Port 2 register (P2) After reset: Undefined Address: FFFFF404H Control of output data (in output mode) Output 0. Output 1. Remark n = 0 to 7 (b) Port 2 mode register (PM2) After reset: FFH Address: FFFFF424H PM27 PM26...
Page 107 CHAPTER 4 PORT FUNCTIONS (c) Port 2 mode control register (PMC2) After reset: 00H Address: FFFFF444H PMC2 PMC27 PMC26 PMC25 PMC24 PMC23 PMC22 PMC21 PMC20 PMC27 Specification of operating mode of P27 pin I/O port TOP31 output Specification of operating mode of P26 pin PMC26 I/O port TOQ10 output...
Page 108 CHAPTER 4 PORT FUNCTIONS (d) Pull-up resistor option register 2 (PU2) After reset: 00H Address: FFFFFC44H PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 PU2n Control of on-chip pull-up resistor connection Do not connect Note Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode. Moreover, an on-chip pull-up resistor can only be connected to the TOQ1T1 to TOQ1T3, TOQ1B1 to TOQ1B3, and TOP31 pins, these pins are output pins in the alternate-function mode, when these pins go into a high-impedance state due to the TOQ1OFF or TOP3OFF pin, or software processing.
Page 109 CHAPTER 4 PORT FUNCTIONS (2) Block diagram Figure 4-9. Block Diagram of P20 to P25, and P27 Pins PU2n P-ch Note 1 Note 2 PMC2 PMC2n PM2n TOQ1T1 to TOQ1T3, TOQ1B1 to TOQ1B3, TOP31 output P20/TOQ1T1 P21/TOQ1B1 P22/TOQ1T2 PORT P23/TOQ1B2 P24/TOQ1T3 P25/TOQ1B3 P27/TOP31...
Page 110 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P26 Pin PU26 P-ch PMC2 PMC26 PM26 TOQ10 output PORT P26/TOQ10 Address User’s Manual U16543EJ4V0UD...
Page 111: Port 3
TCLR10 Input Note Software pull-up function Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20) User’s Manual U16543EJ4V0UD...
Page 112 CHAPTER 4 PORT FUNCTIONS (1) Registers (a) Port 3 register (P3) After reset: Undefined Address: FFFFF406H Control of output data (in output mode) Output 0. Output 1. Remark n = 0 to 7 (b) Port 3 mode register (PM3) After reset: FFH Address: FFFFF426H PM37 PM36...
Page 113 CHAPTER 4 PORT FUNCTIONS (c) Port 3 mode control register (PMC3) After reset: 00H Address: FFFFF446H PMC3 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PMC37 Specification of operating mode of P37 pin I/O port TCLR10 input PMC36 Specification of operating mode of P36 pin I/O port TCUD10 input PMC35...
Page 114 CHAPTER 4 PORT FUNCTIONS (d) Port 3 function control register (PFC3) After reset: 00H Address: FFFFF466H PFC3 PFC35 PFC33 PFC32 PFC35 Specification of alternate function of P35 pin TIUD10 input TO10 output Specification of alternate function of P33 pin PFC33 SOB1 output TXDA1 output PFC32...
Page 115 CHAPTER 4 PORT FUNCTIONS (2) Block diagram Figure 4-11. Block Diagram of P30 Pin PU30 P-ch PMC3 PMC30 PM30 PORT P30/RXDA0 Address RXDA0 input User’s Manual U16543EJ4V0UD...
Page 116 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P31 Pin PU31 P-ch PMC3 PMC31 PM31 TXDA0 output PORT P31/TXDA0 Address User’s Manual U16543EJ4V0UD...
Page 117 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P32 Pin PU32 P-ch PFC3 PFC32 PMC3 PMC32 PM32 PORT P32/SIB1/RXDA1 Address SIB1 input RXDA1 input User’s Manual U16543EJ4V0UD...
Page 118 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P33 Pin PU33 P-ch PFC3 PFC33 PMC3 PMC33 PM33 SOB1 output TXDA1 output PORT P33/SOB1/TXDA1 Address User’s Manual U16543EJ4V0UD...
Page 119 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P34 Pin PU34 P-ch SCKB1 master mode PMC3 PMC34 PM34 SCKB1 output PORT P34/SCKB1 Address SCKB1 input User’s Manual U16543EJ4V0UD...
Page 120 CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of P35 Pin PU35 P-ch PFC3 PFC35 PMC3 PMC35 PM35 TO10 output PORT P35/TIUD10/TO10 Address Digital noise TIUD10 input elimination User’s Manual U16543EJ4V0UD...
Page 121 CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P36 and P37 Pins PU3n P-ch PMC3 PMC3n PM3n PORT P36/TCUD10 P37/TCLR10 Address Digital noise TCUD10, TCLR10 input elimination Remark n = 6, 7 User’s Manual U16543EJ4V0UD...
Page 122: Port 4
Note Software pull-up function Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20) (1) Registers (a) Port 4 register (P4)
Page 123 CHAPTER 4 PORT FUNCTIONS (b) Port 4 mode register (PM4) After reset: FFH Address: FFFFF428H PM44 PM43 PM42 PM41 PM40 PM4n Control of input/output mode (in port mode) Output mode Input mode Remark n = 0 to 4 (c) Port 4 mode control register (PMC4) After reset: 00H Address: FFFFF448H PMC4...
Page 124 CHAPTER 4 PORT FUNCTIONS (d) Port 4 function control register (PFC4) After reset: 00H Address: FFFFF468H PFC4 PFC44 PFC43 PFC44 Specification of alternate function of P44 pin TOP01 output TIP01 input Specification of alternate function of P43 pin PFC43 TOP00 output TIP00 input (e) Pull-up resistor option register 4 (PU4) After reset: 00H...
Page 125 CHAPTER 4 PORT FUNCTIONS (2) Block diagram Figure 4-18. Block Diagram of P40 Pin PU40 P-ch PMC4 PMC40 PM40 PORT P40/SIB0 Address SIB0 input User’s Manual U16543EJ4V0UD...
Page 126 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of P41 Pin PU41 P-ch PMC4 PMC41 PM41 SOB0 output PORT P41/SOB0 Address User’s Manual U16543EJ4V0UD...
Page 127 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of P42 Pin PU42 P-ch SCKB0 master mode PMC4 PMC42 PM42 SCKB0 output PORT P42/SCKB0 Address SCKB0 input User’s Manual U16543EJ4V0UD...
Page 128 CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of P43 and P44 Pins PU4n P-ch PFC4 PFC4n PMC4 PMC4n PM4n TOP00, TOP01 output P43/TOP00/TIP00 PORT P44/TOP01/TIP01 Address Digital noise TIP00, TIP01 input elimination Remark n = 3, 4 User’s Manual U16543EJ4V0UD...
Page 129: Port 5 (V850E/Ia4 Only)
CHAPTER 4 PORT FUNCTIONS 4.3.6 Port 5 (V850E/IA4 only) Port 5 can be set to the input or output mode in 1-bit units. Port 5 has an alternate function as the following pins. Table 4-11. Alternate-Function Pins of Port 5 Note 1 Port Pin No.
Page 130 CHAPTER 4 PORT FUNCTIONS (b) Port 5 mode register (PM5) After reset: FFH Address: FFFFF42AH PM52 PM51 PM50 PM5n Control of input/output mode (in port mode) Output mode Input mode Remark n = 0 to 2 (c) Port 5 mode control register (PMC5) After reset: 00H Address: FFFFF44AH PMC5...
Page 131 CHAPTER 4 PORT FUNCTIONS (e) Pull-up resistor option register 5 (PU5) After reset: 00H Address: FFFFFC4AH PU52 PU51 PU50 PU5n Control of on-chip pull-up resistor connection Do not connect Note Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or when the pins function as input pins in the alternate-function mode.
Page 132 CHAPTER 4 PORT FUNCTIONS (2) Block diagram Figure 4-22. Block Diagram of P50 Pin PU50 P-ch Note DRST pin level PFC5 PFC50 PMC5 PMC50 PM50 TO11 output PORT Note P50/DDI /TIUD11/TO11 Address Digital noise TIUD11 input elimination Note DRST pin level Note DDI input μ...
Page 133 CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of P51 and P52 Pins PU5n P-ch Note DRST pin level PMC5 PMC5n PM5n PORT Note P51/DCK /TCUD11 Note P52/DMS /TCLR11 Address Digital noise TCUD11, TCLR11 input elimination Note DRST pin level Note DCK, DMS input μ...
Page 134: Port 7
Notes 1. Software pull-up function 2. V850E/IA4 only Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20) User’s Manual U16543EJ4V0UD...
Page 135 P7 register is read. In this case, the read value of the P7n bit is fixed to the low level (V850E/IA3: n = 0 to 5, V850E/IA4: n = 0 to 7).
Page 136 P-ch ANI20 to ANI25 input P74/ANI24 N-ch Note ANI26, ANI27 input P75/ANI25 Note Note /ANI26 Note Note /ANI27 PMC7 PMC7n Address Note V850E/IA4 only Remark V850E/IA3: n = 0 to 5 V850E/IA4: n = 0 to 7 User’s Manual U16543EJ4V0UD...
Page 137: Port Dl
μ PD70F3184 (V850E/IA3), PD70F3186 (V850E/IA4) only Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20) User’s Manual U16543EJ4V0UD...
Page 138 CHAPTER 4 PORT FUNCTIONS (1) Registers (a) Port DL register (PDL) After reset: Undefined Address: PDL FFFFF004H PDLL FFFFF004H, PDLH FFFFF005H Note PDL (PDLH PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 (PDLL) PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 PDLn Control of output data (in output mode)
Page 139 CHAPTER 4 PORT FUNCTIONS (c) Pull-up resistor option register DL (PUDL) After reset: 0000H Address: PUDL FFFFFF44H PUDLL FFFFFF44H, PUDLH FFFFFF45H Note 1 PUDL (PUDLH PUDL15 PUDL14 PUDL13 PUDL12 PUDL11 PUDL10 PUDL9 PUDL8 (PUDLL) PUDL7 PUDL6 PUDL5 PUDL4 PUDL3 PUDL2 PUDL1 PUDL0 PUDLn...
Page 140 Notes 1. This pin is used in the flash programming mode and does not have to be manipulated by a port control register. For details, see CHAPTER 22 FLASH MEMORY. μ μ PD70F3184 (V850E/IA3), PD70F3186 (V850E/IA4) only User’s Manual U16543EJ4V0UD...
Page 141: Output Data And Port Read Value For Each Setting
CHAPTER 4 PORT FUNCTIONS Output Data and Port Read Value for Each Setting Table 4-14 shows the values used to select the alternate function of the respective pins, output data and port read values for each setting. In addition to the settings shown in Table 4-14, the setting of each peripheral function control register is required.
Page 142 Table 4-14. Output Data and Port Read Value for Each Setting (1/5) Output Data Remark Port Name Function PMCmn PFCEmn PFCmn PMmn Pmn Read Value Note 1 Output port None P00, P01 None Port latch Port latch − P02 to P07 Input port Pin level −...
Page 143 Table 4-14. Output Data and Port Read Value for Each Setting (2/5) Output Data Port Name Function PMCmn PFCEmn PFCmn PMmn Pmn Read Value Remark Note P20 to P27 Output port None None Port latch Port latch − Input port Pin level Note Note...
Page 144 Table 4-14. Output Data and Port Read Value for Each Setting (3/5) Output Data Port Name Function PMCmn PFCEmn PFCmn PMmn Pmn Read Value Remark × Output port None Port latch Port latch − Input port Pin level SOB1 None Alternate output 1 Port latch (serial output)
Page 145 Table 4-14. Output Data and Port Read Value for Each Setting (4/5) Output Data Port Name Function PMCmn PFCEmn PFCmn PMmn Pmn Read Value Remark Output port None None Port latch Port latch − Input port Pin level Output in master mode SCKB0 None None...
Page 146 P52/TCLR11 μ μ 3. The PDL5 pin is also used in flash programming mode ( PD70F3184 (V850E/IA3), PD70F3186 (V850E/IA4) only). This pin does not have to be manipulated by a port control register. For details, see CHAPTER 22 FLASH MEMORY.
Page 147: Port Register Settings When Alternate Function Is Used
CHAPTER 4 PORT FUNCTIONS Port Register Settings When Alternate Function Is Used The following shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each pin. User’s Manual U16543EJ4V0UD...
Page 148 Table 4-15. Using Port Pin as Alternate-Function Pin (1/5) Pin Name Alternate Pin Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn PFCEnx Bit of PFCnx Bit of Other Bit Register PFCEn Register PFCn Register (Register) Name −...
Page 149 Table 4-15. Using Port Pin as Alternate-Function Pin (2/5) Pin Name Alternate Pin Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn PFCEnx Bit of PFCnx Bit of Other Bit Register PFCEn Register PFCn Register (Register) Name −...
Page 150 Table 4-15. Using Port Pin as Alternate-Function Pin (3/5) Pin Name Alternate Pin Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn PFCEnx Bit of PFCnx Bit of Other Bit Register PFCEn Register PFCn Register (Register) Name −...
Page 151 Table 4-15. Using Port Pin as Alternate-Function Pin (4/5) Pin Name Alternate Pin Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn PFCEnx Bit of PFCnx Bit of Other Bit Register PFCEn Register PFCn Register (Register) Name −...
Page 152 μ 2. The PDL5 pin also functions as a pin to be set in the flash programming mode ( PD70F3184 (V850E/IA3), PD70F3186 (V850E/IA4) only). This pin does not need to be manipulated using the port control register. For details, see CHAPTER 22 FLASH MEMORY.
Page 153: Noise Eliminator
TIP21 TIP00 TIP01 μ Notes 1. PD70F3186 (V850E/IA4) only μ μ PD70F3184 (V850E/IA3), PD70F3186 (V850E/IA4) only μ μ μ PD703183 (V850E/IA3), PD703185 (V850E/IA4), PD703186 (V850E/IA4) only A maskable interrupt input other than INTP6 can be used as the release source of IDLE or STOP mode.
Page 154 CHAPTER 4 PORT FUNCTIONS The timing example of digital noise elimination at an input pin of INTP6 and the timer ENC. Figure 4-26. Example of Noise Elimination Timing <R> Noise elimination clock Sampling Input signal 5 times Sampling 5 times 2 clocks 2 clocks 3 clocks 3 clocks...
Page 155 CHAPTER 4 PORT FUNCTIONS (1) External interrupt noise elimination control register (INTPNRC) The INTPNRC register is used to select the sampling clock that is used to eliminate digital noise on the INTP6 pin. If the same level is not detected five times in a row, the signal is eliminated as noise. This register can be read or written in 8-bit or 1-bit units.
Page 156 CHAPTER 4 PORT FUNCTIONS (2) Noise elimination time select register 1n (NRC1n) (V850E/IA3: n = 0, V850E/IA4: n = 0, 1) The NRC1n register is used to select the sampling clock that is used to eliminate digital noise on the TIUD1n, TCUD1n, or TCLR1n pin.
Page 157: Cautions
Moreover, for the V850E/IA3, an on-chip pull-up resistor can be connected to the TOQ0T1 to TOQ0T3, TOQ0B1 to TOQ0B3, and TOP21 pins, these are output pins in the alternate-function mode, when these pins go into a high-impedance state due to the TOQ0OFF and TOP2OFF pins or software processing.
Page 158: Cautions On Bit Manipulation Instruction For Port N Register (Pn)
Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A bit manipulation instruction is executed in the following order in the V850E/IA3 and V850E/IA4. <1> The Pn register is read in 8-bit units.
Page 159: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR Overview The features of clock generator are as follows. Oscillator • In PLL mode: f = 4 to 8 MHz (f = 32 to 64 MHz) • In clock-through mode: f = 4 to 8 MHz (f = 4 to 8 MHz) Multiply (×8 fixed) function by PLL (Phase Locked Loop) •...
Page 160: Configuration
CHAPTER 5 CLOCK GENERATOR Configuration Figure 5-1. Clock Generator SELPLL PLLSIN IDLE mode CK1, CK0 bits IDLE Oscillator Prescaler 2 control HALT mode HALT CPU clock control Internal system Oscillator clock stop control STOP mode Oscillation stabilization time wait <R> to f /4,096 Oscillation stabilization...
Page 161 CHAPTER 5 CLOCK GENERATOR (1) Oscillator The main resonator oscillates the following frequencies (f • In PLL mode (×8 fixed): f = 4 to 8 MHz (f = 32 to 64 MHz) • In clock-through mode: f = 4 to 8 MHz (f = 4 to 8 MHz) (2) IDLE control All functions other than the oscillator, PLL, clock monitor operation, and CSIB in slave mode are stopped.
Page 162: Control Registers
CHAPTER 5 CLOCK GENERATOR Control Registers The clock generator is controlled by the following six registers. • PLL control register (PLLCTL) • Processor clock control register (PCC) • Power save control register (PSC) • Power save mode register (PSMR) • Oscillation stabilization time select register (OSTS) •...
Page 163 CHAPTER 5 CLOCK GENERATOR (2) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in a combination of specific sequences (see 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 03H.
Page 164 CHAPTER 5 CLOCK GENERATOR (3) Power save control register (PSC) The PSC register is a special register. Data can be written to this register only in a combination of specific sequences (see 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 165 CHAPTER 5 CLOCK GENERATOR (4) Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation in the software standby mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF820H <...
Page 166 CHAPTER 5 CLOCK GENERATOR (5) Oscillation stabilization time select register (OSTS) The OSTS register selects the oscillation stabilization time until the oscillation stabilizes after the STOP mode is released by interrupt request. This register can be read or written in 8-bit units. Reset sets this register to 04H.
Page 167 CHAPTER 5 CLOCK GENERATOR (6) Clock monitor mode register (CLM) The CLM register sets clock monitor operation mode. The CLM register is a special register. It can be written only in a combination of specific sequences (see 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units.
Page 168: Pll Function
) = 4 to 8 MHz 5.4.2 Setting PLL output frequency With the V850E/IA3 and V850E/IA4, the PLL output frequency range must be set as follows via signal input to the PLLSIN pin. Table 5-2. Setting PLL Output Frequency PLLSIN...
Page 169: Operation
CHAPTER 5 CLOCK GENERATOR Operation 5.5.1 Operation of each clock The following table shows the operation status of each clock. Table 5-3. Operation Status of Each Clock Power Save Mode Oscillator Internal Peripheral CPU Clock Watchdog System Clock Timer Note 1 Clock (f Clock <R>...
Page 170: Operation Timing
CHAPTER 5 CLOCK GENERATOR 5.5.2 Operation timing (1) Power on (power-on reset) Fixed oscillation stabilization time of clock from oscillator PLL lockup time 1.024 ms (8 MHz) 1.024 ms (8 MHz) RESET (input) <1> <3> OST counter 00H (initialization) PLL output clock <2>...
Page 171 CHAPTER 5 CLOCK GENERATOR (2) Reset input with power on Fixed oscillation stabilization PLL lockup time time of clock from oscillator 1.024 ms (8 MHz) 1.024 ms (8 MHz) Note <1> Reset <3> OST counter 00H (initialization) PLL output clock <2>...
Page 172 CHAPTER 5 CLOCK GENERATOR (3) When releasing STOP mode by interrupt request Fixed oscillation stabilization time of clock from oscillator PLL lockup time is is 1/2 of set value of 1/2 of set value of <3> OSTS register OSTS register <2>...
Page 173: Clock Monitor
CHAPTER 5 CLOCK GENERATOR Clock Monitor (1) Clock monitor function The clock monitor samples the clock generated by the oscillator, by using the internal oscillation clock. When it detects stop of oscillation, output of the timer for motor control goes into a high-impedance state (for details, see CHAPTER 10 MOTOR CONTROL FUNCTION).
Page 174: Chapter 6 16-Bit Timer/Event Counter P (Tmp)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Timer P (TMP) is a 16-bit timer/event counter. The V850E/IA3 and V850E/IA4 incorporate TMP0 to TMP3. Overview The TMPn of channels are outlined below (n = 0 to 3). Table 6-1. TMPn Overview...
Page 175: Configuration
3. V850E/IA4 only 4. Not provided for TMP1 Remark V850E/IA3: n = 0 to 3, m = 0, 2, k = 0, 2 V850E/IA4: n = 0 to 3, m = 0, 2, 3, k = 0, 2 User’s Manual U16543EJ4V0UD...
Page 176 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-1. TMP0 Block Diagram Internal bus TP0CNT INTTP0OV 16-bit counter Clear /128 TOP00 /256 TOP01 CCR0 buffer CCR1 register buffer INTTP0CC0 register INTTP0CC1 TIP00 TP0CCR0 TIP01 TP0CCR1 Internal bus Remark : Peripheral clock Figure 6-2.
Page 177 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-3. TMP2 Block Diagram Internal bus TP2CNT INTTP2OV 16-bit counter Clear /128 /256 TOP21 CCR0 buffer CCR1 register buffer INTTP2CC0 register INTTP2CC1 TIP20 TP2CCR0 TIP21 TP2CCR1 TOP2OFF Internal bus Remarks 1. f : Peripheral clock 2.
Page 178 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-4. TMP3 Block Diagram Internal bus TP3CNT INTTP3OV 16-bit counter Clear /128 /256 Note TOP31 CCR0 buffer CCR1 register INTTP3CC0 buffer register INTTP3CC1 TP3CCR0 TP3CCR1 Note TOP3OFF Internal bus Note V850E/IA4 only Remarks 1.
Page 179 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TPnCCR1 register is used as a compare register, the value written to the TPnCCR1 register is transferred to the CCR1 buffer register.
Page 180: Registers
After reset: 00H Address: TP0CTL0 FFFFF640H, TP1CTL0 FFFFF660H, TP2CTL0 FFFFF680H, TP3CTL0 FFFFF6A0H <7> TPnCTL0 TPnCE TPnCKS2 TPnCKS1 TPnCKS0 V850E/IA3 n = 0 to 3 TPnCE TMPn operation control m = 0, 2 Note TMPn operation disabled (TMPn reset asynchronously V850E/IA4 TMPn operation enabled.
Page 181 Notes 1. This bit can only be set in TMP0 and TMP1. Be sure to clear bit 7 of TMP2 and TMP3 to 0. For details of tuning operation mode, see CHAPTER 10 MOTOR CONTROL FUNCTION. 2. This bit can only be set in TMP0 and TMP2 in the V850E/IA3. Be sure to clear bit 6 of TMP1 and TMP3 to 0.
Page 182 This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Remark TMP1 and TMP3 do not have the TP1IOC0 and TP3IOC0 registers in the V850E/IA3. TMP1 does not have the TP1IOC0 register in the V850E/IA4. User’s Manual U16543EJ4V0UD...
Page 183 TP3IOC0 FFFFF6A2H <2> <0> Note 2 Note 2 TPmIOC0 TPmOL1 TPmOE1 TP0OL0 TP0OE0 V850E/IA3 m = 0, 2 Note 3 TPmOL1 TOPm1 pin output level setting V850E/IA4 TOPm1 pin starts output at high level. m = 0, 2, 3 TOPm1 pin starts output at low level.
Page 184 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) Cautions 2. Rewrite the TPmOL1, TPmOE1, TP0OL0, and TP0OE0 bits when the TPmCTL0.TPnCE bit = 0. (The same value can be written when the TPmCE bit = 1.) If rewriting was mistakenly performed, clear the TPmCE bit to 0 and then set the bits again.
Page 185 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (4) TMPk I/O control register 1 (TPkIOC1) The TPkIOC1 register is an 8-bit register that controls the valid edge for the capture trigger input signals (TIPk0, TIPk1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 186 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (5) TMPk I/O control register 2 (TPkIOC2) The TPkIOC2 register is an 8-bit register that controls the valid edge for the external event count input signal (TIPk0 pin) and external trigger input signal (TIPk0 pin). This register can be read or written in 8-bit or 1-bit units.
Page 187 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (6) TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register that sets the capture/compare operation and detects overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 188 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (7) TMPn capture/compare register 0 (TPnCCR0) The TP0CCR0 and TP2CCR0 registers are 16-bit registers that can be used as capture registers or compare registers depending on the mode. The TP1CCR0 and TP3CCR0 registers are 16-bit registers that can only be used as compare registers.
Page 189 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR0 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTPnCC0) is generated.
Page 190 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (8) TMPn capture/compare register 1 (TPnCCR1) The TP0CCR1 and TP2CCR1 registers are 16-bit registers that can be used as capture registers or compare registers depending on the mode. The TP1CCR1 and TP3CCR1 registers are 16-bit registers that can only be used as compare registers.
Page 191 (the TOP11 pin is not provided). The compare register is not cleared by the TPnCTL0.TPnCE bit = 0. Remark V850E/IA3: m = 0, 2 V850E/IA4: m = 0, 2, 3 (b) Function as capture register (TP0CCR1 and TP2CCR1 registers only)
Page 192 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (9) TMPn counter read buffer register (TPnCNT) The TPnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TPnCTL0.TPnCE bit = 1, the count value of the 16-bit counter can be read. This register is read-only, in 16-bit units.
Page 193: Timer Output Operations
High-level output High level immediately before counting, low level after counting is started Remark V850E/IA3: a = 0 or 1 when m = 0 a = 1 when m = 2 V850E/IA4: a = 0 or 1 when m = 0 a = 1 when m = 2 or 3 User’s Manual U16543EJ4V0UD...
Page 194: Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Operation The functions of TMPn that can be realized differ from one channel to another. The functions of each channel are shown below. Table 6-8. TMP0 Specifications in Each Mode Operation TP0CTL1.TP0EST Bit TIP00 Pin (External Capture/Compare Compare Register...
Page 195 Only a software trigger (set by the TP3CTL1.TP3EST bit) can be used. Remark TMP3 does not have timer input pins (TIP30, TIP31) and timer output pin (V850E/IA3: TOP30, TOP31, V850E/IA4: TOP30). The match interrupt request signals (INTTP3CC0, INTTP3CC1) of the 16-bit counter and the TP3CCR0 and TP3CCR1 registers are provided.
Page 196 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Counter basic operation This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation in each mode. Remark n = 0 to 3, k = 0, 2 <R>...
Page 197 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Anytime write and batch write The TPnCCR0 and TPnCCR1 registers in TMPn can be rewritten during timer operation (TPnCTL0.TPnCE bit = 1), but the write method (anytime write, batch write) of the CCR0 and CCR1 buffer registers differs depending on the mode.
Page 198 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-6. Timing of Anytime Write TPnCE bit = 1 FFFFH 16-bit counter 0000H TPnCCR0 register CCR0 buffer register 0000H TPnCCR1 register CCR1 buffer register 0000H INTTPnCC0 signal INTTPnCC1 signal Remarks 1. D : Setting values of TPnCCR0 register : Setting values of TPnCCR1 register 2.
Page 199 TPmCCR0 register. Remarks 1. The above flowchart illustrates an example of the operation in the PWM output mode. 2. V850E/IA3: m = 0, 2, a = 0, 1 V850E/IA4: m = 0, 2, 3, a = 0, 1...
Page 200 : Setting values of TPmCCR0 register Setting values of TPmCCR1 register 2. The above timing chart illustrates an example of the operation in the PWM output mode. 3. V850E/IA3: m = 0, 2 V850E/IA4: m = 0, 2, 3 User’s Manual U16543EJ4V0UD...
Page 201: Interval Timer Mode (Tpnmd2 To Tpnmd0 Bits = 000)
50%, which is inverted when the INTTPmCC1 signal is generated, can be output from the TOPm1 pin. The value of the TPnCCR0 and TPnCCR1 registers can be rewritten even while the timer is operating. Remark V850E/IA3: m = 0, 2 V850E/IA4: m = 0, 2, 3 Figure 6-9. Configuration of Interval Timer Clear...
Page 202 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOP00 pin is inverted. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
Page 203 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-11. Register Setting for Interval Timer Mode Operation (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Select count clock 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPaSYE TPmEST TPkEEE...
Page 204 2. V850E/IA3: n = 0 to 3, m = 0, 2, k = 0, 2, a = 0, 1 V850E/IA4: n = 0 to 3, m = 0, 2, 3, k = 0, 2, a = 0, 1...
Page 205 In this case, set the TPkCCR0 and TPkCCR1 registers to the same value. Remark V850E/IA3: n = 0 to 3, m = 0, 2, k = 0, 2 V850E/IA4: n = 0 to 3, m = 0, 2, 3, k = 0, 2...
Page 206 TPmIOC0 register. STOP Remark V850E/IA3: n = 0 to 3, m = 0, 2 V850E/IA4: n = 0 to 3, m = 0, 2, 3 (2) Interval timer mode operation timing (a) Operation if TPnCCR0 register is set to 0000H If the TPnCCR0 register is set to 0000H, the INTTPnCC0 signal is generated at each count clock, and the output of the TOP00 pin is inverted.
Page 207 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Operation if TPnCCR0 register is set to FFFFH If the TPnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTPnCC0 signal is generated and the output of the TOP00 pin is inverted.
Page 208 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Notes on rewriting TPnCCR0 register If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When an overflow may occur, stop counting and then change the set value. FFFFH 16-bit counter 0000H...
Page 209 TOP00 pin selection controller Match signal INTTPnCC0 signal CCR0 buffer register TPnCE bit TPnCCR0 register Remark V850E/IA3: n = 0 to 3, m = 0, 2 V850E/IA4: n = 0 to 3, m = 0, 2, 3 User’s Manual U16543EJ4V0UD...
Page 210 TPnCE bit TPnCCR0 register TOP00 pin output INTTPnCC0 signal TPnCCR1 register TOPm1 pin output INTTPnCC1 signal Remark V850E/IA3: n = 0 to 3, m = 0, 2 V850E/IA4: n = 0 to 3, m = 0, 2, 3 User’s Manual U16543EJ4V0UD...
Page 211 TPnCE bit TPnCCR0 register TOP00 pin output INTTPnCC0 signal TPnCCR1 register TOPm1 pin output INTTPnCC1 signal Remark V850E/IA3: n = 0 to 3, m = 0, 2 V850E/IA4: n = 0 to 3, m = 0, 2, 3 User’s Manual U16543EJ4V0UD...
Page 212 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) <R> (3) Operation by external event count input (TIPk0) (a) Operation To count the 16-bit counter at the valid edge of external event count input (TIPk0) in the interval timer mode, clear the 16-bit counter from FFFFH to 0000H at the valid edge of the first external event count input after the TPkCE bit is set from 0 to 1.
Page 213: External Event Count Mode (Tpkmd2 To Tpkmd0 Bits = 001)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.6.2 External event count mode (TPkMD2 to TPkMD0 bits = 001) This mode is valid only in TMP0 and TMP2. In the external event count mode, the valid edge of the external event count input (TIPk0) is counted when the TPkCTL0.TPkCE bit is set to 1, and an interrupt request signal (INTTPkCC0) is generated each time the number of <R>...
Page 214 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-17. Basic Timing in External Event Count Mode FFFFH 16-bit counter − 1 16-bit counter 0000 0001 0000H External event count input TPkCE bit (TIPk0 pin input) TPkCCR0 register TPkCCR0 register INTTPkCC0 signal INTTPkCC0 signal External External...
Page 215 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPkCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TPkCCR0 register is transferred to the CCR0 buffer register.
Page 216 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-18. Register Setting for Operation in External Event Count Mode (2/2) (f) TMPk capture/compare register 1 (TPkCCR1) The TPkCCR1 register is not used in the external event count mode. However, the set value of the TPkCCR1 register is transferred to the CCR1 buffer register.
Page 217 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) External event count mode operation flow Figure 6-19. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TPkCE bit TPkCCR0 register INTTPkCC0 signal <1> <2> <1> Count operation start flow START Initial setting of these registers Register initial setting...
Page 218 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, the TPkCCR0 and TPkCCR1 registers must not be cleared to 0000H. <R> 2. In the external event count mode, use of the timer output (TOP00, TOPk1) is disabled. If performing timer output (TOPk1) using external event count input (TIPk0), set the interval timer mode, and enable the count clock operation with the external event count input (TPkCTL1.TPkEEE bit = 1) (see 6.6.1 (3) Operation by external event count input (TIPk0)).
Page 219 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Notes on rewriting the TPkCCR0 register If the value of the TPkCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When the overflow may occur, stop counting once and then change the set value. FFFFH 16-bit counter 0000H...
Page 220 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Operation of TPkCCR1 register Figure 6-20. Configuration of TPkCCR1 Register TPkCCR1 register CCR1 buffer register Match signal INTTPkCC1 signal Clear TIPk0 pin Edge (external event 16-bit counter detector count input) Match signal INTTPkCC0 signal TPkCE bit CCR0 buffer register...
Page 221 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPkCCR1 register is greater than the set value of the TPkCCR0 register, the INTTPkCC1 signal is not generated because the count value of the 16-bit counter and the value of the TPkCCR1 register do not match.
Page 222: External Trigger Pulse Output Mode (Tpmmd2 To Tpmmd0 Bits = 010)
Caution In the external trigger pulse output mode, select the internal clock as the count clock (by clearing the TPkCTL1.TPkEEE bit to 0). Remark V850E/IA3: m = 0, 2, k = 0, 2 V850E/IA4: m = 0, 2, 3, k = 0, 2 User’s Manual U16543EJ4V0UD...
Page 223 The valid edge of an external trigger input (TIPk0) or setting the software trigger (TPmCTL1.TPmEST bit) to 1 is used as the trigger. Remark V850E/IA3: m = 0, 2, k = 0, 2, a = 0, 1 V850E/IA4: m = 0, 2, 3, k = 0, 2, a = 0, 1 User’s Manual U16543EJ4V0UD...
Page 224 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-25. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TMPm control register 0 (TPmCTL0) TPmCE TPmCKS2 TPmCKS1 TPmCKS0 TPmCTL0 <R> Select count clock 0: Stop counting 1: Enable counting (b) TMPm control register 1 (TPmCTL1) TP0SYE TPmEST...
Page 225 Remarks 1. TMPk I/O control register 1 (TPkIOC1) and TMPm option register 0 (TPmOPT0) are not used in the external trigger pulse output mode. 2. V850E/IA3: m = 0, 2, k = 0, 2 V850E/IA4: m = 0, 2, 3, k = 0, 2...
Page 226 TPmCCR1 register CCR1 buffer register INTTPmCC1 signal TOPm1 pin output <1> <2> <3> <4> <5> Remark V850E/IA3: m = 0, 2, k = 0, 2 V850E/IA4: m = 0, 2, 3, k = 0, 2 User’s Manual U16543EJ4V0UD...
Page 227 TPmCCRa register is transferred to the CCRa buffer register. Remark V850E/IA3: m = 0, 2, k = 0, 2, a = 0, 1 V850E/IA4: m = 0, 2, 3, k = 0, 2, a = 0, 1 User’s Manual U16543EJ4V0UD...
Page 228 INTTPmCC0 signal TOP00 pin output (software trigger) TPmCCR1 register CCR1 buffer register INTTPmCC1 signal TOPm1 pin output Remark V850E/IA3: m = 0, 2, k = 0, 2 V850E/IA4: m = 0, 2, 3, k = 0, 2 User’s Manual U16543EJ4V0UD...
Page 229 TPmCCRa register to the CCRa buffer register conflicts with writing the TPmCCRa register. Remark V850E/IA3: m = 0, 2, a = 0, 1 V850E/IA4: m = 0, 2, 3, a = 0, 1 User’s Manual U16543EJ4V0UD...
Page 230 Note INTTPmCC1 signal TOPm1 pin output Note Actually, the timing is delayed by one operating clock (f Remark V850E/IA3: m = 0, 2, k = 0, 2 V850E/IA4: m = 0, 2, 3, k = 0, 2 User’s Manual U16543EJ4V0UD...
Page 231 INTTPmCC1 signal <R> TOPm1 pin output Note Actually, the timing is delayed by one operating clock (f Remark V850E/IA3: m = 0, 2, k = 0, 2 V850E/IA4: m = 0, 2, 3, k = 0, 2 User’s Manual U16543EJ4V0UD...
Page 232 TOPm1 pin output Shortened Remark V850E/IA3: m = 0, 2, k = 0, 2 V850E/IA4: m = 0, 2, 3, k = 0, 2 If the trigger is detected immediately before the INTTPmCC1 signal is generated, the INTTPmCC1 signal is not generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the TOPm1 pin remains active.
Page 233 TOPm1 pin output Extended Remark V850E/IA3: m = 0, 2, k = 0, 2 V850E/IA4: m = 0, 2, 3, k = 0, 2 If the trigger is detected immediately before the INTTPmCC0 signal is generated, the INTTPmCC0 signal is not generated. The 16-bit counter is cleared to 0000H, the TOPm1 pin is asserted, and the counter continues counting.
Page 234 INTTPmCC1 signal Note Actually, the timing is delayed by one operating clock (f Remark V850E/IA3: m = 0, 2, V850E/IA4: m = 0, 2, 3 Usually, the INTTPmCC1 signal is generated in synchronization with the next count up, after the count value of the 16-bit counter matches the value of the TPmCCR1 register.
Page 235: One-Shot Pulse Output Mode (Tpmmd2 To Tpmmd0 Bits = 011)
Caution In the one-shot pulse output mode, select the internal clock as the count clock (by clearing the TPkCTL1.TPkEEE bit to 0). Remark V850E/IA3: m = 0, 2, k = 0, 2 V850E/IA4: m = 0, 2, 3, k = 0, 2 User’s Manual U16543EJ4V0UD...
Page 236 The valid edge of an external trigger input (TIPk0 pin) or setting the software trigger (TPmCTL1.TPmEST bit) to 1 is used as the trigger. Remark V850E/IA3: m = 0, 2, k = 0, 2 V850E/IA4: m = 0, 2, 3, k = 0, 2 User’s Manual U16543EJ4V0UD...
Page 237 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-29. Setting of Registers in One-Shot Pulse Output Mode (1/2) (a) TMPm control register 0 (TPmCTL0) TPmCE TPmCKS2 TPmCKS1TPmCKS0 TPmCTL0 Select count clock <R> 0: Stop counting 1: Enable counting (b) TMPm control register 1 (TPmCTL1) TP0SYE TPmEST TPkEEE...
Page 238 Remarks 1. TMPk I/O control register 1 (TPkIOC1) and TMPm option register 0 (TPmOPT0) are not used in the one-shot pulse output mode. 2. V850E/IA3: m = 0, 2, k = 0, 2 V850E/IA4: m = 0, 2, 3, k = 0, 2...
Page 239 INTTPmCC0 signal is recommended. Remark V850E/IA3: m = 0, 2, k = 0, 2, a = 0, 1 V850E/IA4: m = 0, 2, 3, k = 0, 2, a = 0, 1 User’s Manual U16543EJ4V0UD...
Page 240 Therefore, the counter may output a pulse with a delay period or active period different from that of the one-shot pulse that is originally expected. Remark V850E/IA3: m = 0, 2, k = 0, 2, a = 0, 1 V850E/IA4: m = 0, 2, 3, k = 0, 2, a = 0, 1 User’s Manual U16543EJ4V0UD...
Page 241 Note Actually, the timing is delayed by one operating clock (f Remark V850E/IA3: m = 0, 2 V850E/IA4: m = 0, 2, 3 Usually, the INTTPmCC1 signal is generated when the 16-bit counter counts up next time after its count value matches the value of the TPmCCR1 register.
Page 242: Pwm Output Mode (Tpmmd2 To Tpmmd0 Bits = 100)
Note Because the external event count input pin (TIP00) and timer output pin (TOP00) function alternately, two or more functions cannot be used at the same time. Remark V850E/IA3: m = 0, 2, k = 0, 2 V850E/IA4: m = 0, 2, 3, k = 0, 2 User’s Manual U16543EJ4V0UD...
Page 243 CCRa buffer register and the 16-bit counter is cleared to 0000H. Remark V850E/IA3: m = 0, 2, a = 0, 1 V850E/IA4: m = 0, 2, 3, a = 0, 1 User’s Manual U16543EJ4V0UD...
Page 244 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-33. Register Setting in PWM Output Mode (1/2) (a) TMPm control register 0 (TPmCTL0) TPmCE TPmCKS2 TPmCKS1 TPmCKS0 TPmCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPmCTL1.TPkEEE bit = 1. (b) TMPm control register 1 (TPmCTL1) TP0SYE TPmEST...
Page 245 Remarks 1. TMPk I/O control register 1 (TPkIOC1) and TMPk option register 0 (TPkOPT0) are not used in the PWM output mode. 2. V850E/IA3: m = 0, 2, k = 0, 2 V850E/IA4: m = 0, 2, 3, k = 0, 2...
Page 246 TOP00 pin output TPmCCR1 register CCR1 buffer register INTTPmCC1 signal TOPm1 pin output <1> <2> <3> <4> <5> Remark V850E/IA3: m = 0, 2, k = 0, 2 V850E/IA4: m = 0, 2, 3, k = 0, 2 User’s Manual U16543EJ4V0UD...
Page 247 TPmCCRa register is transferred to the CCRa buffer register. Remark V850E/IA3: m = 0, 2, k = 0, 2, a = 0, 1 V850E/IA4: m = 0, 2, 3, k = 0, 2, a = 0, 1 User’s Manual U16543EJ4V0UD...
Page 248 TPmCCRa register to the CCRa buffer register conflicts with writing the TPmCCRa register. Remark V850E/IA3: m = 0, 2, a = 0, 1 V850E/IA4: m = 0, 2, 3, a = 0, 1 User’s Manual U16543EJ4V0UD...
Page 249 Note Actually, the timing is delayed by one operating clock (f Remark V850E/IA3: m = 0, 2 V850E/IA4: m = 0, 2, 3 To output a 100% waveform, set a value of (set value of TPmCCR0 register + 1) to the TPmCCR1 register.
Page 250 INTTPmCC1 signal Note Actually, the timing is delayed by one operating clock (f Remark V850E/IA3: m = 0, 2 V850E/IA4: m = 0, 2, 3 Usually, the INTTPmCC1 signal is generated in synchronization with the next counting up after the count value of the 16-bit counter matches the value of the TPmCCR1 register.
Page 251: Free-Running Timer Mode (Tpnmd2 To Tpnmd0 Bits = 101)
Remark V850E/IA3: n = 0 to 3, m = 0, 2, k = 0, 2 V850E/IA4: n = 0 to 3, m = 0, 2, 3, k = 0, 2...
Page 252 CLR instruction CLR instruction CLR instruction CLR instruction Remark V850E/IA3: n = 0 to 3, m = 0, 2, a = 0, 1 V850E/IA4: n = 0 to 3, m = 0, 2, 3, a = 0, 1 User’s Manual U16543EJ4V0UD...
Page 253 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) • Capture operation When the TPkCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPka pin is detected, the count value of the 16-bit counter is stored in the TPkCCRa register, and a capture interrupt request signal (INTTPkCCa) is generated.
Page 254 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-38. Register Setting in Free-Running Timer Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPkCTL1.TPkEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TP0SYE TPmEST...
Page 255 TOP00 and TOPm1 pins are inverted. Remark V850E/IA3: n = 0 to 3, m = 0, 2, k = 0, 2, a = 0, 1 V850E/IA4: n = 0 to 3, m = 0, 2, 3, k = 0, 2, a = 0, 1...
Page 256 Cleared to 0 by Cleared to 0 by <3> CLR instruction CLR instruction CLR instruction <2> <2> <2> Remark V850E/IA3: n = 0 to 3, m = 0, 2 V850E/IA4: n = 0 to 3, m = 0, 2, 3 User’s Manual U16543EJ4V0UD...
Page 257 TPnCE bit = 0 clearing TPnCE bit to 0. STOP Remark V850E/IA3: n = 0 to 3, m = 0, 2, k = 0, 2 V850E/IA4: n = 0 to 3, m = 0, 2, 3, k = 0, 2 User’s Manual U16543EJ4V0UD...
Page 258 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) When using capture/compare register as capture register Figure 6-40. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TPkCE bit TIPk0 pin input TPkCCR0 register 0000 0000 INTTPkCC0 signal TIPk1 pin input 0000...
Page 259 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-40. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TPkCTL0 register is performed before setting the (TPkCKS0 to TPkCKS2 bits) TPkCE bit to 1.
Page 260 (If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the register.) Remark V850E/IA3: n = 0 to 3, m = 0, 2, a = 0, 1 V850E/IA4: n = 0 to 3, m = 0, 2, 3, a = 0, 1 User’s Manual U16543EJ4V0UD...
Page 261 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TPkCCRa register used as a capture register, software processing is necessary for reading the capture register each time the INTTPkCCa signal has been detected and for calculating an interval.
Page 262 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two capture registers are used FFFFH 16-bit counter...
Page 263 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TPkCE bit INTTPkOV signal TPkOVF bit Note TPkOVF0 flag TIPk0 pin input TPkCCR0 register Note TPkOVF1 flag TIPk1 pin input TPkCCR1 register <1>...
Page 264 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TPkCE bit INTTPkOV signal TPkOVF bit Note TPkOVF0 flag TIPk0 pin input TPkCCR0 register Note TPkOVF1 flag TIPk1 pin input TPkCCR1 register <1>...
Page 265 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
Page 266 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TPkCE bit TIPka pin input TPkCCRa register INTTPkOV signal TPkOVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1>...
Page 267 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction after reading the TPnOVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TPnOPT0 register after reading the TPnOVF bit when it is 1.
Page 268: Pulse Width Measurement Mode (Tpkmd2 To Tpkmd0 Bits = 110)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.6.7 Pulse width measurement mode (TPkMD2 to TPkMD0 bits = 110) The mode is valid only in TMP0 and TMP2. In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TPkCTL0.TPkCE bit is set to 1.
Page 269 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-42. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPkCE bit TIPka pin input 0000H TPkCCRa register INTTPkCCa signal INTTPkOV signal Cleared to 0 by TPkOVF bit CLR instruction Remark k = 0, 2 a = 0, 1...
Page 270 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-43. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMPk control register 0 (TPkCTL0) TPkCE TPkCKS2 TPkCKS1 TPkCKS0 TPkCTL0 <R> Select count clock 0: Stop counting 1: Enable counting (b) TMPk control register 1 (TPkCTL1) TP0SYE TPkEST TPkEEE...
Page 271 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-43. Register Setting in Pulse Width Measurement Mode (2/2) (d) TMPk option register 0 (TPkOPT0) TPkCCS1 TPkCCS0 TPkOVF TPkOPT0 Overflow flag (e) TMPk counter read buffer register (TPkCNT) The value of the 16-bit counter can be read by reading the TPkCNT register. (f) TMPk capture/compare registers 0 and 1 (TPkCCR0 and TPkCCR1) These registers store the count value of the 16-bit counter when the valid edge input to the TIPk0 and TIPk1 pins is detected.
Page 272 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in pulse width measurement mode Figure 6-44. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPkCE bit TIPk0 pin input 0000H 0000H TPkCCR0 register INTTPkCC0 signal <1>...
Page 273 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPkOVF bit to 0 with the CLR instruction after reading the TPkOVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TPkOPT0 register after reading the TPkOVF bit when it is 1.
Page 274: Chapter 7 16-Bit Timer/Event Counter Q (Tmq)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Timer Q (TMQ) is a 16-bit timer/event counter. The V850E/IA3 and V850E/IA4 incorporate TMQ1 and TMQ0. Overview The TMQn channels are outlined below (n = 0, 1). Table 7-1. TMQn Overview Item TMQ0...
Page 275: Functions
√ Free-running timer √ × Pulse width measurement Notes 1. This is connected to TMQOPn. For details, see CHAPTER 10 MOTOR CONTROL FUNCTION. 2. V850E/IA3: × V850E/IA4: √ Configuration TMQn includes the following hardware. Table 7-3. TMQn Configuration Item Configuration 16-bit counter ×...
Page 276 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-1. TMQ0 Block Diagram Internal bus TQ0CNT /128 INTTQ0OV 16-bit counter /256 Clear EVTQ0 TOQ00 TOQ01 TRGQ0 TOQ02 TOQ03 CCR0 buffer CCR1 register INTTQ0CC0 buffer CCR2 register buffer INTTQ0CC1 TIQ00 TQ0CCR0 CCR3 register buffer INTTQ0CC2...
Page 277 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-2. TMQ1 Block Diagram Internal bus TQ1CNT INTTQ1OV 16-bit counter Clear Note TOQ10 /128 /256 CCR0 buffer CCR1 register buffer CCR2 register buffer CCR3 register INTTQ1CC0 buffer TQ1CCR0 INTTQ1CC1 register INTTQ1CC2 TQ1CCR1 TQ1CCR2 INTTQ1CC3 TQ1CCR3...
Page 278 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TQnCCR1 register is used as a compare register, the value written to the TQnCCR1 register is transferred to the CCR1 buffer register.
Page 279: Registers
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Registers (1) TMQn control register 0 (TQnCTL0) The TQnCTL0 register is an 8-bit register that controls the TMQn operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TQnCTL0 register by software.
Page 280 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) After reset: 00H Address: TQ0CTL1 FFFFF5C1H, TQ1CTL1 FFFFF601H Note 1 Note 1 TQnCTL1 TQ0EST TQ0EEE TQnMD2 TQnMD1 TQnMD0 (n = 0, 1) Note 1 TQ0EST Software trigger control − Generate a valid signal for external trigger input. •...
Page 281 TQnIOC0 TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQnOL0 TQnOE0 V850E/IA3 n = 0 Note 3 TQnOLm Output level setting of TOQnm and TOQnTb pins b = 1 to 3 (TMQ0: m = 0 to 3, TMQ1: m = 0) V850E/IA4 TOQnm and TOQnTb pins start output at high level.
Page 282 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2/2) Cautions 2. Rewrite the TQnOLm and TQnOEm bits when the TQnCTL0.TQnCE bit = 0. (The same value can be written when the TQnCE bit = 1.) If rewriting was mistakenly performed, clear (0) the TQnCE bit and then set the bits again.
Page 283 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (4) TMQ0 I/O control register 1 (TQ0IOC1) The TQ0IOC1 register is an 8-bit register that controls the valid edge for the capture trigger input signals (TIQ00 to TIQ03 pins). This register can be read or written in 8-bit or 1-bit units. Rest sets this register to 00H.
Page 284 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (5) TMQ0 I/O control register 2 (TQ0IOC2) The TQ0IOC2 register is an 8-bit register that controls the valid edge for the external event count input signal (EVTQ0 pin) and external trigger input signal (TRGQ0 pin). This register can be read or written in 8-bit or 1-bit units.
Page 285 Notes 1. Valid only in TMQ0. Be sure to clear bits 7 to 4 in TMQ1 to 0. 2. In the V850E/IA3, be sure to clear bits 2 and 1 of TMQ1 to 0. For details of the TQnCMS and TQnCUF bits, see CHAPTER 10 MOTOR CONTROL FUNCTION.
Page 286 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (7) TMQn capture/compare register 0 (TQnCCR0) The TQ0CCR0 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. The TQ1CCR0 register is a 16-bit register that can only be used as a compare register.
Page 287 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQnCCR0 register can be rewritten even when the TQnCTL0.TQnCE bit = 1. The set value of the TQnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTQnCC0) is generated.
Page 288 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (8) TMQn capture/compare register 1 (TQnCCR1) The TQ0CCR1 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. The TQ1CCR1 register is a 16-bit register that can only be used as a compare register.
Page 289 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQnCCR1 register can be rewritten even when the TQnCTL0.TQnCE bit = 1. The set value of the TQnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTQnCC1) is generated.
Page 290 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (9) TMQn capture/compare register 2 (TQnCCR2) The TQ0CCR2 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. The TQ1CCR2 register is a 16-bit register that can only be used as a compare register.
Page 291 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQnCCR2 register can be rewritten even when the TQnCTL0.TQnCE bit = 1. The set value of the TQnCCR2 register is transferred to the CCR2 buffer register. When the value of the 16-bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTQnCC2) is generated.
Page 292 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (10) TMQn capture/compare register 3 (TQnCCR3) The TQ0CCR3 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. The TQ1CCR3 register is a 16-bit register that can only be used as a compare register.
Page 293 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQnCCR3 register can be rewritten even when the TQnCTL0.TQnCE bit = 1. The set value of the TQnCCR3 register is transferred to the CCR3 buffer register. When the value of the 16-bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTQnCC3) is generated.
Page 294 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (11) TMQn counter read buffer register (TQnCNT) The TQnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TQnCTL0.TQnCE bit = 1, the count value of the 16-bit counter can be read. This register is read-only, in 16-bit units.
Page 295: Timer Output Operations
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Timer Output Operations The following table shows the operations and output levels of the TOQ00 to TOQ03 and TOQ10 pins (the TOQ10 pin is provided only in the V850E/IA4). Table 7-8. Timer Output Control in Each Mode Note 1 Operation Mode TOQn0 Pin...
Page 296: Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Operation The functions that can be realized differ between TMQ0 and TMQ1. The functions of each channel are shown below. Table 7-10. TMQ0 Specifications in Each Mode Operation TQ0CTL1.TQ0EST Bit TRGQ0 Pin Capture/Compare Compare Register (Software Trigger Bit) (External Trigger Input)
Page 297 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Counter basic operation This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation in each mode. Remark n = 0, 1 a = 0 to 3 <R>...
Page 298 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (e) Interrupt operation TMQn generates the following five interrupt request signals. • INTTQnCC0 interrupt: This signal functions as a match interrupt request signal of the CCR0 buffer register and as a capture interrupt request signal to the TQnCCR0 register. •...
Page 299 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Anytime write and batch write The TQnCCR0 to TQnCCR3 registers can be rewritten in the TMQn during timer operation (TQnCTL0.TQnCE bit = 1), but the write method (anytime write, batch write) of the CCR0 to CCR3 buffer registers differs depending on the mode.
Page 300 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-4. Timing of Anytime Write TQnCE bit = 1 FFFFH 16-bit counter 0000H TQnCCR0 register CCR0 buffer 0000H register INTTQnCC0 signal TQnCCR1 register CCR1 buffer 0000H register INTTQnCC1 signal TQnCCR2 register CCR2 buffer 0000H register INTTQnCC2...
Page 301 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Batch write In this mode, data is transferred all at once from the TQ0CCR0 to TQ0CCR3 registers to the CCR0 to CCR3 buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counter.
Page 302 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-5. Flowchart of Basic Operation for Batch Write START Initial settings • Set values to TQ0CCRa register • Timer operation enable (TQ0CE bit = 1) → Transfer of values of TQ0CCRa register to CCRa buffer register TQ0CCRy register rewrite Batch write enable...
Page 303 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-6. Timing of Batch Write TQ0CE bit = 1 FFFFH 16-bit counter 0000H TQ0CCR0 register CCR0 buffer 0000H register Note 1 Note 1 Same value write TQ0CCR1 Note 2 Note 3 register CCR1 buffer 0000H register...
Page 304: Interval Timer Mode (Tqnmd2 To Tqnmd0 = 000)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.6.1 Interval timer mode (TQnMD2 to TQnMD0 = 000) In the interval timer mode, an interrupt request signal (INTTQnCC0) is generated at the interval set by the TQnCCR0 register if the TQnCTL0.TQnCE bit is set to 1. A PWM waveform with a duty factor of 50% whose half cycle is equal to the interval can be output from the TOQn0 pin (the TOQ10 pin is provided in the V850E/IA4 only).
Page 305 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization Note with the count clock, and the counter starts counting. At this time, the output of the TOQn0 pin is inverted.
Page 306 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-9. Register Setting for Interval Timer Mode Operation (2/3) (c) TMQn I/O control register 0 (TQnIOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQnOL0 TQnOE0 TQnIOC0 0: Disable TOQn0 pin output 1: Enable TOQn0 pin output Setting of TOQn0 pin output level before count operation 0: Low level...
Page 307 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-9. Register Setting for Interval Timer Mode Operation (3/3) (g) TMQn capture/compare registers 1 to 3 (TQnCCR1 to TQnCCR3) The TQnCCR1 to TQnCCR3 registers are not used in the interval timer mode. However, the set values of the TQnCCR1 to TQnCCR3 registers are transferred to the CCR1 to CCR3 buffer registers.
Page 308 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Interval timer mode operation flow Figure 7-10. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TQnCE bit TQnCCR0 register Note TOQn0 pin output INTTQnCC0 signal <1> <2> Note The TOQ10 pin is provided only in the V850E/IA4. <1>...
Page 309 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Interval timer mode operation timing (a) Operation if TQnCCR0 register is set to 0000H If the TQnCCR0 register is set to 0000H, the INTTQnCC0 signal is generated at each count clock, and the output of the TOQn0 pin is inverted (the TOQ10 pin is provided only in the V850E/IA4).
Page 310 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Operation if TQnCCR0 register is set to FFFFH If the TQnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTQnCC0 signal is generated and the output of the TOQn0 pin is inverted (the TOQ10 pin is provided only in the V850E/IA4).
Page 311 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Notes on rewriting TQnCCR0 register If the value of the TQnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When the overflow may occur, stop counting once and then change the set value. FFFFH 16-bit counter 0000H...
Page 312 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Operation of TQnCCR1 to TQnCCR3 registers Figure 7-11. Configuration of TQnCCR1 to TQnCCR3 Registers TQnCCR1 register CCR1 buffer Output TOQ01 pin register controller Match signal INTTQnCC1 signal TQnCCR2 register Output CCR2 buffer TOQ02 pin controller register...
Page 313 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) <R> When the TQnCCRb register is set to the same value as that of the TQnCCR0 register, the INTTQnCCb signal is generated at the same timing as the INTTQnCC0 signal is generated, and the TOQ0b pin output is inverted.
Page 314 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQnCCRb register is greater than the set value of the TQnCCR0 register, the count value of the 16-bit counter does not match the value of the TQnCCRb register. Consequently, the INTTQnCCb signal is not generated, nor is the output of the TOQ0b pin changed.
Page 315 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) <R> (3) Operation by external event count input (EVTQ0) (a) Operation To count the 16-bit counter at the valid edge of external event count input (EVTQ0) in the interval timer mode, clear the 16-bit counter from FFFFH to 0000H at the valid edge of the first external event count input after the TQ0CE bit is set from 0 to 1.
Page 316: External Event Count Mode (Tq0Md2 To Tq0Md0 Bits = 001)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.6.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) This mode is valid only in TMQ0. In the external event count mode, the valid edge of the external event count input (EVTQ0) is counted when the TQ0CTL0.TQ0CE bit is set to 1, and an interrupt request signal (INTTQ0CC0) is generated each time the specified number of edges set by the TQ0CCR0 register have been counted.
Page 317 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-15. Basic Timing in External Event Count Mode FFFFH 16-bit counter 16-bit counter 0000 0001 0000H External event count input TQ0CE bit (EVTQ0 pin input) TQ0CCR0 register TQ0CCR0 register INTTQ0CC0 signal INTTQ0CC0 signal External External External...
Page 318 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TQ0CCR0 register is transferred to the CCR0 buffer register.
Page 319 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-16. Register Setting for Operation in External Event Count Mode (2/2) (f) TMQ0 capture/compare registers 1 to 3 (TQ0CCR1 to TQ0CCR3) The TQ0CCR1 to TQ0CCR3 registers are not used in the external event count mode. However, the set values of the TQ0CCR1 to TQ0CCR3 registers are transferred to the CCR1 to CCR3 buffer registers.
Page 320 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) External event count mode operation flow Figure 7-17. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register INTTQ0CC0 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers...
Page 321 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, the TQ0CCR0 to TQ0CCR3 registers must not be cleared to 0000H. <R> 2. In the external event count mode, use of the timer output (TOQ00 to TOQ03) is disabled. If using timer output (TOQ00 to TOQ03) with external event count input (EVTQ0), set the interval timer mode, and enable the count clock operation with the external event count input (TQ0CTL1.TQ0EEE bit = 1) (see 7.6.1 (3) Operation by external event count input...
Page 322 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Notes on rewriting the TQ0CCR0 register If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. When the overflow may occur, stop counting once and then change the set value. FFFFH 16-bit counter 0000H...
Page 323 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Operation of TQ0CCR1 to TQ0CCR3 registers Figure 7-18. Configuration of TQ0CCR1 to TQ0CCR3 Registers TQ0CCR1 register CCR1 buffer register Match signal INTTQ0CC1 signal TQ0CCR2 register CCR2 buffer register Match signal INTTQ0CC2 signal TQ0CCR3 register CCR3 buffer...
Page 324 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRb register is smaller than the set value of the TQ0CCR0 register, the INTTQ0CCb signal is generated once per cycle. ≥ D Figure 7-19. Timing Chart When D FFFFH 16-bit counter 0000H...
Page 325 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRb register is greater than the set value of the TQ0CCR0 register, the INTTQ0CCb signal is not generated because the count value of the 16-bit counter and the value of the TQ0CCRb register do not match.
Page 326: External Trigger Pulse Output Mode (Tq0Md2 To Tq0Md0 Bits = 010)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.6.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) This mode is valid only in TMQ0. In the external trigger pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set to 1.
Page 327 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-22. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TQ0CE External trigger input (TRGQ0 pin input) TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output <R> TQ0CCR1 register INTTQ0CC1 signal TOQ01 pin output Active level...
Page 328 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 16-bit timer/event counter Q waits for a trigger when the TQ0CE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOQ0b pin.
Page 329 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-23. Setting of Registers in External Trigger Pulse Output Mode (2/3) (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE TQ0MD2 TQ0MD1 TQ0MD0 TQ0CTL1 0, 1, 0: External trigger pulse output mode 0: Operate on count clock selected by TQ0CKS0 to TQ0CKS2 bits 1: Count with external...
Page 330 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-23. Setting of Registers in External Trigger Pulse Output Mode (3/3) (d) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 TQ0IOC2 Select valid edge of external trigger input (TRGQ0 pin) Select valid edge of external event count input (EVTQ0 pin) (e) TMQ0 counter read buffer register (TQ0CNT)
Page 331 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in external trigger pulse output mode Figure 7-24. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TQ0CE bit External trigger input (TRGQ0 pin input) TQ0CCR0 register CCR0 buffer register INTTQ0CC0 signal...
Page 332 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-24. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <4> TQ0CCR1 to TQ0CCR3 register setting change flow Writing of the TQ0CCR1 START Setting of TQ0CCR2, register must be performed TQ0CCR3 registers when the set duty factor is only...
Page 333 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQ0CCR1 register last. Rewrite the TQ0CCRb register after writing the TQ0CCR1 register after the INTTQ0CC0 signal is detected. Remark b = 1 to 3 FFFFH...
Page 334 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) In order to transfer data from the TQ0CCRa register to the CCRa buffer register, the TQ0CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TQ0CCR0 register, set the active level width to the TQ0CCR2 and TQ0CCR3 registers, and then set an active level to the TQ0CCR1 register.
Page 335 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) 0%/100% output of PWM waveform <R> To output a 0% waveform, set the TQ0CCRb register to 0000H. The 16-bit counter is cleared to 0000H and the INTTQ0CC0 and INTTQ0CCb signals are generated at the next timing after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register.
Page 336 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) To output a 100% waveform, set a value of (set value of TQ0CCR0 register + 1) to the TQ0CCRb register. If the set value of the TQ0CCR0 register is FFFFH, 100% output cannot be produced. Count clock −...
Page 337 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Conflict between trigger detection and match with CCRb buffer register If the trigger is detected immediately after the INTTQ0CCb signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOQ0b pin is asserted, and the counter continues counting.
Page 338 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTQ0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOQ0b pin is extended by time from generation of the INTTQ0CC0 signal to trigger detection.
Page 339 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (e) Generation timing of compare match interrupt request signal (INTTQ0CCb) The timing of generation of the INTTQ0CCb signal in the external trigger pulse output mode differs from the timing of INTTQ0CCb signals in other modes; the INTTQ0CCb signal is generated when the count value of the 16-bit counter matches the value of the CCRb buffer register.
Page 340: One-Shot Pulse Output Mode (Tq0Md2 To Tq0Md0 Bits = 011)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.6.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011) This mode is valid only in TMQ0. In the one-shot pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set to 1.
Page 341 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-26. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TQ0CE bit External trigger input (TRGQ0 pin input) TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register INTTQ0CC1 signal TOQ01 pin output Delay Active Delay...
Page 342 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, 16-bit timer/event counter Q waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOQ0b pin. After the one-shot pulse is output, the 16-bit counter is cleared to 0000H, stops counting, and waits for a trigger.
Page 343 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-27. Register Setting in One-Shot Pulse Output Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0IOC0 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of TOQ00 pin output level in external trigger waiting state 0: Low level...
Page 344 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-27. Register Setting in One-Shot Pulse Output Mode (3/3) (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) If D is set to the TQ0CCR0 register and D to the TQ0CCRb register, the active level width and output delay period of the one-shot pulse are as follows.
Page 345 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in one-shot pulse output mode <R> Figure 7-28. Software Processing Flow in One-Shot Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TQ0CE bit External trigger input (TRGQ0 pin input) TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register...
Page 346 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) <R> Figure 7-28. Software Processing Flow in One-Shot Pulse Output Mode (2/2) <2> Count operation stop flow <1> Count operation start flow Count operation is stopped TQ0CE bit = 0 START STOP Initial setting of these Register initial setting registers is performed TQ0CTL0 register...
Page 347 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TQ0CCRa register If the value of the TQ0CCRa register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 348 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Generation timing of compare match interrupt request signal (INTTQ0CCb) The generation timing of the INTTQ0CCb signal in the one-shot pulse output mode is different from INTTQ0CCb signals in other modes; the INTTQ0CCb signal is generated when the count value of the 16- bit counter matches the value of the TQ0CCRb register.
Page 349: Pwm Output Mode (Tq0Md2 To Tq0Md0 Bits = 100)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.6.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) This mode is valid only in TMQ0. In the PWM output mode, a PWM waveform is output from the TOQ01 to TOQ03 pins when the TQ0CTL0.TQ0CE bit is set to 1.
Page 350 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-30. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register INTTQ0CC1 signal TOQ01 pin output Active Active Active Active level width level width level width level width...
Page 351 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs PWM waveform from the TOQ0b pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TQ0CCRb register ) ×...
Page 352 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-31. Register Setting in PWM Output Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0IOC0 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of TOQ00 pin output level before count operation 0: Low level...
Page 353 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-31. Register Setting in PWM Output Mode (3/3) (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) If D is set to the TQ0CCR0 register and D to the TQ0CCRb register, the cycle and active level of the PWM waveform are as follows.
Page 354 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in PWM output mode Figure 7-32. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register CCR0 buffer register INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register CCR1 buffer register INTTQ0CC1 signal...
Page 355 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-32. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <4> TQ0CCR1 to TQ0CCR3 register setting change flow Writing of the TQ0CCR1 START Setting of TQ0CCR2, register must be performed TQ0CCR3 registers when the set duty factor is only changed after writing the...
Page 356 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQ0CCR1 register last. <R> Rewrite the TQ0CCRa register after writing the TQ0CCR1 register after the INTTQ0CC0 signal is detected. FFFFH 16-bit counter 0000H...
Page 357 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) To transfer data from the TQ0CCRa register to the CCRa buffer register, the TQ0CCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TQ0CCR0 register, set the active level width to the TQ0CCR2 and TQ0CCR3 registers, and then set an active level width to the TQ0CCR1 register.
Page 358 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TQ0CCRb register to 0000H. The 16-bit counter is cleared to 0000H and the INTTQ0CC0 and INTTQ0CCb signals are generated at the next timing after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register.
Page 359 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Generation timing of compare match interrupt request signal (INTTQ0CCb) The timing of generation of the INTTQ0CCb signal in the PWM output mode differs from the timing of INTTQ0CCb signals in other modes; the INTTQ0CCb signal is generated when the count value of the 16- bit counter matches the value of the TQ0CCRb register.
Page 360: Free-Running Timer Mode (Tqnmd2 To Tqnmd0 Bits = 101)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.6.6 Free-running timer mode (TQnMD2 to TQnMD0 bits = 101) The compare function is valid in both TMQ0 and TMQ1. The capture function is valid in TMQ0 only. In the free-running timer mode, 16-bit timer/event counter Q starts counting when the TQnCTL0.TQnCE bit is set to 1.
Page 361 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) • Compare operation When the TQnCE bit is set to 1, 16-bit timer/event counter Q starts counting, and the output signals of the Note TOQ00 to TOQ03 and TOQ10 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TQnCCRa register, a compare match interrupt request signal (INTTQnCCa) is generated, and Note the output signals of the TOQ00 to TOQ03 and TOQ10...
Page 362 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) • Capture operation When the TQ0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQ0a pin is detected, the count value of the 16-bit counter is stored in the TQ0CCRa register, and a capture interrupt request signal (INTTQ0CCa) is generated.
Page 363 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-36. Register Setting in Free-Running Timer Mode (1/3) (a) TMQn control register 0 (TQnCTL0) TQnCE TQnCKS2 TQnCKS1 TQnCKS0 TQnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TQ0CTL1.TQ0EEE bit = 1. (b) TMQn control register 1 (TQnCTL1) TQ0EST TQ0EEE...
Page 364 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-36. Register Setting in Free-Running Timer Mode (2/3) (c) TMQn I/O control register 0 (TQnIOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQnOL0 TQnOE0 TQnIOC0 Note 0: Disable TOQn0 pin output Note 1: Enable TOQn0 pin output Note Setting of TOQn0 pin...
Page 365 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-36. Register Setting in Free-Running Timer Mode (3/3) (e) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 TQ0IOC2 Select valid edge of external event count input (EVTQ0 pin) (f) TMQn option register 0 (TQnOPT0) TQ0CCS1 TQ0CCS0 TQnCMS TQnCUF TQnOVF...
Page 366 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 7-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter 0000H TQnCE bit TQnCCR0 register INTTQnCC0 signal Note...
Page 367 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Initial setting of these registers Register initial setting is performed before setting the TQnCTL0 register TQnCE bit to 1.
Page 368 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) When using capture/compare register as capture register Figure 7-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TQ0CE bit TIQ00 pin input TQ0CCR0 register 0000 0000 INTTQ0CC0 signal TIQ01 pin input TQ0CCR1 register...
Page 369 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TQ0CTL0 register is performed before setting the (TQ0CKS0 to TQ0CKS2 bits) TQ0CE bit to 1.
Page 370 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter Q is used as an interval timer with the TQnCCRa register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTQnCCa signal has been detected.
Page 371 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, the value of the corresponding TQnCCRa register must be re-set in the interrupt servicing that is executed when the INTTQnCCa signal is detected.
Page 372 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TQ0CCRa register used as a capture register, software processing is necessary for reading the capture register each time the INTTQ0CCa signal has been detected and for calculating an interval.
Page 373 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) When executing pulse width measurement in the free-running timer mode, four pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TQ0CCRa register in synchronization with the INTTQ0CCa signal, and calculating the difference between the read value and the previously read value.
Page 374 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Processing of overflow when two or more capture registers are used Care must be exercised in processing the overflow flag when two or more capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two or more capture registers are used FFFFH 16-bit counter...
Page 375 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TQ0CE bit INTTQ0OV signal TQ0OVF bit Note TQ0OVF0 flag TIQ00 pin input TQ0CCR0 register Note TQ0OVF1 flag TIQ01 pin input TQ0CCR1 register <1>...
Page 376 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TQ0CE bit INTTQ0OV signal TQ0OVF bit Note TQ0OVF0 flag TIQ00 pin input TQ0CCR0 register Note TQ0OVF1 flag TIQ01 pin input TQ0CCR1 register <1>...
Page 377 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
Page 378 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TQ0CE bit TIQ0a pin input TQ0CCRa register INTTQ0OV signal TQ0OVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1>...
Page 379 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TQnOVF bit to 0 with the CLR instruction after reading the TQnOVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TQnOPT0 register after reading the TQnOVF bit when it is 1.
Page 380: Pulse Width Measurement Mode (Tq0Md2 To Tq0Md0 Bits = 110)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) 7.6.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter Q starts counting when the TQ0CTL0.TQ0CE bit is set to 1. Each time the valid edge input to the TIQ0a pin has been detected, the count value of the 16-bit counter is stored in the TQ0CCRa register, and the 16-bit counter is cleared to 0000H.
Page 381 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-40. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQ0CE bit TIQ0a pin input 0000H TQ0CCRa register INTTQ0CCa signal INTTQ0OV signal Cleared to 0 by TQ0OVF bit CLR instruction Remark a = 0 to 3 When the TQ0CE bit is set to 1, the 16-bit counter starts counting.
Page 382 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-41. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CKS2 TQ0CKS1 TQ0CKS0 TQ0CTL0 Note Select count clock 0: Stop counting 1: Enable counting Note Setting is invalid when the TQ0CTL1.TQ0EEE bit = 1. (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE...
Page 383 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 7-41. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMQ0 option register 0 (TQ0OPT0) TQ0CCS3 TQ0CCS2 TQ0CCS1 TQ0CCS0 TQ0CMS TQ0CUF TQ0OVF TQ0OPT0 Overflow flag (f) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register.
Page 384 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in pulse width measurement mode Figure 7-42. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQ0CE bit TIQ00 pin input 0000H 0000H TQ0CCR0 register INTTQ0CC0 signal <1>...
Page 385 CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TQ0OVF bit to 0 with the CLR instruction after reading the TQ0OVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TQ0OPT0 register after reading the TQ0OVF bit when it is 1.
Page 386: Chapter 8 16-Bit 2-Phase Encoder Input Up/Down Counter/ General-Purpose Timer (Timer Enc1N)
GENERAL-PURPOSE TIMER (TIMER ENC1n) 8.1 Functions The 16-bit 2-phase encoder input up/down counter/general-purpose timer (timer ENC1n) performs the following operations (V850E/IA3: n = 0, V850E/IA4: n = 0, 1). • General-purpose timer mode (see 8.5.1 Operation in general-purpose timer mode) Free-running timer <R>...
Page 387 PD70F3186 (V850E/IA4), because the I/O pins (TIUD11, TO11, TCUD11, TCLR11) of timer ENC11 and input pins (DDI, DCK, DMS) of the on-chip debug function are the alternate-function pin, two functions cannot be used at the same time. Remark V850E/IA3: n = 0 V850E/IA4: n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 388: Configuration
/128, /256 CC1n1 Read/write INTCCn1 TCLR1n or TCUD1n Remarks 1. f : Peripheral clock 2. V850E/IA3: n = 0, V850E/IA4: n = 0, 1 Figure 8-1. Block Diagram of Timer ENC1n Internal bus Edge detector/ INTCCn0 noise eliminator CC1n0 Selector...
Page 389 CM1n0 and CM1n1 registers is permitted (writing the same value is guaranteed even during a count operation). Note After reset: 0000H Address: TMENC10 FFFFF580H, TMENC11 FFFFF5A0H TMENC1n V850E/IA3 n = 0 V850E/IA4 n = 0, 1 Note V850E/IA4 only TMENC1n start and stop is controlled by the TMC1n.TM1CEn bit.
Page 390 CM1n1 register set value during count down operation Other than above Setting prohibited Remarks 1. ×: Indicates that the set value of that bit is ignored. 2. V850E/IA3: n = 0 V850E/IA4: n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 391: Control Registers
B) is prohibited. Note After reset: 00H Address: TUM10 FFFFF58BH, TUM11 FFFFF5ABH TUM1n CMDn TOEn ALVT10n MSELn V850E/IA3 n = 0 CMDn TMENC1n operation mode specification V850E/IA4 n = 0, 1 General-purpose timer mode (count up) UDC mode (count up/down) TOEn...
Page 392 CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n) (2) Timer control register 1n (TMC1n) The TMC1n register enables/disables TMENC1n operation and sets transfer and timer clear operations. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 393 After reset: 00H Address: TMC10 FFFFF58CH, TMC11 FFFFF5ACH <6> TMC1n TM1CEn RLENn ENMDn CLRn1 CLRn0 V850E/IA3 n = 0 TM1CEn TMENC1n operation control V850E/IA4 n = 0, 1 Count operation disabled Count operation enabled RLENn Specification of transfer operation from the CM1n0 register to TMENC1n...
Page 394 Therefore, when the TCLR1n input is used in UDC mode A, the external capture function cannot be used. Note After reset: 00H Address: CCR10 FFFFF58AH, CCR11 FFFFF5AAH CCR1n CMSn1 CMSn0 V850E/IA3 n = 0 CMSn1 CC1n1 register operation mode specification V850E/IA4 n = 0, 1 Operates as capture register Operates as compare register...
Page 395 CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n) Note After reset: 00H Address: SESA10 FFFFF58DH, SESA11 FFFFF5ADH SESA1n TESUDn1 TESUDn0 CESUDn1 CESUDn0 IESUD1n1 IESUD1n0 IESUD0n1 IESUD0n0 V850E/IA3 TIUD1n, TCUD1n TCLR1n CC1n1 CC1n0 n = 0 capture trigger capture trigger...
Page 396 3. When TMENC1n is in mode 4, specification of the valid edge for the TIUD1n and TCUD1n pins is invalid. Note After reset: 07H Address: PRM10 FFFFF58EH, PRM11 FFFFF5AEH PRM1n PRM1n2 PRM1n1 PRM1n0 V850E/IA3 n = 0 PRM1n2 PRM1n1 PRM1n0 CMDn = 0 CMDn = 1 V850E/IA4...
Page 397 Note After reset: 00H Address: STATUS10 FFFFF58FH, STATUS11 FFFFF5AFH <2> <1> <0> STATUS1n TM1UDFn TM1OVFn TM1UBDn V850E/IA3 n = 0 TM1UDFn TMENC1n underflow flag V850E/IA4 No TMENC1n count underflow n = 0, 1 TMENC1n count underflow The TM1UDFn bit is cleared (0) upon completion of a read access to the STATUS1n register from the CPU.
Page 398 This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Note After reset: 00H Address: CSL10 FFFFF596H, CSL11 FFFFF5B6H CSL1n CSL1n0 V850E/IA3 n = 0 CSL1n0 Selection of capture input signal of CC1n1 register V850E/IA4 TCLR1n input...
Page 399 Caution When the TMC1n.TM1CEn bit is 1, it is prohibited to overwrite the value of the CM1n0 register. Note After reset: 0000H Address: CM100 FFFFF582H, CM110 FFFFF5A2H CM1n0 V850E/IA3 n = 0 V850E/IA4 n = 0, 1 Note V850E/IA4 only User’s Manual U16543EJ4V0UD...
Page 400 Caution When the TMC1n.TM1CEn bit is 1, it is prohibited to overwrite the value of the CM1n1 register. Note After reset: 0000H Address: CM101 FFFFF584H, CM111 FFFFF5A4H CM1n1 V850E/IA3 n = 0 V850E/IA4 n = 0, 1 Note V850E/IA4 only User’s Manual U16543EJ4V0UD...
Page 401 Note After reset: 0000H Address: CC100 FFFFF586H, CC110 FFFFF5A6H CC1n0 V850E/IA3 n = 0 V850E/IA4 n = 0, 1 Note V850E/IA4 only (a) When set as a capture register When CC1n0 is set as a capture register, the valid edge of the corresponding external interrupt request signal (TCUD1n) is detected as the capture trigger.
Page 402 Note After reset: 0000H Address: CC101 FFFFF588H, CC111 FFFFF5A8H CC1n1 V850E/IA3 n = 0 V850E/IA4 n = 0, 1 Note V850E/IA4 only (a) When set as a capture register When CC1n1 is set as a capture register, the valid edge of the corresponding external interrupt request signal (TCLR1n) is detected as the capture trigger.
Page 403: Operation
CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n) 8.5 Operation 8.5.1 Operation in general-purpose timer mode TMENC1n can perform the following operations in the general-purpose timer mode. (1) Interval operation (when TMC1n. ENMDn bit = 1) TMENC1n and the CM1n0 register always compare their values and the INTCMn0 interrupt request signal is generated upon occurrence of a match.
Page 404 CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n) <R> (5) PWM output operation PWM output operation is performed from the TO1n pin by setting TMENC1n to the general-purpose timer mode (TUM1n.CMDn bit = 0) using TUM1n register. The resolution is 16 bits, and the count clock can be selected from among seven internal clocks (f /4, f /16, f...
Page 405: Operation In Udc Mode
CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n) 8.5.2 Operation in UDC mode (1) Overview of operation in UDC mode The count clock input to TMENC1n in the UDC mode (TUM1n.CMDn bit = 1) can only be externally input from the TIUD1n and TCUD1n pins.
Page 406 CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n) (2) Up/count down operation in UDC mode TMENC1n up/count down judgment in the UDC mode is determined based on the phase difference of the TIUD1n and TCUD1n pin inputs according to the PRM1n register setting. (a) Mode 1 (PRM1n.PRM1n2 bit = 1, PRM1n.PRM1n1 bit = 0, PRM1n.PRM1n0 bit = 0) In mode 1, the following count operations are performed based on the level of the TCUD1n pin upon detection of the valid edge of the TIUD1n pin.
Page 407 CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n) (b) Mode 2 (PRM1n.PRM1n2 bit = 1, PRM1n.PRM1n1 bit = 0, PRM1n.PRM1n0 bit = 1) The count conditions in mode 2 are as follows. • TMENC1n count up upon detection of valid edge of TIUD1n pin •...
Page 408 CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n) Figure 8-8. Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD1n Pin): In Case of Simultaneous TIUD1n, TCUD1n Pin Edge Timing TIUD1n TCUD1n TMENC1n 0007H 0008H 0009H 000AH 0009H...
Page 409 CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n) (3) Operation in UDC mode A (a) Interval operation The operations at the count clock following a match of the TMENC1n count value and the CM1n0 register set value are as follows. •...
Page 410 CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n) (4) Operation in UDC mode B (a) Basic operation The operations at the next count clock after the count value of TMENC1n and the CM1n0 register set value match when TMENC1n is in UDC mode B are as follows. •...
Page 411: Supplementary Description Of Internal Operation
CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n) 8.6 Supplementary Description of Internal Operation 8.6.1 Clearing of count value in UDC mode B When TMENC1n is in UDC mode B, the conditions to clear the count value are as follows. •...
Page 412: Transfer Operation
CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n) Figure 8-13. Clear Operation After Match of CM1n1 Register Set Value and TMENC1n Count Value (a) Count down → Count down TMENC1n cleared Count clock (Rising edge set as valid edge) TMENC1n 00FFH 00FEH...
Page 413: Interrupt Request Signal Output Upon Compare Match
CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n) 8.6.3 Interrupt request signal output upon compare match An interrupt request signal is output when the count value of TMENC1n matches the set value of the CM1n0, Note Note CM1n1, CC1n0 , or CC1n1 register.
Page 414: Chapter 9 16-Bit Interval Timer M (Tmm)
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Overview • Interval function • 8 clocks selectable • 16-bit counter × 1 (The 16-bit counter cannot be read during timer count operation.) • Compare register × 1 (The compare register cannot be written during timer counter operation.) •...
Page 415: Configuration
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Configuration TMM0 includes the following hardware. Table 9-1. Configuration of TMM0 Item Configuration Timer register 16-bit counter Register TMM0 compare register 0 (TM0CMP0) Control register TMM0 control register 0 (TM0CTL0) Figure 9-1. Block Diagram of TMM0 Internal bus TM0CTL0 TM0CE TM0CKS2 TM0CKS1TM0CKS0...
Page 416: Control Register
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Control Register (1) TMM0 control register 0 (TM0CTL0) The TM0CTL0 register is an 8-bit register that controls the TMM0 operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TM0CTL0 register by software.
Page 417: Operation
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Operation 9.4.1 Interval timer mode In the interval timer mode, an interrupt request signal (INTTM0EQ0) is generated at the interval set by the TM0CMP0 register if the TM0CTL0.TM0CE bit is set to 1. Figure 9-2.
Page 418 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) When the TM0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. When the count value of the 16-bit counter matches the value of the TM0CMP0 register, the 16-bit counter is cleared to 0000H, and a compare match interrupt request signal (INTTM0EQ0) is generated.
Page 419 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (1) Interval timer mode operation flow Figure 9-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TM0CE bit TM0CMP0 register INTTM0EQ0 signal <1> <2> <1> Count operation start flow START Initial setting of these registers is performed before setting the TM0CE bit to 1.
Page 420 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (2) Interval timer mode operation timing (a) Operation if TM0CMP0 register is set to 0000H If the TM0CMP0 register is set to 0000H, the INTTM0EQ0 signal is generated at each count clock. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter FFFFH...
Page 421: Cautions
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Cautions (1) Error on starting timer It takes one clock to generate the first compare match interrupt request signal (INTTM0EQ0) after the TM0CTL0.TM0CE bit is set to 1 and TMM0 is started. This is because the value of the 16-bit counter is FFFFH when the TM0CE bit = 0 and TMM0 is started asynchronously to the count clock.
Page 422: Chapter 10 Motor Control Function
• At overvoltage detection by comparator function of A/D converter • At main clock oscillation stop detection by clock monitor function Remark V850E/IA3: n = 0, m = 2 V850E/IA4: n = 0, 1, m = 2, 3 User’s Manual U16543EJ4V0UD...
Page 423: Configuration
High-impedance output control registers 0, 1 (HZAyCTL0, HZAyCTL1) Remark V850E/IA3: m = 0 to 3, n = 0, y = 0, 2, a = 0, 1 V850E/IA4: m = 0 to 3, n = 0, 1, y = 0 to 2, a = 0, 1 •...
Page 424 (INTTQnCC0) A/D trigger of A/D converters 0 and 1 INTC Valley interrupt (INTTQnOV) • Interrupt control Edge detection Edge detection Remark V850E/IA3: n = 0, m = 2 V850E/IA4: n = 0, 1, m = 2, 3 User’s Manual U16543EJ4V0UD...
Page 425 0 TMPn A/D trigger A/D trigger selection INTTPnCC0 generator (TQnOPT3 register) INTTPnCC1 Up/down selection TQTADTn1 converter 1 Note TOQ01, TOQ02, and TOQ03 function alternately as output pins. Remark V850E/IA3: n = 0 V850E/IA4: n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 426 Remarks 1. The operation differs when the TQnOPT2.TQnDTM bit = 1. For details, see 10.4.2 (4) Automatic dead-time width narrowing function (TQnOPT2.TQnDTM bit = 1). 2. V850E/IA3: n = 0, m = 1 to 3 V850E/IA4: n = 0, 1, m = 1 to 3 User’s Manual U16543EJ4V0UD...
Page 427: Control Registers
Caution The TQnCMS and TQnCUF bits can be set only in the 6-phase PWM output mode. Be sure to clear these bits to 0 when TMQn is used alone (V850E/IA3: n = 0, V850E/IA4: n = 0, 1). After reset: 00H Address: TQ0OPT0 FFFFF5C5H, TQ1OPT0 FFFFF605H <6>...
Page 428 TQnOPT1 TQnICE TQnIOE TQnID4 TQnID3 TQnID2 TQnID1 TQnID0 V850E/IA3 n = 0 <R> Note 2 TQnICE Crest interrupt (INTTQnCC0 signal) enable V850E/IA4 Do not use INTTQnCC0 signal (do not use it as count signal for interrupt n = 0, 1 culling).
Page 429 <2> <1> <7> <0> TQnOPT2 TQnRDE TQnDTM TQnATM03 TQnATM02 TQnAT03 TQnAT02 TQnAT01 TQnAT00 V850E/IA3 n = 0 TQnRDE Transfer culling enable m = 1 to 3 Do not cull transfer (transfer timing is generated every time at crest V850E/IA4 and valley).
Page 430 CHAPTER 10 MOTOR CONTROL FUNCTION (2/2) TQnATM03 TQnATM03 mode selection Output A/D trigger signal (TQTADTn0) for INTTPnCC1 interrupt while dead-time counter is counting up. Output A/D trigger signal (TQTADTn0) for INTTPnCC1 interrupt while dead-time counter is counting down. TQnATM02 TQnATM02 mode selection Output A/D trigger signal (TQTADTn0) for INTTPnCC0 interrupt while dead-time counter is counting up.
Page 431 <5> <4> <3> <2> <1> <0> TQnOPT3 TQnATM13 TQnATM12 TQnAT13 TQnAT12 TQnAT11 TQnAT10 V850E/IA3 n = 0 TQnATM13 TQnATM13 mode selection V850E/IA4 Output A/D trigger signal (TQTADTn1) of INTTPnCC1 interrupt while n = 0, 1 dead-time counter is counting up.
Page 432 <5> <4> <3> <2> <7> TQnIOC3 TQnOLB3 TQnOEB3 TQnOLB2 TQnOEB2 TQnOLB1 TQnOEB1 V850E/IA3 n = 0 m = 1 to 3 TQnOLBm Setting of TOQnBm pin output level Disable inversion of output of TOQnBm pin V850E/IA4 n = 0, 1...
Page 433 TQnOEm bit = 1, TQnOLm bit = 1 (negative-phase output) TQnOEBm bit = 1, TQnOLBm bit = 1 (negative-phase output) TOQnTm pin output TOQnBm pin output Remark V850E/IA3: n = 0, m = 1 to 3 V850E/IA4: n = 0, 1, m = 1 to 3 User’s Manual U16543EJ4V0UD...
Page 434 TOQnTm positive-phase output High-level output High-level output TOQnTm negative-phase output Remark V850E/IA3: n = 0, m = 1 to 3 V850E/IA4: n = 0, 1, m = 1 to 3 Table 10-2. TOQnBm Pin Output TQnOLBm Bit TQnOEBm Bit TQnCE Bit...
Page 435 CHAPTER 10 MOTOR CONTROL FUNCTION (6) High-impedance output control registers 00, 01, 10, 11, 20, 21 (HZAmCTL0, HZAmCTL1) The HZAmCTL0 and HZAmCTL1 registers are 8-bit registers that control the high-impedance state of the output buffer. These registers can be read or written in 8-bit or 1-bit units. However, the HZAmDCFn bit is a read-only bit and cannot be written.
Page 436 (by setting HZAmDCEn bit to 1). If the external pin is at the active level when the operation is enabled, therefore, high-impedance output control is not performed. Notes 1. V850E/IA4 only 2. • V850E/IA3 HZA0CTL0: TOQ0OFF pin, HZA0CTL1: TOP2OFF pin, HZA2CTL0: ANI00, ANI01 pins, HZA2CTL1: ANI10 to ANI12 pins •...
Page 437 • This bit is set to 1 when an edge indicating abnormality is input to the Note external pin (which is detected according to the setting of the HZAmDCNn and HZAmDCPn bits). Note • V850E/IA3 HZA0CTL0: TOQ0OFF pin, HZA0CTL1: TOP2OFF pin, HZA2CTL0: ANI00, ANI01 pins, HZA2CTL1: ANI10 to ANI12 pins •...
Page 438 CHAPTER 10 MOTOR CONTROL FUNCTION Figure 10-4. High-Impedance Output Controller Configuration INTP0 Edge detection Edge detection INTP2 INTP2/ Analog HZA0CTL1 TOP2OFF delay TMP2 TOP21 Analog INTP0/ HZA0CTL0 TOQ0OFF delay CMPEN0 ANI00 TOQ0B1 TMQOP0 INTCMP0 − TOQ0T1 ANI01 Analog HZA2CTL0 delay −...
Page 439 However, if the external pin is not used with the HZAmDCPn bit and HZAmDCNn bit cleared to 0, the pin goes into a high-impedance state when the HZAmDCTn bit is set to 1. Note • V850E/IA3 HZA0CTL0: TOQ0OFF pin, HZA0CTL1: TOP2OFF pin,...
Page 440: Operation
The functions of the compare registers are as follows. TMPn can perform a tuning operation with TMQn to start a conversion trigger source for A/D converters 0 and Remark V850E/IA3: n = 0 V850E/IA4: n = 0, 1 Compare Register...
Page 441 (W) TQnCCR3 register (phase W output data) TOQnB3 pin TOB3 output (W) TQnDTC register (dead-time value) Note TOQ01, TOQ02, and TOQ03 function alternately as output pins. Remark V850E/IA3: n = 0 V850E/IA4: n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 442 U, V, and W is 0 or lower, it is converged to 0 (100% output). If the operation value is higher than “(M + 1) × 2”, it is converged to (M + 1) × 2 (0% output). Remark V850E/IA3: n = 0 V850E/IA4: n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 443 0000H − m TQnCUF bit = 0 Counting up (m+1) − 0001H TQnCUF bit = 1 Counting down Remarks 1. m = Set value of TQnCCR0 register 2. V850E/IA3: n = 0 V850E/IA4: n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 444 (U) TOQnT2 pin output (V) TOQnB2 pin output (V) TOQnT3 pin output (W) TOQnB3 pin output (W) INTTQnCC0 (crest interrupt) INTTQnOV (valley interrupt) TQnCUF (up/down flag) Remark V850E/IA3: n = 0 V850E/IA4: n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 445: Dead-Time Control (Generation Of Negative-Phase Wave Signal)
(b) No dead time (TQnDTC register = 000H) 16-bit counter TOQnm signal (internal signal) Dead-time 0000H counter m TOQnTm pin output TOQnBm pin output Remark V850E/IA3: n = 0, m = 1 to 3 V850E/IA4: n = 0, 1, m = 1 to 3 User’s Manual U16543EJ4V0UD...
Page 446 (2) PWM output of 0%/100% The V850E/IA3 and V850E/IA4 are capable of 0% wave output and 100% wave output for PWM output. A low level is continuously output from TOQnTm pin as the 0% wave output. A high level is continuously output from TOQnTm pin as the 100% wave output.
Page 447 CHAPTER 10 MOTOR CONTROL FUNCTION <R> Figure 10-10. 100% PWM Output Waveform (With Dead Time) 16-bit counter TQnCCR0 register TQnCCR1 0000H 0000H register CCR1 0000H 0000H 0000H buffer register <1> <2> <3> <4> TOQnT1 pin output 100% 100% output output TOQnB1 pin output Forced timing...
Page 448 CHAPTER 10 MOTOR CONTROL FUNCTION <R> Figure 10-11. PWM Output Waveform from 0% to 100% and from 100% to 0% (With Dead Time) 16-bit counter TQnCCR0 register TQnCCR1 0000H M + 1 0000H M + 1 0000H register CCR1 M + 1 M + 1 0000H 0000H...
Page 449 (internal signal) Dead-time 000H (dead-time counter m does not count.) counter m TOQnTm pin output TOQnBm pin output Remark V850E/IA3: n = 0, m = 1 to 3 V850E/IA4: n = 0, 1, m = 1 to 3 User’s Manual U16543EJ4V0UD...
Page 450 TQnCTL0.TQnCE bit has been set. The first wave is shorter than the second wave because the dead time is fully counted. Remark V850E/IA3: n = 0, m = 1 to 3 V850E/IA4: n = 0, 1, m = 1 to 3 User’s Manual U16543EJ4V0UD...
Page 451 TOQnBm pin output Starts counting Output does not change down. and dead-time counter m continues counting down. Remark V850E/IA3: n = 0, m = 1 to 3 V850E/IA4: n = 0, 1, m = 1 to 3 User’s Manual U16543EJ4V0UD...
Page 452: Interrupt Culling Function
CHAPTER 10 MOTOR CONTROL FUNCTION 10.4.3 Interrupt culling function • The interrupts to be culled are INTTQnCC0 (crest interrupt) and INTTQnOV (valley interrupt). • The TQnOPT1.TQnICE bit is used to enable output of the INTTQnCC0 interrupt and the number of times the interrupt is to be culled.
Page 453 TQnOPT1.TQnID4 to TQnOPT1.TQnID0 bits = 00101 (5 masks) INTTQnCC0 signal INTTQnOV signal TQnOPT1.TQnID4 to TQnOPT1.TQnID0 bits = 00110 (6 masks) INTTQnCC0 signal INTTQnOV signal Remarks 1. : Culled interrupt 2. V850E/IA3: n = 0 V850E/IA4: n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 454 TQnOPT1.TQnID4 to TQnOPT1.TQnID0 bits = 00011 (3 masks) INTTQnCC0 signal INTTQnOV signal TQnOPT1.TQnID4 to TQnOPT1.TQnID0 bits = 00100 (4 masks) INTTQnCC0 signal INTTQnOV signal Remarks 1. : Culled interrupt 2. V850E/IA3: n = 0 V850E/IA4: n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 455 TQnOPT1.TQnID4 to TQnOPT1.TQnID0 bits = 00011 (3 masks) INTTQnCC0 signal INTTQnOV signal TQnOPT1.TQnID4 to TQnOPT1.TQnID0 bits = 00100 (4 masks) INTTQnCC0 signal INTTQnOV signal Remarks 1. : Culled interrupt 2. V850E/IA3: n = 0 V850E/IA4: n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 456 Remarks 1. Transfer is performed when the culled interrupt is output. The other transfer timing is ignored. : Culled interrupt 3. V850E/IA3: n = 0 V850E/IA4: n = 0, 1 (b) TQnCMS bit = 1, TQnRDE bit = 0 or 1 (without transfer control)
Page 457 Remarks 1. Transfer is performed when the culled interrupt is output. The other transfer timing is ignored. : Culled interrupt 3. V850E/IA3: n = 0 V850E/IA4: n = 0, 1 (b) TQnOPT0.TQnCMS bit = 1, TQnOPT0.TQnRDE bit = 0 or 1 (without transfer control)
Page 458 Remarks 1. Transfer is performed when the culled interrupt is output. The other transfer timing is ignored. : Culled interrupt 3. V850E/IA3: n = 0 V850E/IA4: n = 0, 1 (b) TQnOPT0.TQnCMS bit = 1, TQnOPT0.TQnRDE bit = 0 or 1 (without transfer control)
Page 459: Operation To Rewrite Register With Transfer Function
CHAPTER 10 MOTOR CONTROL FUNCTION 10.4.4 Operation to rewrite register with transfer function The following seven registers are provided with a transfer function and used to control a motor. Each of registers has a buffer register. • TQnCCR0: Register that specifies the cycle of the 16-bit counter (TMQ) •...
Page 460 CHAPTER 10 MOTOR CONTROL FUNCTION (1) Anytime rewriting mode This mode is set when the TQnOPT0.TQnCMS bit is 1. The setting of the TQnOPT2.TQnRDE bit is ignored. In this mode, the value written to each register with a transfer function is immediately transferred to an internal buffer register and compared with the value of the counter.
Page 461 <1> <2> <1> <2> <1> <2> <1> <2> Remarks 1. i = Set value of TQnCCRm register 2. V850E/IA3: n = 0, m = 1 to 3 V850E/IA4: n = 0, 1, m = 1 to 3 User’s Manual U16543EJ4V0UD...
Page 462 For details, see 10.4.2 (2) PWM output of 0%/100%. Remarks 1. i, r, k = Set values of TQnCCRm register 2. V850E/IA3: n = 0, m = 1 to 3 V850E/IA4: n = 0, 1, m = 1 to 3...
Page 463 Remarks 1. i, r, k = Set value of TQnCCRm register 2. V850E/IA3: n = 0, m = 1 to 3 V850E/IA4: n = 0, 1, m = 1 to 3 (c) Rewriting TQnOPT1 register The interrupt culling counter is cleared when the TQnOPT1 register is written.
Page 464 CHAPTER 10 MOTOR CONTROL FUNCTION (2) Batch rewrite mode (transfer mode) This mode is set by clearing the TQnOPT0.TQnCMS bit to 0, the TQnOPT1.TQnID4 to TQnOPT1.TQnID0 bits to 00000, and the TQnOPT2.TQnRDE bit to 0. In this mode, the values written to each compare register are transferred to the internal buffer register all at once at the transfer timing and compared with the counter value.
Page 465 CHAPTER 10 MOTOR CONTROL FUNCTION Figure 10-26. Basic Operation in Batch Mode 16-bit counter (TMQn) Transfer <Q2> timing <Q3> TQnCCR0 register CCR0 buffer register TQnCCR1 <Q3> <Q1>&<P1> register CCR1 buffer register <Q3> TQnCCR2 register CCR2 buffer register TQnCCR3 <Q3> register CCR3 buffer register <Q3>...
Page 466 CHAPTER 10 MOTOR CONTROL FUNCTION (b) Rewriting TQnCCR0 register When rewriting the TQnCCR0 register in the batch rewrite mode, the output waveform differs depending on whether transfer occurs at the crest (match between the 16-bit counter value and TQnCCR0 register value) or at the valley (match between the 16-bit counter value and 0001H).
Page 467 CHAPTER 10 MOTOR CONTROL FUNCTION Figure 10-28. Example of Rewriting TQnCCR0 Register (During Counting Up) (a) M > N 16-bit N + 1 N + 1 counter Transfer timing TQnCCR0 register CCR0 buffer 0000H register TQnCCR1 register CCR1 buffer 0000H register TOQnT1 pin output...
Page 468 CHAPTER 10 MOTOR CONTROL FUNCTION Figure 10-29. Example of Rewriting TQnCCR0 Register (During Counting Down) M + 1 16-bit N + 1 counter Transfer timing TQnCCR0 register CCR0 buffer 0000H register TQnCCR1 register CCR1 buffer 0000H register TOQnT1 pin output INTTQnCC0 signal INTTQnOV...
Page 469 CHAPTER 10 MOTOR CONTROL FUNCTION (c) Rewriting TQnCCRm register Figure 10-30. Example of Rewriting TQnCCRm Register 16-bit counter Transfer timing TQnCCRm register CCRm buffer 0000H register TOQnTm pin output INTTQnCCm signal <1> <2> <1> <2> Rewriting during period <1> (rewriting during counting up) Because the TQnCCRm register value is transferred at the transfer timing of the crest (match between the 16- bit counter value and TQnCCR0 register value), an asymmetrical triangular wave is output.
Page 470 CHAPTER 10 MOTOR CONTROL FUNCTION (3) Intermittent batch rewriting mode (transfer culling mode) This mode is set when the TQnOPT0.TQnCMS bit is 0 and the TQnOPT2.TQnRDE bit is 1. In this mode, the values written to each compare register are transferred to the internal buffer register all at once at the culled transfer timing and compared with the counter value.
Page 471 CHAPTER 10 MOTOR CONTROL FUNCTION Figure 10-31. Basic Operation in Intermittent Batch Rewriting Mode 16-bit counter (TMQn) Transfer <Q2> <Q4> <Q4> timing TQnCCR0 <Q3> register CCR0 buffer register TQnCCR1 <Q3> <Q1>&<P1> register CCR1 buffer register <Q3> TQnCCR2 register CCR2 buffer register TQnCCR3 <Q3>...
Page 472 Remarks 1. This is an example of the operation when the TQnOPT1.TQnICE bit = 1, TQnOPT1.TQnIOE bit = 0, TQnOPT1.TQnID4 to TQnOPT1.TQnID0 bits = 00001. : Culled interrupt 3. V850E/IA3: n = 0 V850E/IA4: n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 473 Remarks 1. This is an example of the operation when the TQnOPT1.TQnICE bit = 0, TQnOPT1.TQnIOE bit = 1, TQnOPT1.TQnID4 to TQnOPT1.TQnID0 bits = 00001. : Culled interrupt 3. V850E/IA3: n = 0 V850E/IA4: n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 474 (TQnOPT1.TQnICE Bit = 1, TQnOPT1.TQnIOE Bit = 0, TQnOPT1.TQnID4 to TQnOPT1.TQnID0 = 00001) 16-bit counter Transfer timing TQnCCR1 register CCR1 buffer register TOQnT1 pin output INTTQnCC0 signal INTTQnOV signal Transfer at crest interrupt Remarks 1. : Culled interrupt 2. V850E/IA3: n = 0 V850E/IA4: n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 475 Remarks 1. : Culled interrupt 2. V850E/IA3: n = 0 V850E/IA4: n = 0, 1 (d) Rewriting TQnOPT1 register Because a new interrupt culling value is transferred when the value of the interrupt culling counter matches the value of the 16-bit counter, the next interrupt and those that follow occur at the set interval.
Page 476 Transfer is performed at the subsequent transfer timing and the transfer request signal is cleared. <6> Once transfer has been performed, the transfer request signal is cleared. Therefore, transfer is not performed at the next transfer timing. Remark V850E/IA3: n = 0 V850E/IA4: n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 477: Tmpn Tuning Operation For A/D Conversion Start Trigger Signal Output
The conversion start trigger signal of A/D converters 0 and 1 can be set as the A/D conversion start trigger source by the INTTPnCC0 and INTTPnCC1 signals of TMPn and the INTTQnOV and INTTQnCC0 signals of TMQn. Remark V850E/IA3: n = 0 V850E/IA4: n = 0, 1 (1) Tuning operation starting procedure The TMPn and TMQn registers should be set using the following procedure to perform the tuning operation.
Page 478 CHAPTER 10 MOTOR CONTROL FUNCTION (e) Set the TPnCE bit to 1 and set the TQnCE bit to 1 immediately after that to start the 6-phase PWM output operation. Note 1 Note 1 Note 2 Rewriting the TQnCTL0, TQnCTL1, TQ0IOC1 , TQ0IOC2 , TPnCTL0, TPnCTL1, and TP0IOC0 Note 2...
Page 479 CHAPTER 10 MOTOR CONTROL FUNCTION (4) Basic operation of TMPn during tuning operation The 16-bit counter of TMPn only counts up. The 16-bit counter is cleared by the set cycle value of the TQnCCR0 register and starts counting from 0000H again. The count value of this counter is the same as the value of the 16-bit counter of TMPn when it counts up.
Page 480 Note The TQTADTn0 signal is masked by the TQnOPT2.TQnATM02 and TQnOPT2.TQnATM03 bits. The TQTADTn1 signal is masked by the TQnOPT3.TQnATM12 and TQnOPT3.TQnATM13 bits. Remark V850E/IA3: n = 0, m = 0, 1 V850E/IA4: n = 0, 1, m = 0, 1 User’s Manual U16543EJ4V0UD...
Page 481: A/D Conversion Start Trigger Output Function
CHAPTER 10 MOTOR CONTROL FUNCTION 10.4.6 A/D conversion start trigger output function The V850E/IA3 and V850E/IA4 have a function to select four trigger sources (INTTQnOV, INTTQnCC0, INTTPnCC0, INTTPnCC1) to generate the A/D conversion start trigger signal (TQTADTn0, TQTADTn1) of A/D converters 0 and 1.
Page 482 CHAPTER 10 MOTOR CONTROL FUNCTION • TQnATM03, TQnATM13 bits = 1 The A/D conversion start trigger signal is output when the 16-bit counter counts down (TQnOPT0.TQnCUF bit = 1), and the A/D conversion start trigger signal is not output when the 16-bit counter counts up (TQnOPT0.TQnCUF bit = 0).
Page 483 TQnAT03 to TQnAT00 bits = 1100, TQnATM03 bit = 1, TQnATM02 bit = 0 (INTTPnCC0 and INTTPnCC1 signals ORed for output. Setting to output A/D conversion start trigger signal when match interrupt of TMPn occurs when counter is counting up or down) TQTADTn0 signal Remark V850E/IA3: n = 0 V850E/IA4: n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 484 TQTADTn0 signal Remarks 1. : Culled interrupt 2. V850E/IA3: n = 0 V850E/IA4: n = 0, 1 Figure 10-40. Example of A/D Conversion Start Trigger (TQTADTn0) Signal Output (TQnOPT1.TQnICE Bit = 0, TQnOPT1.TQnIOE Bit = 1, TQnOPT1.TQnID4 to TQnOPT1.TQnID0 Bits = 00010: With Interrupt Culling) (2)
Page 485 If a value higher than “M + 1” is set, the 16-bit counter of TMPn is cleared by “M”. Therefore, the TQTADTnm signal is not output. Remark V850E/IA3: n = 0, m = 0, 1 V850E/IA4: n = 0, 1, m = 0, 1 User’s Manual U16543EJ4V0UD...
Page 486: Chapter 11 Watchdog Timer Functions
CHAPTER 11 WATCHDOG TIMER FUNCTIONS 11.1 Functions The watchdog timer has the following functions. • Reset mode: Reset operation upon overflow of the watchdog timer (generation of WDTRES signal) • Non-maskable interrupt request mode: Non-maskable interrupt operation upon overflow of the watchdog timer (generation of INTWDT signal) Caution The watchdog timer is stopped after reset is released.
Page 487: Control Registers
CHAPTER 11 WATCHDOG TIMER FUNCTIONS 11.3 Control Registers (1) Watchdog timer mode register (WDTM) The WDTM register sets the overflow time and operation clock of the watchdog timer. This register can be read or written in 8-bit units. This register can be read any number of times, but can be written only once following reset release;...
Page 488: Operation
CHAPTER 11 WATCHDOG TIMER FUNCTIONS (2) Watchdog timer enable register (WDTE) The counter of the watchdog timer is cleared and counting restarted by writing “ACH” to the WDTE register. This register can be read or written in 8-bit units. Reset sets this register to 1AH. After reset: 1AH Address: FFFFF6D1H WDTE...
Page 489: Chapter 12 A/D Converters 0 And 1
• Two 10-bit resolution A/D converter circuits (A/D converters 0 and 1) Simultaneous sampling of two circuits possible • Analog input [V850E/IA3] Two circuits, total of six channels A/D converter 0: ANI00 and ANI01 (2 channels) A/D converter 1: ANI10 to ANI13 (4 channels)
Page 490 A/D converter 1: ANI10 to ANI12 • Overvoltage detection comparator • These channels can be used only when the overvoltage detection comparator is used. • [V850E/IA3] Two circuits, total of five channels A/D converter 0: Two channels A/D converter 1: Three channels...
Page 491: Configuration
Cautions 1. If there is noise at the analog input pins (ANIn0 to ANIn3 (only ANI00 and ANI01 for A/D converter 0 of the V850E/IA3)) or at the A/D converter power supply voltage pin (AV that noise may generate an illegal conversion result (n = 0, 1).
Page 492 A/D converter 2 Pin Name Pin No. Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GC (V850E/IA4): 100-pin plastic QFP (14 × 20) User’s Manual U16543EJ4V0UD...
Page 493 INTCMPn − Comparator 1 To high-impedance controller of timer output for motor control OPnCEN2 bit − CMPREF OPnCMP Comparator 2 flag OPnGA0 Note In the V850E/IA3, only ANI12 and ANI13 are valid. Remark n = 0, 1 User’s Manual U16543EJ4V0UD...
Page 494 CHAPTER 12 A/D CONVERTERS 0 AND 1 Figure 12-3. Block Diagram of Trigger Source Selector in Timer Trigger Modes 0 and 1 A/D converter 0 Edge detection/ P04/INTP4/ADTRG0 ADTRG0 noise eliminator Timer (TMQ0 + TMQOP0 + TMP0) TQTADT00 TTRG00 TQTADT01 TTRG01 A/D converter 1 Edge detection/...
Page 495 & hold circuit (n = 0, 1). ANIn0 to ANIn2 (only ANI00 and ANI01 for A/D converter 0 of the V850E/IA3) are provided with an operational amplifier for input level amplification and an overvoltage detection comparator. The operational amplifier and comparator of each analog input pin can be specified to be on or off.
Page 496 (4) Array The array generates the comparison voltage input from an analog input pin (ANIn0 to ANIn3 (ANI00 and ANI01 only for A/D converter 0 of the V850E/IA3)) (n = 0, 1). (5) Successive approximation register (SAR) The SAR is a 10-bit register that sets voltage tap data whose values from the array match the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB).
Page 497 (14) ANIn0 to ANIn3 pins (n = 0, 1) The ANIn0 to ANIn3 pins (only ANI00 and ANI01 pins for A/D converter 0 of the V850E/IA3) are analog input pins for A/D converters 0 and 1. They input the analog signals to be A/D converted.
Page 498: Control Registers
CHAPTER 12 A/D CONVERTERS 0 AND 1 12.3 Control Registers A/D converters 0 and 1 are controlled by the following registers. • A/D converter n mode registers 0 to 2 (ADAnM0 to ADAnM2) • A/D converter n channel specification register (ADAnS) •...
Page 499 CHAPTER 12 A/D CONVERTERS 0 AND 1 After reset: 00H Address: ADA0M0 FFFFF200H, ADA1M0 FFFFF220H < > ADAnM0 ADAnCE ADAnMD1 ADAnMD0 ADAnETS1 ADAnETS0 ADAnTMD ADAnEF (n = 0, 1) ADAnCE A/D conversion operation control Stop conversion operation Start conversion operation ADAnMD1 ADAnMD0 Operation mode specification...
Page 500 CHAPTER 12 A/D CONVERTERS 0 AND 1 (2) A/D converter n mode register 1 (ADAnM1) (n = 0, 1) The ADAnM1 register is an 8-bit register that specifies the number of conversion clocks. The number of conversion clocks includes the number of sampling clocks. This register can be read or written in 8-bit or 1-bit units.
Page 501 → ANIn2 operational amplifier operation Note Note In the V850E/IA3, these can be set only when A/D converter 1 is used. They must not be set when A/D converter 0 is used. Cautions 1. If the ADAnS register is written during A/D conversion (ADAnM0.ADAnEF bit = 1), the operation is performed as follows in each mode.
Page 502 TQTADTa1) of the timer (motor control function). The TQTADTa0 and TQTADTa1 signals are connected to the TTRG0a and TTRG1a signals of A/D converter n (see Figure 12-3) (V850E/IA3: a = 0, V850E/IA4: a = 0, 1). • Timer trigger of A/D converter 0...
Page 503 CHAPTER 12 A/D CONVERTERS 0 AND 1 (2/2) Caution 3. If the ADAnM2 register is written during A/D conversion (ADAnM0.ADAnEF bit = 1), the operation is performed as follows in each mode. • In software trigger mode A/D conversion is stopped and executed again from the beginning. •...
Page 504 ×2.5 ×5 Note In the V850E/IA3, this bit can be set only when A/D converter 1 is used. This bit must be cleared to 0 when A/D converter 0 is used. Cautions 1. Be sure to clear bits 1 to 3 and 7 to “0”.
Page 505 Comparator output = 0 (no overvoltage detection) Comparator output = 1 (overvoltage detection) Notes 1. In the V850E/IA3, this bit can be set only when A/D converter 1 is used. This bit must be cleared to 0 when A/D converter 0 is used.
Page 506 CHAPTER 12 A/D CONVERTERS 0 AND 1 (7) A/Dn conversion result registers 0 to 3, 0H to 3H (ADAnCR0 to ADAnCR3, ADAnCR0H to ADAnCR3H) (n = 0, 1) The ADAnCRm and ADAnCRmH registers are registers that hold the A/D conversion results. Four of these registers are provided per circuit, and two circuits are available.
Page 507 CHAPTER 12 A/D CONVERTERS 0 AND 1 (8) A/Dn conversion result registers 4 to 7, 4H to 7H (ADAnCR4 to ADAnCR7, ADAnCR4H to ADAnCR7H) (n = 0, 1) The ADAnCRm and ADAnCRmH registers are registers that hold the A/D conversion results. These registers can be used only when the operational amplifier for input level amplification is used.
Page 508 CHAPTER 12 A/D CONVERTERS 0 AND 1 The relationship between the analog voltage input to the analog input pin (ANInm) and the A/D conversion result (of A/Dn conversion result register m (ADAnCRm)) is as follows: × 1,024 + 0.5) SAR = INT ( = SAR ×...
Page 509: Operation
CHAPTER 12 A/D CONVERTERS 0 AND 1 12.4 Operation Cautions 1. A/D converters 0 and 1 are capable of simultaneous sampling of two circuits. 2. For operation when using the operational amplifier for input level amplification, refer to 12.3 (3) A/D converter n channel specification register (ADAnS) (n = 0, 1). For the relationship between the analog input pins and A/D conversion result registers, see Table 12-4.
Page 510 CHAPTER 12 A/D CONVERTERS 0 AND 1 (7) Next, bit 8 of the successive approximation register (SAR) is automatically set, and the next comparison is started. The voltage tap of the array is selected according to the value of bit 9, to which the result has been already set.
Page 511: Operation Mode And Trigger Mode
CHAPTER 12 A/D CONVERTERS 0 AND 1 12.4.2 Operation mode and trigger mode Various conversion operations can be specified for the A/D converter by specifying the operation mode and trigger mode. The operation mode and trigger mode are set by the ADAnM0, ADAnM1, ADAnM2, and ADAnS registers. The following shows the relationship between the operation mode and trigger mode.
Page 512 (a) Software trigger mode Of the ANIn0 to ANIn3 pins (only ANI00 and ANI01 pins for A/D converter 0 of the V850E/IA3), the analog input pin specified by the ADAnS.ADAnS2 to ADAnS.ADAnS0 bits is used for the A/D conversion start timing when the ADAnM0.ADAnCE bit is set to 1 in this mode.
Page 513 (b) Timer trigger modes 0 and 1 Of the ANIn0 to ANIn3 pins (only ANI00 and ANI01 pins for A/D converter 0 of V850E/IA3), the analog input pin specified by the ADAnS.ADAnS2 to ADAnS.ADAnS0 bits is used for A/D conversion in this mode.
Page 514 (c) External trigger mode Of the ANIn0 to ANIn3 pins (only ANI00 and ANI01 pins for A/D converter 0 of the V850E/IA3), the analog input pin specified by the ADAnS.ADAnS2 to ADAnS.ADAnS0 bits is used for A/D conversion in this mode (n = 0, 1).
Page 515 . In this mode, the 1-buffer mode and 4-buffer mode are provided for storing the A/D conversion results. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. • 1-buffer mode...
Page 516 CHAPTER 12 A/D CONVERTERS 0 AND 1 Figure 12-5. Continuous Select 1-Buffer Mode Operation Timing (When ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 Bits = 00, ADA0M2.ADA0BS Bit = 0, ADA0S.ADA0S2 to ADA0S.ADA0S0 Bits = 001): V850E/IA4 Data 4 Data 3 Data 2 ANI01 (input) Data 1 Data 5 Data 6...
Page 517 After end of A/D conversion, the conversion is started again from the beginning, unless the ADAnM0.ADAnCE bit is cleared to 0. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Remark n = 0, 1, m = 0 to 3 Figure 12-6.
Page 518 A/D conversion, the conversion is started again from the ANIn0 pin, unless the ADAnM0.ADAnCE bit is cleared to 0. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Remark n = 0, 1, m = 0 to 3 Figure 12-7.
Page 519 . In this mode, the 1-buffer mode and 4-buffer mode are provided for storing the A/D conversion results. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. • 1-buffer mode...
Page 520 (INTADn) is generated when the four A/D conversions end. After end of A/D conversion, the conversion operation is stopped. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Remark n = 0, 1, m = 0 to 3 Figure 12-9.
Page 521 A/Dn conversion end interrupt request signal (INTADn) is generated. After end of A/D conversion, the conversion operation is stopped. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Remark...
Page 522 CHAPTER 12 A/D CONVERTERS 0 AND 1 Figure 12-10. One-Shot Scan Mode Operation Timing (When ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 Bits = 11, ADA0S.ADA0S2 to ADA0S.ADA0S0 Bits = 011): V850E/IA4 Data 1 Data 5 ANI00 (input) Data 2 Data 6 ANI01 (input) Data 3 ANI02 (input) ANI03 (input)
Page 523: Operation In Software Trigger Mode
ADAnCRm register. In the continuous select mode, the 1-buffer mode and 4- buffer mode are supported according to the method of storing the A/D conversion results. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Remark...
Page 524 It is not necessary to set (1) the ADAnM0.ADAnCE bit to restart A/D conversion Notes 1. Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. 2. In the software trigger continuous select 1-buffer mode, the A/D conversion operation is not stopped unless the ADAnM0.ADAnCE bit is cleared to 0.
Page 525 Note 2 conversion Notes 1. Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. 2. In the software trigger continuous select 4-buffer mode, the A/D conversion operation is not stopped unless the ADAnM0.ADAnCE bit is cleared to 0. If the ADAnCRm register is not read before the next A/D conversion ends, it is overwritten.
Page 526: Continuous Scan Mode Operations
In the continuous scan mode, only the 1-buffer mode is supported. Notes 1. Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. 2. In the software trigger continuous scan mode, the A/D conversion operation is not stopped unless the ADAnM0.ADAnCE bit is cleared to 0.
Page 527: One-Shot Select Mode Operations
ADAnCRm register. In the one-shot select mode, the 1-buffer mode and 4-buffer mode are supported according to the method of storing the A/D conversion results. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Remark...
Page 528 If the ADAnM0.ADAnCE bit is set (1), A/D conversion can be restarted. This mode is suitable for applications in which the average of the A/D conversion results is calculated. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Analog Input Pin...
Page 529: One-Shot Scan Mode Operations
In the one-shot scan mode, only the 1-buffer mode is supported. This mode is suitable for applications in which multiple analog inputs are constantly monitored. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Analog Input Pin...
Page 530: Operation In Timer Trigger Modes 0 And 1
If the A/D conversion start trigger signal is generated at an interval shorter than the minimum number of conversion clocks, the last trigger is valid. Remark n = 0, 1 m = 0 to 3 V850E/IA3: a = 0 V850E/IA4: a = 0, 1 User’s Manual U16543EJ4V0UD...
Page 531: Continuous Select Mode/One-Shot Select Mode Operations
The conversion results are stored in the ADAnCRm register. In the continuous select mode or one-shot select mode, the 1-buffer mode and 4-buffer mode are supported according to the method of storing the A/D conversion results. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Remark...
Page 532 After the end of A/D conversion, the A/D converter waits for a trigger. This mode is suitable for applications in which the average of the A/D conversion results is calculated. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Analog Input Pin...
Page 533: Continuous Scan Mode/One-Shot Scan Mode Operations
This mode is suitable for applications in which multiple analog input pins are constantly monitored. In the continuous scan mode or one-shot scan mode, only the 1-buffer mode is supported. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Analog Input Pin...
Page 534: Operation In External Trigger Mode
If the ADAnM0, ADAnM2, and ADAnS registers are written during A/D conversion, the conversion is stopped and the A/D converter waits for a trigger again. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Remark...
Page 535: Continuous Select Mode/One-Shot Select Mode Operations
ADAnCRm register. In the continuous select mode or one-shot select mode, there are two select modes: 1-buffer mode and 4-buffer mode, according to the method of storing the A/D conversion results. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Remark...
Page 536 After the end of A/D conversion, the A/D converter waits for a trigger. This mode is suitable for applications in which the average of the A/D conversion results is calculated. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Analog Input Pin...
Page 537: Continuous Scan Mode/One-Shot Scan Mode Operations
(INTADn) is generated. After the end of A/D conversion, the A/D converter waits for a trigger. This is most suitable for applications in which multiple analog inputs are constantly monitored. Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Analog Input Pin...
Page 538: Internal Equivalent Circuit
2. n = 0, 1 m = 0 to 3 Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. Caution A/D converters 0 and 1 perform the first sampling when A/D conversion starts after A/D initialization.
Page 539 0 V to 5 V at the same time as sampling start. 2. n = 0, 1 m = 0 to 3 Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used. 3. f : System clock frequency...
Page 540: Notes On Operation
CHAPTER 12 A/D CONVERTERS 0 AND 1 12.9 Notes on Operation Caution For operation when using the operational amplifier for input level amplification, refer to 12.3 (3) A/D converter n channel specification register (ADAnS) (n = 0, 1). For the relationship between the analog input pins and A/D conversion result registers, see Table 12-4.
Page 541: Operation In Standby Mode
(INTCMPn), the conversion operation resumes. At this time, the A/Dn conversion end interrupt request signal (INTADn) may be generated, but the conversion result written to the ADAnCRm register will be undefined. Note V850E/IA3: INTP0, INTP2 to INTP5, INTP7 pins V850E/IA4: INTP0 to INTP5, INTP7 pins Remark...
Page 542: Timer Interrupt Request Signal In Timer Trigger Modes 0 And 1
CHAPTER 12 A/D CONVERTERS 0 AND 1 12.9.4 Timer interrupt request signal in timer trigger modes 0 and 1 The timer interrupt request signal (TQTADTn0, TQTADTn1) becomes an A/D conversion start trigger and starts the conversion operation. When this happens, the timer interrupt request signal also functions as an interrupt for the CPU.
Page 543: Restrictions On Setting One-Shot Mode And Software Trigger Mode
CHAPTER 12 A/D CONVERTERS 0 AND 1 <R> 12.9.8 Restrictions on setting one-shot mode and software trigger mode If the A/D converters 0 and 1 are set in the one-shot select mode and software trigger mode (ADAnM0 register = 1010XX0XB) or one-shot scan mode and software trigger mode (ADAnM0 register = 1011XX0XB), a re-conversion operation should be performed in a new condition when data is written to any of the ADAnM0, ADAnM2, and ADAnS registers upon completion of an A/D conversion operation.
Page 544: How To Read A/D Converter Characteristics Table
CHAPTER 12 A/D CONVERTERS 0 AND 1 12.10 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1 LSB (Least Significant Bit).
Page 545 CHAPTER 12 A/D CONVERTERS 0 AND 1 (3) Quantization error When analog values are converted to digital values, a ±1/2 LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of ±1/2 LSB is converted to the same digital code, so a quantization error cannot be avoided.
Page 546 CHAPTER 12 A/D CONVERTERS 0 AND 1 (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (full-scale value − 3/2 LSB) when the digital output changes from 1……110 to 1……111. Figure 12-28.
Page 547 CHAPTER 12 A/D CONVERTERS 0 AND 1 (7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0.
Page 548: Chapter 13 A/D Converter 2
CHAPTER 13 A/D CONVERTER 2 The V850E/IA3 and V850E/IA4 are provided with the A/D converter of the first-order Δ∑ conversion method for which 8-bit or 10-bit resolution can be selected. 13.1 Features • On-chip 8-/10-bit resolution A/D converter using first-order ΔΣ conversion method •...
Page 549: Configuration
Cautions 1. If there is noise at the analog input pins (ANI2n) or at the A/D converter power supply voltage pin (AV ), that noise may generate an illegal conversion result (V850E/IA3: n = 0 to 5, V850E/IA4: n = 0 to 7).
Page 550 A/D converter 2 status register (ADA2STR) (1) Selector The input circuit selects the analog input pins (V850E/IA3: ANI20 to ANI25, V850E/IA4: ANI20 to ANI27) according to the mode set by the ADA2CTL0, ADA2CTL1, ADA2CTL2, and ADA2CTL3 registers and performs A/D conversion.
Page 551 ADA2CTL2, and ADA2CTL3 registers. (12) ANI20 to ANI27 pins The ANI2n pin is an analog input pin for A/D converter 2 (V850E/IA3: n = 0 to 5, V850E/IA4: n = 0 to 7). These pins input the analog signals to be A/D converted.
Page 552: Control Registers
CHAPTER 13 A/D CONVERTER 2 13.3 Control Registers A/D converter 2 is controlled by the following registers. • A/D converter 2 control registers 0 to 3 (ADA2CTL0 to ADA2CTL3) • A/D converter 2 status register (ADA2STR) The following registers are also used. •...
Page 553 (ANI2n) is converted can be calculated from “sampling clock × (sampling counts + 6)” (V850E/IA3: n = 0 to 5, V850E/IA4: n = 0 to 7). Caution Be sure to clear bits 2 to 5 to “0”.
Page 554 CHAPTER 13 A/D CONVERTER 2 (3) A/D converter 2 control register 2 (ADA2CTL2) Note The ADA2CTL2 register is an 8-bit register that specifies the analog input pin (ANI2n) This register can be read or written in 8-bit or 1-bit units. However, if the ADA2CTL2 register is written (if the Note ANI2n pin is changed) during A/D conversion, the conversion under execution is aborted, and conversion of...
Page 555 CHAPTER 13 A/D CONVERTER 2 (4) A/D converter 2 control register 3 (ADA2CTL3) The ADA2CTL3 register is an 8-bit register that specifies the A/D conversion buffer mode and operation mode. This register can be read or written in 8-bit or 1-bit units. However, writing the ADA2CTL3 register during A/D conversion, including writing the same value, is prohibited.
Page 556 CHAPTER 13 A/D CONVERTER 2 Table 13-2. Correspondence Between Analog Input Pin and ADA2CRn Register in 1-Buffer Mode Analog Input Pin ADA2CRn Register ANI20 ADA2CR0 ANI21 ADA2CR1 ANI22 ADA2CR2 ANI23 ADA2CR3 ANI24 ADA2CR4 ANI25 ADA2CR5 Note ANI26 ADA2CR6 Note ANI27 ADA2CR7 Note V850E/IA4 only Figure 13-2.
Page 557 The ADA2STR register is an 8-bit register that is used to confirm the analog input pin (ANI2n) whose signal has been converted (V850E/IA3: n = 0 to 5, V850E/IA4: n = 0 to 7). If selecting an ANI2n pin and the end of the previous A/D conversion conflict, or if there is such a possibility, it can be checked which ANI2n pin has finished being converted.
Page 558 CHAPTER 13 A/D CONVERTER 2 (6) A/D2 conversion result registers 0 to 7, 0H to 7H (ADA2CR0 to ADA2CR7, ADA2CR0H to ADA2CR7H) The ADA2CRn and ADA2CRnH registers are registers that hold the A/D conversion results. Each time A/D conversion ends, the conversion result is loaded from the conversion register (SAR) to this register. The conversion result is stored in the higher 8 bits or 10 bits of the ADA2CRn register at the resolution (8 bits or 10 bits) specified by the ADA2CTL1 register.
Page 559 CHAPTER 13 A/D CONVERTER 2 The correspondence between the analog input pins and the ADA2CRn and ADA2CRnH registers is shown below. Table 13-3. Correspondence Between Analog Input Pins and ADA2CRn and ADA2CRnH Registers Analog Input Pin A/D Conversion Result Register ANI20 ADA2CR0, ADA2CR0H ANI21...
Page 560 CHAPTER 13 A/D CONVERTER 2 The relationship between the analog voltage input to the analog input pin (ANI2n) and the A/D conversion result (of A/D2 conversion result register n (ADA2CRn)) is as follows (when 10-bit resolution setting): × 1,024 + 0.5) SAR = INT ( = SAR ×...
Page 561: Operation
CHAPTER 13 A/D CONVERTER 2 13.4 Operation 13.4.1 Basic operation Once started, A/D converter 2 performs conversion until it is stopped. Each time conversion ends, an A/D2 conversion end interrupt request signal (INTAD2) is generated. A/D conversion is performed in the following sequence.
Page 562: Buffer Mode And Operation Mode
CHAPTER 13 A/D CONVERTER 2 13.4.2 Buffer mode and operation mode With A/D converter 2, continuous conversion and time difference conversion can be specified for one analog input Note pin (ANI2n) specified by the ADA2CTL2 register (n = 0 to 7). The buffer mode and operation mode are specified by the ADA2CTL3 register.
Page 563 CHAPTER 13 A/D CONVERTER 2 (2) Operation mode Note Two operation modes are available: serial mode in which A/D conversion of one analog input pin (ANI2n) continuously executed, and parallel mode in which conversion operations are executed in parallel with the time difference between operations set on starting the first conversion (n = 0 to 7).
Page 564: Operation Timing
CHAPTER 13 A/D CONVERTER 2 13.4.3 Operation timing The operation timing in each buffer mode and operation mode is shown below. (1) 1-buffer serial mode Note 1 A/D conversion of the analog input pin (ANI2n) specified by the ADA2CTL2 register is executed, and the conversion result is continuously stored in A/D2 conversion result register n (ADA2CRn) corresponding to the ANI2n pin (n = 0 to 7).
Page 565 CHAPTER 13 A/D CONVERTER 2 (2) 1-buffer parallel mode Note 1 A/D conversion of the analog input pin (ANI2n) specified by the ADA2CTL2 register is performed four times in parallel, with a time difference. The conversion results are continuously stored in A/D2 conversion result Note 1 register n (ADA2CRn) corresponding to the ANI2n pin (n = 0 to 7).
Page 566 CHAPTER 13 A/D CONVERTER 2 (3) 4-buffer serial mode Note 1 A/D conversion of the analog input pin (ANI2n) specified by the ADA2CTL2 register is performed four times, and the four conversion results are stored in four A/D2 conversion result registers n (ADA2CRn) (n = 0 to 7).
Page 567 CHAPTER 13 A/D CONVERTER 2 (4) 4-buffer parallel mode Note 1 A/D conversion of the analog input pin (ANI2n) specified by the ADA2CTL2 register is performed four times in parallel, with a time difference. The conversion results are continuously stored in four A/D2 conversion Note 1 result registers n (ADA2CRn) corresponding to the ANI2n pin (n = 0 to 7).
Page 568: Internal Equivalent Circuit
15 pF 0.25 pF Remarks 1. The maximum values are shown (reference values). 2. V850E/IA3: n = 0 to 5 V850E/IA4: n = 0 to 7 13.6 How to Read A/D Converter Characteristics Table For details, see 12.10 How to Read A/D Converter Characteristics Table.
Page 569: R> 13.7 Cautions
CHAPTER 13 A/D CONVERTER 2 <R> 13.7 Cautions 13.7.1 Writing to the ADA2CTL1 and ADA2CTL3 registers during conversion Writing the ADA2CTL1 and ADA2CTL3 registers (including writing the same value) during A/D conversion is prohibited. If data is written to the registers during A/D conversion, the conversion result of A/D2 conversion result register n (ADA2CRn) and the conversion operation cannot be guaranteed (n = 0 to 7).
Page 570 CHAPTER 13 A/D CONVERTER 2 (3) Conflicts with ADA2STR register read timing If the timing of storing the A/D conversion result from the SAR register to the ADA2CRn register conflicts with the timing of reading the ADA2STR register, an undefined value is read from the ADA2STR register. The ADA2STR register value itself, though, is correctly updated.
Page 571: Chapter 14 Asynchronous Serial Interface A (Uarta)
14.1 Mode Switching Between UARTA1 and CSIB1 In the V850E/IA3 and V850E/IA4, UARTA1 and CSIB1 function alternately, and these pins cannot be used at the same time. To switch between UARTA1 and CSIB1, the PMC3 and PFC3 registers must be set in advance.
Page 572: Features
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 14.2 Features Transfer rate: 300 bps to 1.25 Mbps (using peripheral clock (f ) of 64 MHz and dedicated baud rate generator) Full-duplex communication: Internal UARTA receive data register n (UAnRX) Internal UARTA transmit data register n (UAnTX) 2-pin configuration: TXDAn: Transmit data output pin RXDAn: Receive data input pin...
Page 573: Configuration
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 14.3 Configuration The block diagram of the UARTAn is shown below. <R> Figure 14-2. Block Diagram of UARTAn Internal bus INTUAnT INTUAnR Reception unit Transmission UAnRX UAnTX unit Receive Transmit Reception Transmission shift register shift register controller controller...
Page 574 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register used to specify the UARTAn operation. (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register used to select the base clock (f ) for the UARTAn.
Page 575: Control Registers
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 14.4 Control Registers (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 10H.
Page 576 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) Note UAnDIR Transfer direction selection MSB-first transfer LSB-first transfer Note Note Parity selection during transmission Parity selection during reception UAnPS1 UAnPS0 No parity output Reception with no parity 0 parity output Reception with 0 parity Odd parity output Odd parity check Even parity output...
Page 577 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (4) UARTAn option control register 0 (UAnOPT0) The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of UARTAn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 14H.
Page 578 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) After reset: 00H Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H <2> <1> <7> <0> UAnSTR UAnTSF UAnPE UAnFE UAnOVE (n = 0, 1) UAnTSF Transfer status flag • When the UAnPWR bit = 0 or the UAnTXE bit = 0 has been set. •...
Page 579 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) UARTAn receive data register (UAnRX) The UAnRX register is an 8-bit buffer register that stores parallel data converted by the UARTAn receive shift register. The data stored in the UARTAn receive shift register is transferred to the UAnRX register upon end of reception of 1 byte of data.
Page 580: Interrupt Request Signals
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 14.5 Interrupt Request Signals The following three interrupt request signals are generated from UARTAn. • Reception error interrupt request signal (INTUAnRE) • Reception end interrupt request signal (INTUAnR) • Transmission enable interrupt request signal (INTUAnT) Among these three interrupt signals, the reception error interrupt signal has the highest default priority, and the reception end interrupt request signal and transmission enable interrupt request signal follow in this order.
Page 581: Operation
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 14.6 Operation 14.6.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 14-3, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s).
Page 582 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 14-3. UARTA Transmit/Receive Data Format (a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start Parity Stop (b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start Parity...
Page 583: Uart Transmission
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 14.6.2 UART transmission A high level is output to the TXDAn pin by setting the UAnCTL0.UAnPWR bit to 1. Next, the transmission enabled status is set by setting the UAnCTL0.UAnTXE bit to 1, and transmission is started by writing transmit data to the UAnTX register.
Page 584: Continuous Transmission Procedure
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 14.6.3 Continuous transmission procedure UARTAn can write the next transmit data to the UAnTX register when the UARTAn transmit shift register starts the shift operation. The transmit timing of the UARTAn transmit shift register can be judged from the transmission enable interrupt request signal (INTUAnT).
Page 585 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 14-6. Continuous Transmission Operation Timing (a) Transmission start Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXDAn pin UAnTX register Data (1) Data (2) Data (3) Transmission Data (2) Data (1) shift register INTUAnT signal...
Page 586: Uart Reception
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 14.6.4 UART reception The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed. Start bit detection is performed using a two-step detection routine.
Page 587: Reception Errors
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 14.6.5 Reception errors Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data reception result error flags are set in the UAnSTR register and a reception error interrupt request signal (INTUAnRE) is output when an error occurs.
Page 588: Parity Types And Operations
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 14.6.6 Parity types and operations The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side. In the case of even parity and odd parity, it is possible to detect odd-count bit errors. In the case of 0 parity and no parity, errors cannot be detected.
Page 589: Receive Data Noise Filter
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 14.6.7 Receive data noise filter This filter samples the RXDAn pin using the base clock (f ) of the prescaler output. UCLK When the same sampling value is read twice, the match detector output changes and the RXDAn signal is sampled as the input data.
Page 590: Dedicated Baud Rate Generator
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 14.7 Dedicated Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel.
Page 591 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register that selects the UARTAn base clock. <R> This register can be read or written in 8-bit unit. Reset sets this register to 00H. Caution Clear the UAnCTL0.UAnPWR bit to 0 before rewriting the UAnCTL1 register.
Page 592 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTAn. This register can be read or written in 8-bit units. Reset sets this register to FFH.
Page 593 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (4) Baud rate The baud rate is obtained by the following equation. UCLK Baud rate = [bps] 2 × k : Frequency of base clock selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits UCLK Value set using the UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (k = 4, 5, 6, ..., 255) (5) Baud rate error The baud rate error is obtained by the following equation.
Page 594 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) Baud rate setting example Table 14-3. Baud Rate Generator Setting Data Baud Rate = 64 MHz = 32 MHz (bps) UAnCTL1 UAnCTL2 ERR (%) UAnCTL1 UAnCTL2 ERR (%) 0.16 0.16 0.16 0.16 1,200 0.16 0.16...
Page 595 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (7) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution The baud rate error during reception must be set within the allowable error range using the following equation.
Page 596 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Therefore, the maximum baud rate that can be received by the destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, obtaining the following maximum allowable transfer rate yields the following. 21k −...
Page 597: Cautions
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (8) Transfer rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result.
Page 598: Chapter 15 Clocked Serial Interface B (Csib)
15.1 Mode Switching Between UARTA1 and CSIB1 In the V850E/IA3 and V850E/IA4, UARTA1 and CSIB1 function alternately, and these functions cannot be used at the same time. To use UARTA1 and CSIB1, the PMC3 and PFC3 registers must be set in advance.
Page 599: Features
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.2 Features Transfer rate: 8 Mbps (using internal clock) Master mode and slave mode selectable 8-bit to 16-bit transfer, 3-wire serial interface Interrupt request signals (INTCBnRE, INTCBnT, INTCBnR) Serial clock and data phase switchable Transfer data length selectable in 1-bit units between 8 and 16 bits Transfer data MSB-first/LSB-first switchable 3-wire transfer SOBn:...
Page 600: Configuration
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.3 Configuration The following shows the block diagram of CSIBn. Figure 15-2. Block Diagram of CSIBn Internal bus CBnCTL1 CBnCTL0 CBnCTL2 CBnSTR INTCBnT Controller INTCBnR INTCBnRE Phase control CCLK /128 /256 CBnTX SCKBn Phase SO latch SOBn...
Page 601 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (1) CSIBn receive data register (CBnRX) The CBnRX register is a 16-bit buffer register that holds receive data. This register is read-only, in 16-bit units. The receive operation is started by reading the CBnRX register in the reception enabled status. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CBnRXL register.
Page 602: Control Registers
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.4 Control Registers The following registers are used to control CSIBn. • CSIBn control register 0 (CBnCTL0) • CSIBn control register 1 (CBnCTL1) • CSIBn control register 2 (CBnCTL2) • CSIBn status register (CBnSTR) (1) CSIBn control register 0 (CBnCTL0) CBnCTL0 is a register that controls the CSIBn serial transfer operation.
Page 603 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2/2) Note 1 CBnDIR Specification of transfer direction mode (MSB/LSB) MSB first LSB first Note 1 CBnTMS Transfer mode specification Single transfer mode Continuous transfer mode • When using single transmission or transmission/reception mode with communication type 2 or 4 (CBnCTL1.CBnDAP bit = 1), write the transfer data to the CBnTX register after checking that the CBnSTR.CBnTSF bit is 0.
Page 604 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (a) How to use CBnSCE bit (i) In single reception mode <1> When the reception of the last data is completed with INTCBnR interrupt servicing, clear the CBnSCE bit to 0, and then read the CBnRX register. <2>...
Page 605 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2) CSIBn control register 1 (CBnCTL1) CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution The CBnCTL1 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0.
Page 606 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (3) CSIBn control register 2 (CBnCTL2) CBnCTL2 is an 8-bit register that controls the number of CSIBn serial transfer bits. This register can be read or written in 8-bit units. Reset sets register to 00H. Caution The CBnCTL2 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0 or when both the CBnTXE and CBnRXE bits = 0.
Page 607 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (a) Transfer data length change function The CSIBn transfer data length can be set in 1-bit units between 8 and 16 bits using the CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits. When the transfer bit length is set to a value other than 16 bits, set the data to the CBnTX or CBnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB.
Page 608 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (4) CSIBn status register (CBnSTR) CBnSTR is an 8-bit register that displays the CSIBn status. This register can be read or written in 8-bit or 1-bit units, but the CBnTSF flag is read-only. Reset sets this register to 00H.
Page 609: Operation
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.5 Operation 15.5.1 Single transfer mode (master mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /4 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 610 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 611: Single Transfer Mode (Master Mode, Reception Mode)
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.5.2 Single transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /4 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 612 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 613: Single Transfer Mode (Master Mode, Transmission/Reception Mode)
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.5.3 Single transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /4 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) <R>...
Page 614 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 615: Single Transfer Mode (Slave Mode, Transmission Mode)
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.5.4 Single transfer mode (slave mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 616 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 617: Single Transfer Mode (Slave Mode, Reception Mode)
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.5.5 Single transfer mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 618 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 619: Single Transfer Mode (Slave Mode, Transmission/Reception Mode)
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.5.6 Single transfer mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 620 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 621: Continuous Transfer Mode (Master Mode, Transmission Mode)
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.5.7 Continuous transfer mode (master mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /4 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 622 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2) Operation timing CBnTSF bit <R> INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 623: Continuous Transfer Mode (Master Mode, Reception Mode)
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.5.8 Continuous transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /4 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) User’s Manual U16543EJ4V0UD...
Page 624 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (1) Operation flow START CBnCTL1 register ← 00H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← A3H CBnRX register dummy read Start reception INTCBnR interrupt generated? INTCBnRE interrupt Is data being received generated? last data? CBnSCE bit = 0...
Page 625 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal CBnSCE bit SCKBn pin SOBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 626: Continuous Transfer Mode (Master Mode, Transmission/Reception Mode)
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.5.9 Continuous transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /4 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) User’s Manual U16543EJ4V0UD...
Page 627 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (1) Operation flow START CBnCTL1 register ← 00H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← E3H Write CBnTX register Start transmission/reception INTCBnT interrupt (6), (11) generated? Yes (11) Is data being transmitted last data? Write CBnTX register Yes (9)
Page 628 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2) Operation timing (1/2) CBnTSF bit INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 629 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2/2) (11) The transfer of the transmit data from the CBnTX register to the shift register is completed and the INTCBnT signal is generated. To end continuous transmission/reception with the current transmission/reception, do not write to the CBnTX register. (12) When the next transmit data is not written to the CBnTX register before transfer completion, stop the serial clock output to the SCKBn pin after transfer completion, and clear the CBnTSF bit to 0.
Page 630: Continuous Transfer Mode (Slave Mode, Transmission Mode)
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.5.10 Continuous transfer mode (slave mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 631 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2) Operation timing CBnTSF bit INTCBnT signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 632: Continuous Transfer Mode (Slave Mode, Reception Mode)
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.5.11 Continuous transfer mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) User’s Manual U16543EJ4V0UD...
Page 633 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (1) Operation flow START CBnCTL1 register ← 07H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← A3H CBnRX register dummy read SCKBn pin input started? Start reception INTCBnR interrupt generated? INTCBnRE interrupt Is data being received generated? last data?
Page 634 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal CBnSCE bit SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 635: Continuous Transfer Mode (Slave Mode, Transmission/Reception Mode)
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.5.12 Continuous transfer mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) User’s Manual U16543EJ4V0UD...
Page 636 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (1) Operation flow START CBnCTL1 register ← 07H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← E3H Write CBnTX register SCKBn pin input started? Start transmission/reception INTCBnT interrupt (6), (11) generated? Yes (11) Is data being transmitted last data?
Page 637 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2) Operation timing (1/2) CBnTSF bit INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 638 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2/2) (12) When the clock of the transfer data length set with the CBnCTL2 register is input without writing to the CBnTX register, the INTCBnR signal is generated. Clear the CBnTSF bit to 0 to end transmission/reception.
Page 639: Reception Error
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.5.13 Reception error When transfer is performed with reception enabled (CBnCTL0.CBnRXE bit = 1) in the continuous transfer mode, the reception error interrupt request signal (INTCBnRE) is generated when the next receive operation is completed before the CBnRX register is read after the reception end interrupt request signal (INTCBnR) is generated, and the overrun error flag (CBnSTR.CBnOVE) is set to 1.
Page 640: Clock Timing
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.5.14 Clock timing (1/2) (i) Communication type 1 (CBnCKP and CBnDAP bits = 00) SCKBn pin SIBn pin capture SOBn pin Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2 interrupt CBnTSF bit (ii) Communication type 3 (CBnCKP and CBnDAP bits = 10) SCKBn pin SIBn pin capture...
Page 641 CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) (2/2) (iii) Communication type 2 (CBnCKP and CBnDAP bits = 01) SCKBn pin SIBn pin capture SOBn pin Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2 interrupt CBnTSF bit (iv) Communication type 4 (CBnCKP and CBnDAP bits = 11) SCKBn pin SIBn pin capture...
Page 642: Output Pins
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB) 15.6 Output Pins (1) SCKBn pin When CSIBn operation is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows. Remark n = 0, 1 CBnCKP CBnCKS2 CBnCKS1 CBnCKS0 SCKBn Pin Output High impedance Other than above Fixed to high level...
Page 643: Chapter 16 Dma Functions (Dma Controller)
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) The V850E/IA3 and V850E/IA4 include a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfers between the internal memory and peripheral I/O, or between peripheral I/Os, based on requests by interrupts from the on-chip peripheral I/O (serial interface, timer, and A/D converter) or DMA requests issued by software triggers.
Page 644: Configuration
(DDAnH/DDAnL) DMA transfer count Count register (DBCn) control block DMA channel control register (DCHCn) DMA addressing control Channel register (DADCn) control block DMA trigger factor register n (DTFRn) DMAC V850E/IA3, V850E/IA4 Remark n = 0 to 3 User’s Manual U16543EJ4V0UD...
Page 645: Control Registers
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) 16.3 Control Registers 16.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) The DSA0 to DSA3 registers set the DMA transfer source address (28 bits) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DSAnH and DSAnL.
Page 646 CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA source address registers 0L to 3L (DSA0L to DSA3L) The DSA0L to DSA3L registers can be read or written in 16-bit units. Reset makes these registers undefined. After reset: Undefined Address: DSA0L FFFFF080H, DSA1L FFFFF088H, DSA2L FFFFF090H, DSA3L FFFFF098H DSAnL SAn15...
Page 647: Dma Destination Address Registers 0 To 3 (Dda0 To Dda3)
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) 16.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) The DDA0 to DDA3 registers set the DMA transfer destination address (28 bits) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DDAnH and DDAnL. Since these registers are configured as 2-stage FIFO buffer registers consisting of the master register and slave register, a new transfer destination address for DMA transfer can be specified during DMA transfer (see 16.8 Next Address Setting Function).
Page 648 CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA destination address registers 0L to 3L (DDA0L to DDA3L) The DDA0L to DDA3L registers can be read or written in 16-bit units. Reset makes these registers undefined. After reset: Undefined Address: DDA0L FFFFF084H, DDA1L FFFFF08CH, DDA2L FFFFF094H, DDA3L FFFFF09CH DDAnL DAn15...
Page 649: Dma Transfer Count Registers 0 To 3 (Dbc0 To Dbc3)
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) 16.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) The DBC0 to DBC3 registers are 16-bit registers that set the byte transfer count for DMA channel n (n = 0 to 3). These registers store the remaining transfer count during DMA transfer.
Page 650: Dma Addressing Control Registers 0 To 3 (Dadc0 To Dadc3)
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) 16.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n = 0 to 3). These registers cannot be accessed during a DMA operation. These registers can be read or written in 16-bit units.
Page 651 CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) After reset: 0000H Address: DADC0 FFFFF0D0H, DADC1 FFFFF0D2H, DADC2 FFFFF0D4H, DADC3 FFFFF0D6H <R> DADCn DSn0 (n = 0 to 3) SADn1 SADn0 DADn1 DADn0 TMn1 TMn0 DSn0 Setting of transfer data size for DMA transfer 8 bits 16 bits SADn1...
Page 652: Dma Channel Control Registers 0 To 3 (Dchc0 To Dchc3)
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) 16.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) The DCHC0 to DCHC3 registers are 8-bit registers that control the DMA transfer operating mode for DMA channel n (n = 0 to 3). These registers can be read or written in 8-bit or 1-bit units.
Page 653 CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) After reset: Address: DCHC0 FFFFF0E0H, DCHC1 FFFFF0E2H, DCHC2 FFFFF0E4H, DCHC3 FFFFF0E6H <7> <3> <2> <1> <0> DCHCn MLEn INITn STGn (n = 0 to 3) Note 1 Status bit that indicates whether DMA transfer via DMA channel n has ended or not DMA transfer has not ended.
Page 654: Dma Trigger Factor Registers 0 To 3 (Dtfr0 To Dtfr3)
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) 16.3.6 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt requests from on-chip peripheral I/O. The interrupt requests set by these registers serve as DMA transfer start factors. These registers can be read or written in 8-bit or 1-bit units.
Page 655 CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) After reset: Address: DTFR0 FFFFF810H, DTFR1 FFFFF812H, DTFR2 FFFFF814H, DTFR3 FFFFF816H <7> DTFRn IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 (n = 0 to 3) Note DMA transfer request status flag DMA transfer not requested DMA transfer requested Note Do not set the DFn bit to “1”...
Page 656 CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) Table 16-1. DMA Start Factors (1/2) IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source DMA request from on-chip peripheral I/O disabled INTP6 INTP7 INTCMP0 INTCMP1 INTTQ0OV INTTQ0CC0 INTTQ0CC1 INTTQ0CC2 INTTQ0CC3 INTTQ1OV INTTQ1CC0 INTTQ1CC1 INTTQ1CC2 INTTQ1CC3 INTCC00 INTCC01...
Page 657 CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) Table 16-1. DMA Start Factors (2/2) IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source INTUA0RE INTUA0R INTUA0T INTCB0RE INTCB0R INTCB0T INTUA1RE INTUA1R INTUA1T INTCB1RE INTCB1R INTCB1T INTAD0 INTAD1 INTAD2 INTTM0EQ0 Other than above Setting prohibited Remark n = 0 to 3 The relationship between the interrupt source and the DMA transfer trigger is as follows (n = 0 to 3).
Page 658: Transfer Modes
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) 16.4 Transfer Modes 16.4.1 Single transfer mode In single transfer mode, the DMAC releases the bus at each byte/halfword transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
Page 659 CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) Figure 16-3 is an example of single transfer where a DMA transfer request with a lower priority is issued one clock after single transfer has been completed. DMA channels 0 and 3 are used for single transfer. If two DMA transfer request signals become active at the same time, two DMA transfer operations are alternately executed.
Page 660: Single-Step Transfer Mode
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) 16.4.2 Single-step transfer mode In single-step transfer mode, the DMAC releases the bus at each byte/halfword transfer. If there is a subsequent DMA transfer request signal, transfer is performed again. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
Page 661: Block Transfer Mode
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) 16.4.3 Block transfer mode In the block transfer mode, once transfer starts, the DMAC continues the transfer operation without releasing the bus until a terminal count occurs. No other DMA requests are acknowledged during block transfer. After the block transfer ends and the DMAC releases the bus, another DMA transfer can be acknowledged.
Page 662: Transfer Types
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) 16.5 Transfer Types 16.5.1 2-cycle transfer In 2-cycle transfer, data transfer is performed in two cycles, a read cycle (source to DMAC) and a write cycle (DMAC to destination). In the first cycle, the source address is output and reading is performed from the source to the DMAC. In the second cycle, the destination address is output and writing is performed from the DMAC to the destination.
Page 663: Next Address Setting Function
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) 16.8 Next Address Setting Function The DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers are two-stage FIFO buffer registers consisting of a master register and a slave register (n = 0 to 3). When the terminal count is issued, these registers are automatically rewritten with the value that was set immediately before.
Page 664: Dma Transfer Start Factors
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) 16.9 DMA Transfer Start Factors There are two types of DMA transfer start factors, as shown below. Cautions 1. Do not use both start factors ((1) and (2)) in combination for the same channel (if both start factors are generated at the same time, only one of them is valid, but the valid start factor cannot be identified).
Page 665: Forcible Termination
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) 16.10 Forcible Termination DMA transfer can be forcibly terminated by the DCHCn.INITn bit (n = 0 to 3). An example of forcible termination by the DCHCn.INITn bit is illustrated below (n = 0 to 3). Figure 16-9.
Page 666: Times Related To Dma Transfer
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) 16.11 Times Related to DMA Transfer The overhead before and after DMA transfer and minimum execution clock for DMA transfer are shown below. Table 16-3. Number of Minimum Execution Clocks in DMA Cycle DMA Cycle Minimum Number of Execution Clocks Note 1 <1>...
Page 667: Dma Transfer End
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) (5) Program execution and DMA transfer with internal RAM Do not execute DMA transfer to/from the internal RAM and an instruction in the internal RAM simultaneously. (6) Restrictions related to automatic clearing of DCHCn.TCn bit The DCHCn.TCn bit is automatically cleared to 0 when it is read.
Page 668: Chapter 17 Interrupt/Exception Processing Function
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850E/IA3 and V850E/IA4 are provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 56 to 61 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 669 3. When TMQm is used in the 6-phase PWM output mode, it functions as INTTQmOV (valley interrupt) from the TMQm option (TMQOPm) (V850E/IA3: m = 0, V850E/IA4: m = 0, 1). 4. When TMQm is used in 6-phase PWM output mode, it functions as INTTQmCC0 (crest interrupt) from the TMQm option (TMQOPm) (V850E/IA3: m = 0, V850E/IA4: m = 0, 1).
Page 670 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 17-1. Interrupt Source List (2/3) Type Classification Interrupt/Exception Source Default Exception Handler Restored Priority Code Address Name Control Generating Source Generating Register Unit Maskable Interrupt INTTQ1CC2 TQ1CCIC2 TQ1CCR2 compare match TMQ1 01A0H 000001A0H nextPC Interrupt INTTQ1CC3 TQ1CCIC3 TQ1CCR3 compare match...
Page 671 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 17-1. Interrupt Source List (3/3) Type Classification Interrupt/Exception Source Default Exception Handler Restored Priority Code Address Name Control Generating Source Generating Register Unit UA0RIC UARTA0 reception UARTA0 0350H 00000350H nextPC Maskable Interrupt INTUA0R completion UA0TIC UARTA0 transmission UARTA0...
Page 672: Non-Maskable Interrupts
(DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupt request signals. The non-maskable interrupt signals of the V850E/IA3 and V850E/IA4 are the non-maskable interrupt request signals generated by the overflow of the watchdog timer (INTWDT).
Page 673: Operation
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.2.1 Operation If a non-maskable interrupt request signal (INTWDT) is generated, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes the exception code (0010H) to the higher halfword (FECC) of ECR.
Page 674 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 17-2. Acknowledging Non-Maskable Interrupt Request (a) If a new INTWDT request is generated while an INTWDT service program is being executed Main routine (PSW.NP bit = 1) INTWDT request is held pending INTWDT request INTWDT request regardless of the value of the PSW.NP bit.
Page 675: Restore
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.2.2 Restore Execution is restored from non-maskable interrupt servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1>...
Page 676: Non-Maskable Interrupt Status Flag (Np)
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (INTWDT) servicing is in progress. The NP flag is allocated to the PSW. This flag is set when an INTWDT interrupt signal has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 677: Maskable Interrupts
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.3 Maskable Interrupts Maskable interrupt request signals can be masked by interrupt control registers. The V850E/IA3 and V850E/IA4 have 60 maskable interrupt sources. If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority.
Page 678 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 17-4. Maskable Interrupt Servicing INT input INTC accepted xxIF = 1 Interrupt requested? xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently being serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests...
Page 679: Restore
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. <1>...
Page 680: Priorities Of Maskable Interrupts
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.3.3 Priorities of maskable interrupts The INTC provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 681 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 17-6. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b (level 3) Interrupt request b is acknowledged because the (level 2) priority of b is higher than that of a and interrupts are...
Page 682 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 17-6. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k...
Page 683 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 17-7. Example of Servicing Interrupt Request Signals Generated Simultaneously Main routine Interrupt request a (level 2) Interrupt request b (level 1) Servicing of interrupt request b Interrupt request b and c are Interrupt request c (level 1) acknowledged first according to their priorities.
Page 684: Interrupt Control Registers (Xxicn)
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.3.4 Interrupt control registers (xxICn) An xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 47H.
Page 685 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION After reset: Address: FFFFF110H to FFFFF186H <7> <6> xxICn xxIFn xxMKn xxPRn2 xxPRn1 xxPRn0 Note xxIFn Interrupt request flag Interrupt request not issued Interrupt request issued xxMKn Interrupt mask flag Interrupt servicing enabled Interrupt servicing disabled (pending) xxPRn2 xxPRn1 xxPRn0...
Page 686 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 17-2. Addresses and Bits of Interrupt Control Registers (1/2) Address Register <7> <6> FFFFF110H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 Note PIC1 FFFFF112H PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF114H PIC2 PIF2 PMK2 PPR22 PPR21 PPR20 FFFFF116H PIC3...
Page 687 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 17-2. Addresses and Bits of Interrupt Control Registers (2/2) Address Register <7> <6> FFFFF162H DMAIC1 DMAIF1 DMAMK1 DMAPR12 DMAPR11 DMAPR10 FFFFF164H DMAIC2 DMAIF2 DMAMK2 DMAPR22 DMAPR21 DMAPR20 FFFFF166H DMAIC3 DMAIF3 DMAMK3 DMAPR32 DMAPR31 DMAPR30 FFFFF168H UA0REIC UA0REIF...
Page 688: Interrupt Mask Registers 0 To 3 (Imr0 To Imr3)
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) The IMR0 to IMR3 registers set the interrupt mask state for the maskable interrupts. The IMR0.xxMKn to IMR3.xxMKn bits are equivalent to the xxICn.xxMKn bit. The IMRm register (m = 0 to 3) can be read or written in 16-bit units.
Page 689 2. These bits are valid only for the V850E/IA4. Be sure to set these bits to 1 in the V850E/IA3. Caution Set bits 15 to 12 of the IMR3 register (bits 7 to 4 of the IMR3H register) to 1. The operation when these settings are changed is not guaranteed.
Page 690: In-Service Priority Register (Ispr)
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.3.6 In-service priority register (ISPR) The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt signal request is set to 1 and remains set while the interrupt is serviced.
Page 691: Maskable Interrupt Status Flag (Id)
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.3.7 Maskable interrupt status flag (ID) The ID flag controls the maskable interrupt’s operating state, and stores control information regarding enabling or disabling of interrupt requests. The ID flag is allocated to the PSW. This flag is set to 00000020H after reset. After rest: 00000020H NP EP ID SAT CY OV...
Page 692: External Interrupt Request Input Pins (Intp0 To Intp7)
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.4 External Interrupt Request Input Pins (INTP0 to INTP7) 17.4.1 Noise elimination (1) Noise elimination of INTP0, INTP1 (V850E/IA4 only), INTP2 to INTP5, and INTP7 pins The INTP0, INTP1 (V850E/IA4 only), INTP2 to INTP5, and INTP7 pins incorporate a noise eliminator that uses analog delay.
Page 693: Edge Detection
17.4.2 Edge detection The valid edges of the INTPn pin can be selected by program (V850E/IA3: n = 0, 2 to 7, V850E/IA4: n = 0 to 7). The edge that can be selected as the valid edge is one of the following.
Page 694 Therefore, be sure to clear the INTF0n and INTR0n bits to 00, and then set the port mode (V850E/IA3: n = 0, 2 to 7, V850E/IA4: n = 0 to 7). After reset: 00H Address: FFFFFC20H <7>...
Page 695: Software Exception
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.5 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. 17.5.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine.
Page 696: Restore
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.5.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 1. <2>...
Page 697: Exception Status Flag (Ep)
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.5.3 Exception status flag (EP) The EP flag is a status flag used to indicate that exception processing is in progress. This flag is set when an exception occurs. The EP flag is allocated to the PSW. This flag is set to 00000020H after reset.
Page 698: Exception Trap
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850E/IA3 and V850E/IA4, an illegal opcode trap (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 17.6.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B, and a sub-opcode (bit 16) of 0B.
Page 699 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 17-10. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC Restored PC DBPSW PSW.NP PSW.EP PSW.ID 00000060H Exception processing (2) Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC.
Page 700: Debug Trap
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.6.2 Debug trap The debug trap is an exception that can be acknowledged anytime and is generated by execution of the DBTRAP instruction. When the debug trap is generated, the CPU performs the following processing. (1) Operation <1>...
Page 701 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restore Recovery from a debug trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2>...
Page 702: Multiple Interrupt Servicing Control
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.7 Multiple Interrupt Servicing Control Multiple interrupt servicing control is a process by which an interrupt request that is currently being serviced can be interrupted during servicing if there is an interrupt request signal with a higher priority level, and the higher priority interrupt request signal is acknowledged and serviced first.
Page 703 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Generation of exception in servicing program Servicing program of maskable interrupt or exception • EIPC saved to memory or register • EIPSW saved to memory or register • TRAP instruction ← Exception such as TRAP instruction acknowledged. •...
Page 704: Interrupt Response Time Of Cpu
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.8 Interrupt Response Time of CPU Except the following cases, the interrupt response time of the CPU is 4 clocks minimum. To input interrupt request signals successively, input the next interrupt request signal at least 4 clocks after the preceding interrupt. •...
Page 705: Periods In Which Cpu Does Not Acknowledge Interrupts
Note that if a port is set to external interrupt input (INTPn), the timer/counter-related interrupt and A/D converter- related interrupt, which are alternate functions, do not occur (V850E/IA3: n = 0, 2 to 7, V850E/IA4: n = 0 to 7).
Page 706: Chapter 18 Standby Function
CHAPTER 18 STANDBY FUNCTION 18.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 18-1. Table 18-1.
Page 707 CHAPTER 18 STANDBY FUNCTION Figure 18-1. Status Transition Normal operation mode Note 5 Note 6 Note 5 Note 5 Setting of HALT mode Setting of STOP mode Setting of IDLE mode Note 1 Interrupt request Note 3 Interrupt request Wait for stabilization of Wait for stabilization of Wait for stabilization of (oscillation) and PLL...
Page 708: Control Registers
CHAPTER 18 STANDBY FUNCTION 18.2 Control Registers (1) Power save control register (PSC) The PSC register is an 8-bit register that controls the standby function. The STB bit of this register is used to specify the standby mode. This register is a special register (see 3.4.8 Special registers). This register can be written only by a combination of specific sequences.
Page 709 CHAPTER 18 STANDBY FUNCTION (2) Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation in the software standby mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF820H <...
Page 710: Halt Mode
CHAPTER 18 STANDBY FUNCTION 18.3 HALT Mode 18.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. When HALT mode is set, clock supply is stopped to the CPU only. The clock generator and PLL continue operating.
Page 711 CHAPTER 18 STANDBY FUNCTION (2) Releasing HALT mode by RESET pin input or WDTRES signal generation The same operation as the normal reset operation is performed. Table 18-3. Operation Status in HALT Mode Setting of HALT Mode Operation Status Item Clock generator, PLL Operates System clock (f...
Page 712: Idle Mode
CHAPTER 18 STANDBY FUNCTION 18.4 IDLE Mode 18.4.1 Setting and operation status The IDLE mode is set by clearing (0) the PSMR.PSM0 bit and setting (1) the PSC.STB bit in the normal operation mode. In the IDLE mode, the clock generator and PLL continue operation but clock supply to the CPU and other on-chip peripheral functions stops.
Page 713 CHAPTER 18 STANDBY FUNCTION (2) Releasing IDLE mode by RESET pin input The same operation as the normal reset operation is performed. Table 18-5. Operation Status in IDLE Mode Setting of IDLE Mode Operation Status Item Clock generator, PLL Operates System clock (f Stops supply Stops operation...
Page 714: Stop Mode
CHAPTER 18 STANDBY FUNCTION 18.5 STOP Mode 18.5.1 Setting and operation status The STOP mode is set by setting (1) the PSMR.PSM0 bit and setting (1) the PSC.STB bit in the normal operation mode. In the STOP mode, the clock generator stops operation. Clock supply to the CPU and the on-chip peripheral functions is stopped.
Page 715 CHAPTER 18 STANDBY FUNCTION (2) Releasing STOP mode by RESET pin input The same operation as the normal reset operation is performed. Table 18-7. Operation Status in STOP Mode Setting of STOP Mode Operation Status Item Clock generator, PLL Stops operation System clock (f Stops supply Stops operation...
Page 716: Securing Oscillation Stabilization Time
CHAPTER 18 STANDBY FUNCTION 18.6 Securing Oscillation Stabilization Time When the STOP mode is released, the oscillation stabilization time set by the OSTS register elapses. The oscillation stabilization time is the reset value of the OSTS register, 2 (2.048 ms at f = 8 MHz), if the STOP mode is released by RESET pin input.
Page 717: Chapter 19 Reset Functions
• System reset signal (WDTRES) generation by watchdog timer (WDT) overflow • Forced reset by on-chip debug function (DCU) and reset mask function (see CHAPTER 21 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).) 19.2 Configuration V850E/IA3, V850E/IA4 main block filter block RESET...
Page 718: Control Register
CHAPTER 19 RESET FUNCTIONS 19.3 Control Register (1) Reset source flag register (RESF) The RESF register is an 8-bit register that indicates occurrence of a reset request from the watchdog timer (WDT). The RESF. RESFH4 bit of this register is set to 1 when the internal reset source signal from WDT is asserted. The RESFH4 bit is cleared by reset via the RESET pin or by a bit manipulation instruction or store instruction (writing 0 to the RESFH4 bit).
Page 719: Operation
19.4 Operation (1) Reset operation by RESET pin input When a low level is input to the RESET pin, the V850E/IA3 and V850E/IA4 are reset, and each hardware unit is initialized to a specific status. The oscillator continues oscillation even while a low level is input to the RESET pin but the oscillation mode is...
Page 720 CHAPTER 19 RESET FUNCTIONS The reset operation by RESET pin input is illustrated below. Figure 19-1. Reset Operation by RESET Pin Input Operation at f Operation at f RESET (input) Analog delay Analog delay Analog delay Analog delay (eliminated as noise) (eliminated as noise) Oscillation stabilization time + PLL lockup time Caution After release of reset, make sure that the oscillation stabilization time (1.024 ms (at f...
Page 721 CHAPTER 19 RESET FUNCTIONS The timing and pin status at power-on are shown below. Figure 19-2. Timing and Pin Status at Power-On 2.5 V RESET (input) Undefined During reset Reset release Undefined Normal output Note (output) Undefined Normal output μ Note PD70F3186 (V850E/IA4) only Remark...
Page 722: Chapter 20 Rom Correction Function
CHAPTER 20 ROM CORRECTION FUNCTION 20.1 Overview The ROM correction function is used to replace part of the program in the mask ROM or flash memory with the program of the internal RAM. By using this function, program bugs found in the mask ROM or flash memory can be corrected. The correction address can be specified at up to four places by the ROM correction function.
Page 723: Control Registers
CHAPTER 20 ROM CORRECTION FUNCTION 20.2 Control Registers (1) Correction address registers 0 to 3 (CORAD0 to CORAD3) The CORAD0 to CORAD3 registers set the first address of the correction program. The program can be corrected at up to four places because four CORADn registers are provided (n = 0 to 3). The CORADn register can be read or written in 32-bit units.
Page 724 CHAPTER 20 ROM CORRECTION FUNCTION (2) Correction control register (CORCN) This register disables or enables the correction operation at the address set by each CORADn register (n = 0 to 3). Each channel can be enabled or disabled by this register. This register can be read or written in 8-bit or 1-bit units.
Page 725: Rom Correction Operation And Program Flow
4. Use of ROM correction is prohibited if self-programming is performed in the PD70F3184 (V850E/IA3) or 70F3186 (V850E/IA4). 5. ROM correction cannot be used when DMA transfer is executed in the internal RAM (do not execute DMA transfer in the internal RAM and instructions in the internal RAM at the same time).
Page 726 CHAPTER 20 ROM CORRECTION FUNCTION Figure 20-2. ROM Correction Operation and Program Flow Reset & start Perform initial settings of microcontroller Set CORADn register Read data for setting ROM Load program for judgment correction from external memory of ROM correction and correction codes Set CORCN register CORENn bit = 1?
Page 727: Chapter 21 On-Chip Debug Function (On-Chip Debug Unit)
Caution The debug function explained in this chapter is the function that can be realized by using the μ PD70F3186 (V850E/IA4), the NEC Electronics’ QB-V850MINI (on-chip debug emulator), and the debugger ID850QB. When using a partner manufacturer’s on-chip debug emulator, refer to the manual for the debugger used.
Page 728 CHAPTER 21 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT) (7) Debug monitor function During debugging, a memory space for debugging that differs from the user memory space is used (background monitor format). The user program can be executed starting from any address. While execution of the user program is stopped, the user resources (such as memory and I/O) can be read or written, and the user program can be downloaded.
Page 729: Rom Security Function
21.1.3 ROM security function (1) Security ID The flash memory versions of the V850E/IA3 and V850E/IA4 perform authentication using a 10-byte ID code to prevent the contents of the flash memory from being read by an unauthorized person during on-chip debugging by the on-chip debug emulator.
Page 730 CHAPTER 21 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT) (2) Setting How to set the ID code as shown in Table 21-1 is shown below. When the ID code is set as shown in Table 21-1, the ID code input in the configuration dialog box of the ID850QB is “123456789ABCDEF123D4”...
Page 731: Selecting On-Chip Debug Function And Port Function (Including Alternate Functions)731
CHAPTER 21 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT) 21.2 Selecting On-Chip Debug Function and Port Function (Including Alternate Functions) μ In the PD70F3186 (V850E/IA4), pins P50 to P52 also function as on-chip debug pins. The on-chip debug function or port function (including the alternate functions) can be selected by using the level of the DRST pin, as shown in the table below.
Page 732: Connection With On-Chip Debug Emulator
CHAPTER 21 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT) 21.3 Connection with On-Chip Debug Emulator To connect an on-chip debug emulator, it is necessary to mount an emulator connector and circuit for connection on the target system. Select either the KEL connector, MICTOR connector (Part number: 2-767004-2, distributor: Tyco Electronics AMP K.K.), or 2.54 mm pitch 20-pin general-purpose connector as the emulator connector.
Page 733: Kel Connector
CHAPTER 21 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT) 21.3.1 KEL connector <R> When the QB-V850MINI is used, use of the following connector is recommended. Part number • 8830E-026-170S: Straight type • 8830E-026-170L: Right-angle type <R> It is necessary to mount an emulator and circuit for connection on the target system. <R>...
Page 734 CHAPTER 21 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT) Figure 21-2. Pin Configuration of Emulator Connector (on Target System Side) B13 A13 B12 A12 (Top View) Caution Design the board based on the dimensions of the connector when actually mounting the connector on the board.
Page 735 CHAPTER 21 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT) (2) Pin functions The following table shows the pin functions of the emulator connector (on the target system side). <R> Table 21-2. Pin Functions of Connector for QB-V850MINI (on Target System Side) Pin No.
Page 736 CHAPTER 21 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT) (3) Recommended circuit example The following figure shows an example of the recommended circuit of the emulator connector (on the target system side). μ Figure 21-3. Example of Recommended Connection of PD70F3186 (V850E/IA4) and KEL Connector μ...
Page 737: Cautions
CHAPTER 21 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT) 21.4 Cautions (1) The flash memory of the device used in debugging is rewritten during debugging, so the number of flash memory rewrites cannot be guaranteed. Therefore, do not use the device used in debugging for a mass production product.
Page 738: Chapter 22 Flash Memory
Flash memory versions are commonly used in the following development environments and mass production applications. For altering software after the V850E/IA3 and V850E/IA4 is soldered onto the target system. For data adjustment when starting mass production. For differentiating software according to the specification in small scale production of various models.
Page 739: Memory Configuration
CHAPTER 22 FLASH MEMORY 22.2 Memory Configuration The 256 KB internal flash memory area is divided into 4 blocks and can be programmed/erased in block units. All the blocks can also be erased at once. When the boot swap function is used, the physical memory located at the addresses of blocks 0 and 1 is replaced by the physical memory located at the addresses of blocks 2 and 3.
Page 740: Functional Overview
CHAPTER 22 FLASH MEMORY 22.3 Functional Overview The internal flash memory of the V850E/IA3 and V850E/IA4 can be rewritten by using the rewrite function of the dedicated flash memory programmer, regardless of whether the V850E/IA3 and V850E/IA4 have already been mounted on the target system or not (on-board/off-board programming).
Page 741 CHAPTER 22 FLASH MEMORY Table 22-2. Basic Functions Support (√: Supported, ×: Not supported) Function Functional Outline On-Board/Off-Board Self Programming Programming √ √ Block erasure The contents of specified memory blocks are erased. √ × Chip erasure The contents of the entire memory area are erased all at once.
Page 742 CHAPTER 22 FLASH MEMORY Table 22-4. Security Setting <R> Function Erase, Write, Read Operations When Each Security Is Set Notes on Security Setting (√: Executable, ×: Not Executable, −: Not Supported) On-Board/ Self Programming On-Board/ Self Off-Board Programming Programming Off-Board Programming Block erase command: ×...
Page 743 CHAPTER 22 FLASH MEMORY (1) Security setting by PG-FP4 and PG-FP5 (Security flag settings) <R> When disabling the read command (Disable Read), to raise the security level, it is recommended to also disable the block erase command (Disable Block Erase) and program command (Disable Program). Furthermore, when rewriting program is not necessary similarly to the mask ROM versions, additionally disable the chip erase command (Disable Chip Erase).
Page 744: Rewriting By Dedicated Flash Memory Programmer
22.4 Rewriting by Dedicated Flash Memory Programmer The flash memory can be rewritten by using a dedicated flash memory programmer after the V850E/IA3 and V850E/IA4 are mounted on the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (FA series).
Page 745: Communication Mode
CHAPTER 22 FLASH MEMORY 22.4.2 Communication mode Communication between the dedicated flash memory programmer and the V850E/IA3 and V850E/IA4 is performed via serial communication using UARTA0 or CSIB0. Remark The recommended target connector is as follows. • 7616-5002SC (Sumitomo 3M Ltd.) The following figure outlines the connector (when viewed from the connector insertion side).
Page 746 − Not used Notes 1. In the V850E/IA3 and V850E/IA4, external clock input is prohibited. Mount the resonator on board. Connect to FLMD1 or GND via a resistor. Caution Connect the PLLSIN pin as follows in accordance with the range of the PLL output clock frequency (f •...
Page 747 − Not used Notes 1. In the V850E/IA3 and V850E/IA4, external clock input is prohibited. Mount the resonator on board. Connect to FLMD1 or GND via a resistor. Caution Connect the PLLSIN pin as follows in accordance with the range of the PLL output clock frequency (f •...
Page 748 − Not used Notes 1. In the V850E/IA3 and V850E/IA4, external clock input is prohibited. Mount the resonator on board. Connect to FLMD1 or GND via a resistor. Caution Connect the PLLSIN pin as follows in accordance with the range of the PLL output clock frequency (f •...
Page 749: Flash Memory Control
CHAPTER 22 FLASH MEMORY 22.4.3 Flash memory control The following shows the procedure for manipulating the flash memory. <R> Figure 22-4. Procedure for Manipulating Flash Memory Start Switch to flash memory programming mode Supplies FLMD0 pulse Select communication system Manipulate flash memory End? User’s Manual U16543EJ4V0UD...
Page 750: Selection Of Communication Mode
22.4.4 Selection of communication mode In the V850E/IA3 and V850E/IA4, the communication mode is selected by inputting pulses (11 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash memory programmer.
Page 751: Communication Commands
V850E/IA3, V850E/IA4 memory programmer The following shows the commands for flash memory control in the V850E/IA3 and V850E/IA4. All of these commands are issued from the dedicated flash memory programmer, and the V850E/IA3 and V850E/IA4 perform the processing corresponding to the commands.
Page 752: Pin Connection
FLMD0 pin via port control, etc., before writing to the flash memory. For details, see 22.5.5 (1) FLMD0 pin. Figure 22-7. FLMD0 Pin Connection Example V850E/IA3, V850E/IA4 Dedicated flash memory programmer connection pin FLMD0 Pull-down resistor (R FLMD0 User’s Manual U16543EJ4V0UD...
Page 753 0 V must be input to the FLMD1 pin. The following shows an example of the connection of the FLMD1 pin. Figure 22-8. FLMD1 Pin Connection Example V850E/IA3, V850E/IA4 FLMD1 Other device...
Page 754 (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. Figure 22-9. Conflict of Signals (Serial Interface Input Pin) V850E/IA3, V850E/IA4 Dedicated flash memory programmer connection pins...
Page 755 Dedicated flash memory programmer connection pin Other device Input pin In the flash memory programming mode, if the signal the V850E/IA3, V850E/IA4 output affects the other device, isolate the signal on the other device side. V850E/IA3, V850E/IA4 Dedicated flash memory...
Page 756 Therefore, do not input signals other than the reset signals from the dedicated flash memory programmer. Figure 22-11. Conflict of Signals (RESET Pin) V850E/IA3, V850E/IA4 Dedicated flash memory programmer connection pin Conflict of signals...
Page 757 CHAPTER 22 FLASH MEMORY Connect the reset pin of the dedicated flash memory programmer to the RESET pin of the V850E/IA3 and V850E/IA4 at the location where the two reset signals are the same. <R> = 5.0 V V850E/IA3, V850E/IA4...
Page 758 CHAPTER 22 FLASH MEMORY (5) Port pins When the system shifts to the flash memory programming mode, all the pins that are not used for flash memory programming are in the same status as that immediately after reset. If the external device connected to each port does not recognize the status of the port immediately after reset, pins require appropriate processing, such as connecting to EV via a resistor or connecting to EV...
Page 759: Rewriting By Self Programming
22.5.1 Overview The V850E/IA3 and V850E/IA4 support a flash macro service that allows the user program to rewrite the internal flash memory by itself. By using this interface and a self programming library that is used to rewrite the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal RAM or external memory.
Page 760: Features
Instructions cannot be fetched from the flash memory during self programming. Conventionally, therefore, a user handler written to the flash memory could not be used even if an interrupt occurred. With the V850E/IA3 and V850E/IA4, a user handler can be registered to an entry RAM area by using a library function, so that interrupt servicing can be performed by internal RAM or external memory execution.
Page 761: Standard Self Programming Flow
CHAPTER 22 FLASH MEMORY 22.5.3 Standard self programming flow The entire processing to rewrite the flash memory by flash self programming is illustrated below. <R> Figure 22-14. Standard Self Programming Flow (a) Rewriting at once (b) Rewriting in block units Flash memory manipulation Flash memory manipulation Flash environment...
Page 762: Flash Functions
Remark For details, refer to the V850 Series Flash Memory Self Programming (Single Power Supply Flash Memory) User’s Manual. Contact an NEC Electronics sales representative for the above manual. 22.5.5 Pin processing (1) FLMD0 pin The FLMD0 pin is used to set the operation mode when reset is released and to protect the flash memory from being written during self rewriting.
Page 763: Internal Resources Used
Note For details, refer to the V850 Series Flash Memory Self Programming (Single Power Supply Flash Memory) User’s Manual. Contact an NEC Electronics sales representative for the above manual. User’s Manual U16543EJ4V0UD...
Page 764: Chapter 23 Electrical Specifications (V850E/Ia3)
CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.5 to +3.6 Supply voltage = CV −0.5 to +0.5 = CV = EV = AV −0.5 to +6.5 = AV −0.5 to +0.5...
Page 765 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) Cautions 1. Do not directly connect the output pins (or I/O pins in the output state) of IC products to other output pins (including I/O pins in the output state), power supply pins such as V...
Page 766 The oscillation voltage and oscillation frequency indicate only oscillator characteristics, therefore use the V850E/IA3 within the DC characteristics and AC characteristics for internal operation conditions. User’s Manual U16543EJ4V0UD...
Page 767 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) DC Characteristics = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.0 to 5.5 V, V = AV = CV = EV = 0 V) Note 1 Parameter...
Page 768 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) Data Retention Characteristics = −40 to +85°C, V STOP mode (T = AV = CV = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention voltage STOP mode , CV DDDR , EV μ...
Page 769 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) AC Characteristics AC Test Input Measurement Points , EV Measurement points AC Test Output Measurement Points Measurement points Load Conditions (Device under measurement) = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
Page 770 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) Output Signal Timing = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.0 to 5.5 V, V = AV = CV = EV = 0 V) Parameter Symbol Conditions MIN.
Page 771 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) Timer Timing = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.0 to 5.5 V, V = AV = CV = EV = 0 V, = 50 pF)
Page 772 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) CSIB Timing (1) Master mode = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.0 to 5.5 V, V = AV = CV = EV = 0 V,...
Page 773 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) CSIB timing when CBnCKP and CBnDAP bits of CBnCTL1 register = 00 <18>, <24> <19>, <25> <19>, <25> SCKBn (I/O) <20>, <21>, <26> <27> SIBn (input) Input data <22>, <28> <23>, <29> SOBn (output) Output data Remarks 1.
Page 774 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) CSIB timing when CBnCKP and CBnDAP bits of CBnCTL1 register = 10 <18>, <24> <19>, <25> <19>, <25> SCKBn (I/O) <20>, <21>, <26> <27> SIBn (input) Input data <22>, <28> <23>, <29> Output data SOBn (output) Remarks 1.
Page 775 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) High-Impedance Control Timing = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.0 to 5.5 V, V = AV = CV = EV = 0 V, C = 50...
Page 776 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) Characteristics of A/D Converters 0, 1 = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.5 to 5.5 V, V = AV = CV = EV = 0 V)
Page 777 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) Characteristics of A/D Converter 2 = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.5 to 5.5 V, V = AV = CV = EV = 0 V)
Page 778 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) Operational Amplifier Characteristics = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.5 to 5.5 V, V = AV = CV = EV = 0 V) Parameter Symbol Conditions MIN.
Page 779 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) Comparator Characteristics = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.5 to 5.5 V, V = AV = CV = EV = 0 V) Parameter Symbol Conditions MIN.
Page 780 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) Supply Voltage Application/Cutoff Timing = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.0 to 5.5 V, V = AV = CV = EV = 0 V, = 50 pF)
Page 781 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) Supply Voltage Cutoff Timing , AV DEVDD 2.5 V , CV Cautions 1. There are no regulations for the voltage level and time of 2.5 V V and CV , and 5 V EV and AV in the process of natural discharge after power supply cutoff.
Page 782: Chapter 24 Electrical Specifications (V850E/Ia4)
CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.5 to +3.6 Supply voltage = CV −0.5 to +0.5 = CV = EV = AV −0.5 to +6.5 = AV −0.5 to +0.5 = CV = EV = AV...
Page 783 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) Cautions 1. Do not directly connect the output pins (or I/O pins in the output state) of IC products to other output pins (including I/O pins in the output state), power supply pins such as V and EV , or GND pin.
Page 784 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) Clock Oscillator Characteristics = −40 to +85°C, CV = 2.3 to 2.7 V, V = AV = CV = EV = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Ceramic Oscillation /crystal frequency (f resonator Oscillation...
Page 785 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) DC Characteristics = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.0 to 5.5 V, V = AV = CV = EV = 0 V) (1/2) Parameter Symbol Conditions MIN.
Page 786 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) DC Characteristics = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.0 to 5.5 V, V = AV = CV = EV = 0 V) (2/2) Note 1 Parameter Symbol Conditions...
Page 787 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) Data Retention Characteristics = −40 to +85°C, V STOP mode (T = AV = CV = EV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention voltage STOP mode , CV DDDR , EV μ...
Page 788 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) AC Characteristics AC Test Input Measurement Points , EV Measurement points AC Test Output Measurement Points Measurement points Load Conditions (Device under measurement) = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
Page 789 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) Output Signal Timing = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.0 to 5.5 V, V = AV = CV = EV = 0 V) Parameter Symbol Conditions MIN.
Page 790 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) Timer Timing = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.0 to 5.5 V, V = AV = CV = EV = 0 V, = 50 pF) Parameter Symbol Conditions...
Page 791 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) CSIB Timing (1) Master mode = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.0 to 5.5 V, V = AV = CV = EV = 0 V, = 50 pF) Parameter Symbol...
Page 792 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) CSIB timing when CBnCKP and CBnDAP bits of CBnCTL1 register = 00 <18>, <24> <19>, <25> <19>, <25> SCKBn (I/O) <20>, <21>, <26> <27> SIBn (input) Input data <22>, <28> <23>, <29> SOBn (output) Output data Remarks 1.
Page 793 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) CSIB timing when CBnCKP and CBnDAP bits of CBnCTL1 register = 10 <18>, <24> <19>, <25> <19>, <25> SCKBn (I/O) <20>, <21>, <26> <27> SIBn (input) Input data <22>, <28> <23>, <29> Output data SOBn (output) Remarks 1.
Page 794 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) High-Impedance Control Timing = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.0 to 5.5 V, V = AV = CV = EV = 0 V, = 50 pF) Parameter Symbol Conditions...
Page 795 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) Characteristics of A/D Converters 0, 1 = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.5 to 5.5 V, V = AV = CV = EV = 0 V) Parameter Symbol Conditions...
Page 796 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) Characteristics of A/D Converter 2 = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.5 to 5.5 V, V = AV = CV = EV = 0 V) Parameter Symbol Conditions...
Page 797 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) Operational Amplifier Characteristics = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.5 to 5.5 V, V = AV = CV = EV = 0 V) Parameter Symbol Conditions MIN.
Page 798 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) Comparator Characteristics = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.5 to 5.5 V, V = AV = CV = EV = 0 V) Parameter Symbol Conditions MIN.
Page 799 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) Supply Voltage Application/Cutoff Timing = −40 to +85°C, V = CV = 2.3 to 2.7 V, AV = EV = 4.0 to 5.5 V, V = AV = CV = EV = 0 V, = 50 pF) Parameter Symbol Conditions...
Page 800 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) (b) Power supply sequence recommended condition 2 , AV DVDD 2.5 V , CV DRES2 Undefined During reset Reset release RESET (input) Stabilization time secured Undefined Normal output Note (output) Undefined Normal output μ Note PD70F3186 only Supply Voltage Cutoff Timing , AV...
Page 801: Chapter 25 Package Drawings
CHAPTER 25 PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.13 mm of 17.20±0.20 its true position (T.P.) at maximum material condition. 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20...
Page 802 CHAPTER 25 PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 16.00±0.20 its true position (T.P.) at maximum material condition. 14.00±0.20 14.00±0.20 16.00±0.20 1.00 1.00 0.22 +0.05 −0.04 0.08...
Page 803 CHAPTER 25 PACKAGE DRAWINGS 100-PIN PLASTIC QFP (14x20) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.15 mm of 23.6±0.4 its true position (T.P.) at maximum material condition. 20.0±0.2 14.0±0.2 17.6±0.4 0.30±0.10 0.15 0.65 (T.P.) 1.8±0.2 0.8±0.2 0.15 +0.10...
Page 804: Chapter 26 Recommended Soldering Conditions
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Remarks 1. Products with -A at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended, please contact an NEC Electronics sales representative.
Page 805: Appendix A Cautions
APPENDIX A CAUTIONS A.1 Restriction on Conflict Between sld Instruction and Interrupt Request A.1.1 Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1>...
Page 806: Appendix B Register Index
APPENDIX B REGISTER INDEX (1/9) Symbol Name Unit Page AD0IC Interrupt control register INTC AD1IC Interrupt control register INTC AD2IC Interrupt control register INTC ADA0CR0 A/D0 conversion result register 0 ADC0 ADA0CR0H A/D0 conversion result register 0H ADC0 ADA0CR1 A/D0 conversion result register 1 ADC0 ADA0CR1H A/D0 conversion result register 1H...
Page 807 APPENDIX B REGISTER INDEX (2/9) Symbol Name Unit Page ADA1M2 A/D converter 1 mode register 2 ADC1 ADA1S A/D converter 1 channel specification register ADC1 ADA2CR0 A/D2 conversion result register 0 ADC2 ADA2CR0H A/D2 conversion result register 0H ADC2 ADA2CR1 A/D2 conversion result register 1 ADC2 ADA2CR1H...
Page 808 APPENDIX B REGISTER INDEX (3/9) Symbol Name Unit Page CC0IC0 Interrupt control register INTC CC0IC1 Interrupt control register INTC CC100 Capture/compare register 100 Timer CC101 Capture/compare register 101 Timer CC110 Capture/compare register 110 Timer CC111 Capture/compare register 111 Timer CC1IC0 Interrupt control register INTC CC1IC1...
Page 809 APPENDIX B REGISTER INDEX (4/9) Symbol Name Unit Page DCHC1 DMA channel control register 1 DMAC DCHC2 DMA channel control register 2 DMAC DCHC3 DMA channel control register 3 DMAC DDA0H DMA destination address register 0H DMAC DDA0L DMA destination address register 0L DMAC DDA1H DMA destination address register 1H...
Page 810 APPENDIX B REGISTER INDEX (5/9) Symbol Name Unit Page IMR3L Interrupt mask register 3L INTC Internal memory size switching register INTF0 External interrupt falling edge specification register 0 INTC INTPNRC External interrupt noise elimination control register INTC 155, 692 INTR0 External interrupt rising edge specification register 0 INTC ISPR...
Page 811 APPENDIX B REGISTER INDEX (6/9) Symbol Name Unit Page Port 5 mode register Port PMC0 Port 0 mode control register Port PMC1 Port 1 mode control register Port PMC2 Port 2 mode control register Port PMC3 Port 3 mode control register Port PMC4 Port 4 mode control register...
Page 812 APPENDIX B REGISTER INDEX (7/9) Symbol Name Unit Page TP0CTL1 TMP0 control register 1 Timer TP0IOC0 TMP0 I/O control register 0 Timer TP0IOC1 TMP0 I/O control register 1 Timer TP0IOC2 TMP0 I/O control register 2 Timer TP0OPT0 TMP0 option register 0 Timer TP0OVIC Interrupt control register...
Page 813 APPENDIX B REGISTER INDEX (8/9) Symbol Name Unit Page TQ0CCR3 TMQ0 capture/compare register 3 Timer TQ0CNT TMQ0 counter read buffer register Timer TQ0CTL0 TMQ0 control register 0 Timer TQ0CTL1 TMQ0 control register 1 Timer TQ0DTC TMQ0 dead-time compare register Timer TQ0IOC0 TMQ0 I/O control register 0 Timer...
Page 814 APPENDIX B REGISTER INDEX (9/9) Symbol Name Unit Page UA0TX UARTA0 transmit data register UARTA0 UA1CTL0 UARTA1 control register 0 UARTA1 UA1CTL1 UARTA1 control register 1 UARTA1 UA1CTL2 UARTA1 control register 2 UARTA1 UA1OPT0 UARTA1 option control register 0 UARTA1 UA1REIC Interrupt control register INTC...
Page 815: Appendix C Instruction Set List
APPENDIX C INSTRUCTION SET LIST C.1 Conventions (1) Register symbols used to describe operands Register Symbol Explanation reg1 General-purpose registers: Used as source registers. reg2 General-purpose registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General-purpose registers: Used mainly to store the remainders of division results and the higher order 32 bits of multiplication results.
Page 816 APPENDIX C INSTRUCTION SET LIST (3) Register symbols used in operations Register Symbol Explanation ← Input for GR [ ] General-purpose register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length. load-memory (a, b) Read size b data from address a.
Page 817 APPENDIX C INSTRUCTION SET LIST (5) Register symbols used in flag operations Identifier Explanation (Blank) No change Clear to 0 Set or cleared in accordance with the results. Previously saved values are restored. (6) Condition codes Condition Name Condition Code Condition Formula Explanation (cond)
Page 818: Instruction Set (In Alphabetical Order)
APPENDIX C INSTRUCTION SET LIST C.2 Instruction Set (in Alphabetical Order) (1/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 r r rr r0 01 11 0 RRRRR GR[reg2]←GR[reg2]+GR[reg1] × × ×...
Page 819 APPENDIX C INSTRUCTION SET LIST (2/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT DBTRAP 1111100001000000 DBPC←PC+2 (returned PC) DBPSW←PSW PSW.NP←1 PSW.EP←1 PSW.ID←1 PC←00000060H 0000011111100000 PSW.ID←1 0000000101100000 DISPOSE imm5,list12 0 0 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend(imm5 logically shift left by 2) LLLLLLLLLLL00000 GR[reg in list12]←Load-memory(sp,Word)
Page 820 APPENDIX C INSTRUCTION SET LIST (3/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT LD.H disp16[reg1],reg2 rrrrr111001RRRRR adr←GR[reg1]+sign-extend(disp16) Note ddddddddddddddd0 GR[reg2]←sign-extend(Load-memory(adr,Halfword)) Note 8 LDSR reg2,regID rrrrr111111RRRRR SR[regID]←GR[reg2] Other than regID = PSW 0000000000100000 × × × ×...
Page 821 APPENDIX C INSTRUCTION SET LIST (4/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × reg1,reg2 r r rr r0 01 00 0 RRRRR GR[reg2]←GR[reg2]OR GR[reg1] × × imm16,reg1,reg2 r r rr r1 10 10 0 RRRRR GR[reg2]←GR[reg1]OR zero-extend(imm16) i i i i i i i i i i i i i i i i PREPARE...
Page 822 APPENDIX C INSTRUCTION SET LIST (5/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16) dddddddddddddddd Z flag←Not (Load-memory-bit(adr,bit#3)) Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,1) × reg2,[reg1] r r rr r1 11 11 1 RRRRR adr←GR[reg1] Z flag←Not(Load-memory-bit(adr,reg2)) 0000000011100000...
Page 823 APPENDIX C INSTRUCTION SET LIST (6/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 r r rr r0 01 10 1 RRRRR GR[reg2]←GR[reg2]–GR[reg1] × × × × SUBR reg1,reg2 r r rr r0 01 10 0 RRRRR GR[reg2]←GR[reg1]–GR[reg2] SWITCH reg1 00000000010RRRRR adr←(PC+2) + (GR [reg1] logically shift left by 1)
Page 824 APPENDIX C INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. r r r r r = regID specification RRRRR = reg2 specification...
Page 825: Appendix D Revision History
APPENDIX D REVISION HISTORY D.1 Major Revisions in This Edition (1/3) Page Description Throughout Addition of PG-FP5 p.36 Addition of description to 2.1 (1) Port pins p.50 Modification of description in Table 3-2 System Register Numbers p.55 Modification of description in 3.2.2 (6) Exception/debug trap status saving registers (DBPC, DBPSW) p.74 Modification of description in 3.4.7 On-chip peripheral I/O registers p.114...
Page 826 APPENDIX D REVISION HISTORY (2/3) Page Description p.274 Addition of description to Table 7-1 TMQn Overview p.281 Modification of description in 7.4 (3) TMQn I/O control register 0 (TQnIOC0) p.297 Modification of description in 7.6 (1) (a) Counter start operation pp.305 to 307 Modification of description in Figure 7-9 Register Setting for Interval Timer Mode Operation p.308...
Page 827 Modification of Figure 22-14 Standard Self Programming Flow p.762 Modification of description in Table 22-11 Flash Function List p.772 Modification of description in CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) CSIB Timing p.791 Modification of description in CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4) CSIB Timing User’s Manual U16543EJ4V0UD...
Page 828: Revision History Up To Previous Edition
Applied to: μ 2nd edition Addition of PD703186 Throughout Modification of pin configuration of pin 20 in 1.2.4 Pin configuration (V850E/IA3) CHAPTER 1 INTRODUCTION Modification of description in 2.2 Pin I/O Circuits and Recommended Connection of CHAPTER 2 Unused Pins PIN FUNCTIONS Modification of description in 2.3 Pin I/O Circuits...
Page 829 APPENDIX D REVISION HISTORY (2/6) Edition Description Applied to: 2nd edition Addition of description in 10.1 Functional Overview CHAPTER 10 MOTOR CONTROL Addition of description to Figure 10-1 Block Diagram of Motor Control FUNCTION Addition of description to Figure 10-2 TMQn Option Modification of description in 10.3 (3) TMQn option register 2 (TQnOPT2) Addition of description to 10.3 (5) TMQn I/O control register 3 (TQnIOC3) Modification of description in 10.3 (6) High-impedance output control registers 00, 01,...
Page 830 APPENDIX D REVISION HISTORY (3/6) Edition Description Applied to: 2nd edition Modification of Figure 12-8 One-Shot Select 1-Buffer Mode Operation Timing (When CHAPTER 12 ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits = 10, ADA0M2.ADA0BS bit = 0, A/D CONVERTERS ADA0S.ADA0S2 to ADA0S.ADA0S0 bits = 001): V850E/IA4 0 AND 1 Modification of Figure 12-9 One-Shot Select 4-Buffer Mode Operation Timing (When ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits = 10, ADA0M2.ADA0BS bit = 1,...
Page 831 PD70F3186 (V850E/IA4) and KEL Connector CHIP DEBUG UNIT) Addition of description of (7) in 21.4 Cautions Modification of CHAPTER 22 FLASH MEMORY CHAPTER 22 FLASH MEMORY Addition of CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) (TARGET) CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) (TARGET)
Page 832 Addition of description to 3.4.9 System wait control register (VSWC) Addition of Caution in 4.6 (2) Noise elimination time select register 1n (NRC1n) CHAPTER 4 PORT (V850E/IA3: n = 0, V850E/IA4: n = 0, 1) FUNCTIONS Addition of Caution in 5.3 (6) Clock monitor mode register (CLM)
Page 833 APPENDIX D REVISION HISTORY (5/6) Edition Description Applied to: 3rd edition Addition of Caution in 10.4.3 Interrupt culling function CHAPTER 10 MOTOR CONTROL Addition of description in 10.4.5 (1) (b) Setting of TMQn register FUNCTION Modification of description in 11.4 Operation CHAPTER 11 WATCHDOG TIMER FUNCTIONS...
Page 834 Voltage Application/Cutoff Timing in CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) Addition of (b) Power supply sequence recommended condition 2 of Supply Voltage Application Timing in CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) Modification of description of Supply Voltage Cutoff Timing in CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3) Modification of specification of write current and erase current of Flash Memory μ...
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